Layout V2
Project | Open issues | State | Due date |
---|---|---|---|
wr2rf-vme | 1 | Open | expired on Feb 12, 2021 |
Unstarted Issues (open and unassigned)
1
- wr2rf-vme · Clock level at input of the IQ DACs too low.
Ongoing Issues (open and assigned)
0
Completed Issues (closed)
15
- wr2rf-vme · RF signal, distributed to trigger unit flip flops looks awful
- wr2rf-vme · Unconnected 5V power rail
- wr2rf-vme · Front panel cannot be fitted
- wr2rf-vme · Front-panel design and fabrication
- wr2rf-vme · OCXO sense goes to FPGA digital input
- wr2rf-vme · EXT REF I/O: PPS / 10M mux direction line needs opposite polarity
- wr2rf-vme · SFP LEDs are on when FPGA is not programmed
- wr2rf-vme · Cross check PCB labelling with front panel for the SFP indexing
- wr2rf-vme · V2: change EP195 delay line to SY89295UMG
- wr2rf-vme · Change electrolytic caps to more reliable series
- wr2rf-vme · Front panel: J9 very close to the front panel handle
- wr2rf-vme · Front panel middle fastening not aligned with PCB
- wr2rf-vme · The PCB labelling of the SFP connectors is inconsistent with front panel labelling
- wr2rf-vme · WRC eeprom are too small
- wr2rf-vme · Change license to CERN-OHL-W