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Schematics error
r19-tdc-del-a#5
· opened
Nov 08, 2016
by
Nicolas Boucquey
bug
0
updated
Feb 12, 2019
Limit the ports from which frames with given VID are accepted
wr-switch-hdl#5
· opened
Sep 16, 2016
by
Adam Wujek
dev
1
updated
Jul 15, 2019
unused pin PLL_PDn
fmc-adc-250m-16b-4cha#4
· opened
Sep 15, 2016
by
Piotr Miedzik
0
updated
Feb 12, 2019
Default values
wishbone-gen#4
· opened
Aug 25, 2016
by
Jan Pospisil
0
updated
Feb 12, 2019
Incorrect *_load_o behaviour?
wishbone-gen#5
· opened
Aug 25, 2016
by
Jan Pospisil
0
updated
Feb 12, 2019
MEM *_rd_i strobe is useless
wishbone-gen#6
· opened
Aug 25, 2016
by
Jan Pospisil
1
updated
Feb 12, 2019
SDB support
wishbone-gen#7
· opened
Aug 25, 2016
by
Jan Pospisil
0
updated
Feb 12, 2019
HMTL filed name formating
wishbone-gen#8
· opened
Aug 25, 2016
by
Jan Pospisil
1
updated
Feb 12, 2019
TYPE support for RAMs
wishbone-gen#9
· opened
Aug 25, 2016
by
Jan Pospisil
0
updated
Feb 12, 2019
No _i/o suffixes for record elements
wishbone-gen#10
· opened
Aug 25, 2016
by
Jan Pospisil
0
updated
Feb 12, 2019
Memory interface as a record in VHDL
wishbone-gen#11
· opened
Aug 25, 2016
by
Jan Pospisil
0
updated
Feb 12, 2019
Bad polarity of reset
wishbone-gen#12
· opened
Aug 25, 2016
by
Jan Pospisil
0
updated
Feb 12, 2019
Warning/Error on PASS_THROUGH & (access_bus = READ_WRITE)
wishbone-gen#13
· opened
Aug 25, 2016
by
Jan Pospisil
0
updated
Feb 12, 2019
CamelCase support
wishbone-gen#14
· opened
Aug 25, 2016
by
Jan Pospisil
0
updated
Feb 12, 2019
Several small changes suggestion
wishbone-gen#15
· opened
Aug 25, 2016
by
Jan Pospisil
1
updated
Feb 12, 2019
Register write/read strobe output
wishbone-gen#16
· opened
Jul 05, 2016
by
Tom Levens
0
updated
Feb 12, 2019
RAM access mode
wishbone-gen#17
· opened
Jul 03, 2016
by
Tom Levens
0
updated
Feb 12, 2019
8-bit memory byte write
wishbone-gen#18
· opened
Jul 03, 2016
by
Tom Levens
0
updated
Feb 12, 2019
String Element inside $display Verilog function will be misinterpreted as module
hdl-make#17
· opened
Jun 02, 2016
by
Andreas Bergmann
bug
2
updated
Mar 30, 2019
Relations missing for VHDL package to be used in system verilog
hdl-make#20
· opened
Jun 01, 2016
by
Nicolas Chevillot
bug
6
updated
Feb 12, 2019
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