Projects issues
https://ohwr.org/groups/project/-/issues
2019-02-12T10:43:02Z
https://ohwr.org/project/fmc-adc-130m-16b-4cha/issues/7
MMCX connector through hole pins can touch AMC front panel
2019-02-12T10:43:02Z
Daniel Tavares
MMCX connector through hole pins can touch AMC front panel
Some FMCs's through hole pins of MMCX connectors (ext. clock, trigger,
ref. clock) makes contact with AMC front panel.
Grzegorz Kasprowicz
Grzegorz Kasprowicz
https://ohwr.org/project/fmc-adc-130m-16b-4cha/issues/8
Wrong mechanical constraints for heatsink
2019-02-12T10:43:02Z
Daniel Tavares
Wrong mechanical constraints for heatsink
One of the heatsink's fins prevents the AMC handle to reach its limit.
Grzegorz Kasprowicz
Grzegorz Kasprowicz
https://ohwr.org/project/video-fpga-hdmi-dvi-ethernet/issues/4
solder mask opening
2019-02-12T11:01:48Z
Grzegorz Kasprowicz
solder mask opening
increase solder mask opening for HDMI connector
Grzegorz Kasprowicz
Grzegorz Kasprowicz
https://ohwr.org/project/amc-cpu-com6/issues/6
IC9: out2 swapped
2019-02-12T11:01:06Z
Grzegorz Kasprowicz
IC9: out2 swapped
Polarity of OUT2 is swapped. it is not used at the moment but it should
be reversed for future reference.
Grzegorz Kasprowicz
Grzegorz Kasprowicz
https://ohwr.org/project/amc-cpu-com6/issues/7
mPCIe support for SATA
2019-02-12T11:01:07Z
Grzegorz Kasprowicz
mPCIe support for SATA
route one of free SATA ports to the mini PCIe Express to support
on-board SSDs
Grzegorz Kasprowicz
Grzegorz Kasprowicz
https://ohwr.org/project/fmc-delay-1ns-8cha/issues/11
WR - "jumpless" switchover
2022-12-12T09:19:48Z
Tomasz Wlostowski
WR - "jumpless" switchover
Enabling the WR mode after a WR link failure causes a "jump" in the
card's time base, as the WR synchronization is re-done from scratch.
If the local time has not diverged too much (too much = a programmable
threshold), realign local time to WR with SoftPLL phase shifter only,
without touching PPS generator counters. This also applies to other
WR-enabled cards (TDC, ADC).
Tomasz Wlostowski
Tomasz Wlostowski
https://ohwr.org/project/spec/issues/31
V4 - Consider adding connector to supply a fan
2019-02-12T09:17:57Z
Erik van der Bij
V4 - Consider adding connector to supply a fan
To allow the possibility to add a fan to cool the FMC cards, consider
adding a (standard?) connector supplying 12V or even a PWM controlled
voltage.
https://ohwr.org/project/fmc-tdc-1ns-5cha-hw/issues/3
V3-1 - Add 10mm spacers,replace FMC front panel kit
2019-02-12T11:26:23Z
Erik van der Bij
V3-1 - Add 10mm spacers,replace FMC front panel kit
The standoffs are not in the BOM file
[EDA-02290-V3-1\_arrangement-mat](http://edms.cern.ch/file/1283037/1/EDA-02290-V3-1_arrangement-mat.pdf).
They are needed and even shown in
[EDA-02290-V3-1\_arrangement](http://edms.cern.ch/file/1283037/1/EDA-02290-V3-1_arrangement.pdf).
Replace the Xtech FMC front panel kit, the two spacers and the four
hexalobular screws by the following ELMA kit reference:
21M280-2
The ELMA 21M280-2 kit contains:
\- 1 FMC front panel
\- 1 O-ring
\- 2 10mm spacers
\- 8 M2.5x6mm screws
https://ohwr.org/project/fmc-tdc-1ns-5cha-hw/issues/4
V3-1 - Wrong Manufacturer PN in BOM for C5, C13-21, C27
2019-02-12T11:26:23Z
Nicolas Voumard
V3-1 - Wrong Manufacturer PN in BOM for C5, C13-21, C27
Actually, the design office did something wrong in the creation of the
capacitor TPSB476K006R0250 in the Altium library. There are two
manufacturer part number in the parameters of the component. In the
actual BOM, Manufacturer part number is "GENERIC
CTE3528-21\_47UF\_6.3V\_10%\_LESR0250" instead of "AVX
TPSB476K006R0250".
Nicolas Voumard
Nicolas Voumard
https://ohwr.org/project/hicce-fmc-128/issues/1
Get first revision started.
2019-02-12T10:16:49Z
Marcelo Magnasco
Get first revision started.
What is the mechanism through which we track the issues with the first
revision?
https://ohwr.org/project/wr-switch-hdl/issues/35
v4-dev - Time Aware Traffic Shaper (TATSU)
2019-02-12T09:51:47Z
Maciej Lipinski
v4-dev - Time Aware Traffic Shaper (TATSU)
Added unit which enables to block/allow particular output queues for a
give time, periodically, starting at a given UTC time
Maciej Lipinski
Maciej Lipinski
https://ohwr.org/project/wr-switch-hdl/issues/36
v4-dev - Topology Resolution Unit (TRU)
2019-02-12T09:51:47Z
Maciej Lipinski
v4-dev - Topology Resolution Unit (TRU)
Added unit which provides hardware support for software topology
resolution protocols (e.g.: LACP, RSTP)
Maciej Lipinski
Maciej Lipinski
https://ohwr.org/project/pts/issues/6
SPEC PTS: VHDL cleanup
2019-02-12T10:06:58Z
Evangelia Gousiou
SPEC PTS: VHDL cleanup
SPEC VHDL files are not in good structure; there should be files missing
and others with mistakes.
Some feedback from a company follows:
"..We have developed the SPEXI based on the SPEC design. To also adjust
the PTS environment from the SPEC to the SPEXI we need the complete VHDL
designs for the SPEC tests to resynthesize these projects.
Erik pointed us to the VHDL zip file on the GIT a few weeks ago. This
zip file is however not complete. And At least one project also contains
an error.
The first project which I opened was ‘test\_ddr’ (test07) of which I
found all source files but this resulted in the following error during
map:
ERROR:PhysDesignRules:2449 - The computed value for the VCO operating
frequency
of PLL\_ADV instance cmp\_gn4124\_core/cmp\_clk\_in/rx\_pll\_adv\_inst
is calculated
to be 320.000000 MHz. This falls below the operating range of the PLL
VCO
frequency for this device of 400.000000 - 1080.000000 MHz. Please
adjust
either the input frequency CLKINx\_PERIOD, multiplication factor
CLKFBOUT\_MULT
or the division factor DIVCLK\_DIVIDE, in order to achieve a VCO
frequency
within the rated operating range for this device.
ERROR:Pack:1642 - Errors in physical DRC.
We currently use the Xilinx ISE WebPack 14.2, but the projects are
created using version 12.2. I do not have this version currently
installed, and I also do not know if this error is caused by the change
in version. I still need to investigate this.
But I have more problems regarding the set of VHDL source files. I have
opened several other projects within this zip file which point to not
existing source files. Fortunately many can be found in other
sub-directories of other project like ‘test\_temp\_sensor’, but not all.
For example project ‘test\_dac\_pll’ is missing the file
wb\_spi\_master.vhd. And the project ‘test\_sata\_dp0’ needs many
ip-cores which I can’t seem to find anywhere.
Is it possible to collect and create a complete set of error free Xilinx
projects which can be synthesized and used for the tests with the SPEC
PTS?"
https://ohwr.org/project/svec/issues/19
V2 - Flash memory M25P128-VME6G obsolete
2020-01-07T10:54:35Z
Erik van der Bij
V2 - Flash memory M25P128-VME6G obsolete
The Flash memory NUMONYX (MICRON) M25P128-VME6G is obsolete.
The replacement part seems to be M25P128-VME6GB.
[Datasheet](http://download.siliconexpert.com/pdfs/2010/3/8/1/11/41/543/nmnyx_/manual/m25p128.pdf).
The difference is the process technology:
\- Blank = 130nm MLC
\- B = 65 nm SLC
- Verify the suggested replacement type.
- AC and DC characteristics are different between 130nm and 65nm
devices.
- Test on an actual board if needed.
- Update schematics with new symbol.
- Update production documents.
https://ohwr.org/project/pts/issues/9
SVEC PTS v1: change .inf extension
2019-02-12T10:07:00Z
Evangelia Gousiou
SVEC PTS v1: change .inf extension
.inf files are quarantined by cern mailing rules
https://ohwr.org/project/pts/issues/10
SVEC PTS v1: test00 in log
2019-02-12T10:07:00Z
Evangelia Gousiou
SVEC PTS v1: test00 in log
add information about test00 results in the .inf and .log files
(so far it was assumed that if there is a log file test00 has passed the
test)
https://ohwr.org/project/wishbone-gen/issues/25
Error while generating documentation
2019-02-12T09:01:40Z
Benoit Rat
Error while generating documentation
Error while generating documentation
neub@5760G:~/WR/misc/wishbone-gen/examples/gpio\_port$ lua -v
Lua 5.1.4 Copyright © 1994-2008 Lua.org, PUC-Rio
neub@5760G:~/WR/misc/wishbone-gen/examples/gpio\_port$ ../../wbgen2 -D
test.html gpio\_port.wb
lua: ../../wbgen2:3946: attempt to call global
'cgen\_generate\_html\_documentation' (a nil value)
stack traceback:
../../wbgen2:3946: in main chunk
\[C\]: ?
### Files
* [0001-fix-_22nil_22-issue-while-generating-documentation-_issue-_680_.patch](/uploads/aa525560a1a48f4de166ca14bea58113/0001-fix-_22nil_22-issue-while-generating-documentation-_issue-_680_.patch)
https://ohwr.org/project/spec/issues/32
V4-0 - enlarge via size 450um to 550um
2019-02-12T09:17:57Z
Erik van der Bij
V4-0 - enlarge via size 450um to 550um
One of the PCB manufacturers would have preferred to see the via sizes
enlarged from 450um to 550um.
It is surely possible to fabricate with 450um (they can go down to
400um), but going by 0.1mm larger would make things easier.
https://ohwr.org/project/fmc-tdc-1ns-5cha-hw/issues/6
V3-0 - Change stackup
2019-02-12T11:26:24Z
Erik van der Bij
V3-0 - Change stackup
- Verify proposal for a new stackup.
### Discussion
-----
- JGR: Some nets of the bus TDC\_D\[27..0\] were routed in the inside
layers with 8 mils of track width. According to my calculations, in
this inside layers the impedance is about 67 Ω \> 50 Ω +/- 10%. This
impedance step may degrade the signal quality. I'd prefer to
propose, if you believe it needed, another PCB stack-up to fit
better the 50 ohms impedance requirement without having to change
the routing.
- NV: Please explain… We can also enlarge the tracks on the internal
layers and/or (don’t know if it’s possible) to grow up the internal
layers thickness.
- EB: To check in a future version.
- JGR: I'd like to propose for this series (December 2012 - EB) this
PCB stack-up as an alternative (see the image below). Using it you
can achieve an impedance of about 50-55R for single ended internal
layers, improving the signals quality.
- NV: I cannot see the image… ;-).
- EB: To check in a future version. Do not change the PCB
specification and produce as specified. The differences in
impedances are too low to validate a change now.
-----
EB: I checked the differences in stackup between the original design
files and the ones that Wurth is proposing (see attached file).
Basically there is
- a slight difference in prepreg thickness at L1/L2 and L5/L6 (150 vs
163 um).
- a large difference in the other thicknesses L2/L3 and L4/L5 (500 vs
200 um) and L3/L4 (150 vs 570 um)
I believe that there nothing critical on this card, but still would like
the production version to be as similar as possible to our prototype and
therefore we should follow our original design files.
-----
### Files
* [7S_tarjeta_TDC_6_layer_standard_1_6.pdf.pdf.pdf](/uploads/fa04a3cfb89ccd23c7369d4d3ca1a04b/7S_tarjeta_TDC_6_layer_standard_1_6.pdf.pdf.pdf)
* [Proposal.gif](/uploads/ae54cd6470892f3d54a98ea5325bc83d/Proposal.gif)
https://ohwr.org/project/fmc-tdc-1ns-5cha-hw/issues/7
V3-0 - Track width not as defined. Verify layout.
2019-02-12T11:26:24Z
Erik van der Bij
V3-0 - Track width not as defined. Verify layout.
- Verify and correct track width of signals. Verify layout.
### Discussion
-----
- JGR: The “Layer Stack Up Detail” table indicates a line width/gap of
0.23/0.30 mm for 50/100 Ω at the top and bottom layers, but finally
the single ended tracks were routed with 0.203 mm (8 mils) width and
~56 Ω
- NV: I don’t think it’s the case for all the lines, but changing the
tracks between TDC chip and FMC connector to 10 mils can be easily
achievable.
- EB: Recommend to change in a future version
-----
- JGR: Some nets of the bus TDC\_D\[27..0\] were routed in the inside
layers with 8 mils of track width. According to my calculations, in
this inside layers the impedance is about 67 Ω \> 50 Ω +/- 10%. This
impedance step may degrade the signal quality. I'd prefer to
propose, if you believe it needed, another PCB stack-up to fit
better the 50 ohms impedance requirement without having to change
the routing.
- NV: Please explain… We can also enlarge the tracks on the internal
layers and/or (don’t know if it’s possible) to grow up the internal
layers thickness.
- EB: To check in a future version.
-----
- JGR: Some signals (TDC\_IN\_FPGA\[5..1\] and differential pairs by
example) were routed too close. It may cause crosstalk problems. I
would recommend using the 3W separation rule where possible.
- NV: This is the case for many other signals, not only TDC\_IN\_FPGA.
Not very easy to route those lines elsewhere -\> too much vias
around…
- EB: To check in a future version.
-----
- NV: Other things on routing: (if a version 4 is planned)
- On C21, enlarge the tracks on both sides.
- Enlarge the tracks of the TDC\_STOP \[1-5\] to 10-12mils on the
bottom side.
- A few more decoupling capacitors can be placed directly under
the TDC chip (bottom layer). Pins 81, 82 and 86.
- Looking at TDC chip, on the right side of pin 86, there is a via
(x: 4662.5mil, y: 4600mil) there is a small piece of track that
can be removed.
- On VDDC\_TDC, a 100nF decoupling capacitor could be added near
pin 1 of TDC chip.
- To check in a future version.
-----