From d34e140510d77821411b1a995c397c0e9aff9783 Mon Sep 17 00:00:00 2001
From: egousiou <egousiou@85dfdc96-de2c-444c-878d-45b388be74a9>
Date: Mon, 11 Jun 2012 10:00:49 +0000
Subject: [PATCH] added logic for controlling the mezzanine DAC that controls
the OSC1 that controls the PLL! added leds_manager unit to remove logic from
top level /!\treatment of 2 bugs in data_formatting (not completed though,
check top_tdc.vhd comments)
git-svn-id: http://svn.ohwr.org/fmc-tdc@76 85dfdc96-de2c-444c-878d-45b388be74a9
---
.../src/rtl/acam_timecontrol_interface.vhd | 2 +-
hdl/spec/src/rtl/clks_rsts_manager.vhd | 583 +++---
hdl/spec/src/rtl/data_formatting.vhd | 120 +-
hdl/spec/src/rtl/leds_manager.vhd | 269 +++
hdl/spec/src/rtl/reg_ctrl.vhd | 62 +-
hdl/spec/src/rtl/start_retrig_ctrl.vhd | 13 +-
hdl/spec/src/rtl/start_retrigger_control.vhd | 209 --
hdl/spec/src/rtl/tdc_core_pkg.vhd | 133 +-
hdl/spec/src/rtl/top_tdc.vhd | 1761 +++++++++--------
9 files changed, 1736 insertions(+), 1416 deletions(-)
create mode 100644 hdl/spec/src/rtl/leds_manager.vhd
delete mode 100644 hdl/spec/src/rtl/start_retrigger_control.vhd
diff --git a/hdl/spec/src/rtl/acam_timecontrol_interface.vhd b/hdl/spec/src/rtl/acam_timecontrol_interface.vhd
index 0231f06..5b878a5 100644
--- a/hdl/spec/src/rtl/acam_timecontrol_interface.vhd
+++ b/hdl/spec/src/rtl/acam_timecontrol_interface.vhd
@@ -56,7 +56,7 @@ use work.tdc_core_pkg.all; -- definitions of types, constants, entities
--=================================================================================================
--- Entity declaration for start_retrig_ctrl
+-- Entity declaration for acam_timecontrol_interface
--=================================================================================================
entity acam_timecontrol_interface is
diff --git a/hdl/spec/src/rtl/clks_rsts_manager.vhd b/hdl/spec/src/rtl/clks_rsts_manager.vhd
index 0fe1d81..3f04fd6 100644
--- a/hdl/spec/src/rtl/clks_rsts_manager.vhd
+++ b/hdl/spec/src/rtl/clks_rsts_manager.vhd
@@ -13,13 +13,13 @@
-- File clks_rsts_manager.vhd |
-- |
-- Description Independent block that uses the spec_clk_i to parameterize the TDC mezzanine PLL |
--- that will be used by all the other blocks. |
--- Includes input clk_i buffers for Xilinx Spartan6. |
+-- and DAC that will be used by all the other blocks. |
+-- Includes input clk buffers for Xilinx Spartan6. |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
--- Date 05/2011 |
--- Version v0.1 |
+-- Date 05/2012 |
+-- Version v0.3 |
-- Depends on |
-- |
---------------- |
@@ -29,6 +29,7 @@
-- Changed completely the internal reset generation; now it depends |
-- on the pll_ld activation |
-- General revamping, comments added, signals renamed |
+-- 05/2012 v0.3 EG Added logic for DAC configuration |
-- |
---------------------------------------------------------------------------------------------------
@@ -67,33 +68,49 @@ use UNISIM.vcomponents.all;
entity clks_rsts_manager is
generic
- (nb_of_reg : integer := 68;
- values_for_simulation : boolean := FALSE);
+ (nb_of_reg : integer := 68);
port
-- INPUTS
- (spec_clk_i : in std_logic;
- acam_refclk_i : in std_logic;
- tdc_clk_p_i : in std_logic;
- tdc_clk_n_i : in std_logic;
+ -- Clock signal from SPEC board
+ (spec_clk_i : in std_logic; -- 20 MHz OSC on SPEC board
- gnum_rst_i : in std_logic;
+ -- Clock signals from the PLL
+ acam_refclk_i : in std_logic; -- 31.25 MHz clock generated by the PLL, clock of ACAM
+ tdc_clk_p_i : in std_logic; -- 125 MHz clock generated by the PLL, clock of all other TDC core logic
+ tdc_clk_n_i : in std_logic;
+ -- Other signals from the PLL
pll_ld_i : in std_logic; -- PLL lock detect
- pll_refmon_i : in std_logic;
- pll_sdo_i : in std_logic;
+ pll_refmon_i : in std_logic; -- not used
pll_status_i : in std_logic; -- not used
+ pll_sdo_i : in std_logic; -- not used
+
+ -- Signal from the GNUM
+ rst_n_a_i : in std_logic; -- reset signal from the GNUM interface
+
+ -- Signals from the reg_ctrl unit for the reconfiguration of the DAC
+ send_dac_word_p_i : in std_logic; -- pulse upon PCI-e request for a DAC reconfiguration
+ dac_word_i : in std_logic_vector(23 downto 0); -- DAC Vout = Vref (dac_word/65536)
+
-- OUTPUTS
- acam_refclk_r_edge_p_o : out std_logic;
- internal_rst_o : out std_logic;
+ -- Signals to the rest of the modules of the TDC core
+ tdc_clk_o : out std_logic; -- 125 MHZ clock
+ internal_rst_o : out std_logic; -- internal reset asserted until the 125 MHZ clock from the PLL is available
+
+ -- Signals to the SPI interface for the PLL and DAC
+ pll_cs_o : out std_logic; -- SPI PLL chip select /!\ negative logic _n to be added
+ pll_dac_sync_o : out std_logic; -- SPI DAC chip select /!\ negative logic _n to be added
+ pll_sdi_o : out std_logic; -- SPI data
+ pll_sclk_o : out std_logic; -- SPI clock
- pll_cs_o : out std_logic;
- pll_dac_sync_o : out std_logic; -- not used
- pll_sdi_o : out std_logic;
- pll_sclk_o : out std_logic;
+ -- Signal to the one_hz_gen and acam_timecontrol_interface units
+ acam_refclk_r_edge_p_o : out std_logic; -- pulse upon acam_refclk_i rising edge
- spec_clk_o : out std_logic;
- tdc_clk_o : out std_logic);
+ -- Signals to the leds_manager unit
+ gnum_rst_o : out std_logic; -- GENUM reset synched with 20 MHz clock
+ spec_clk_o : out std_logic; -- 20 MHz clock
+ pll_ld_o : out std_logic);-- PLL lock detect synched with 20 MHz clock
end clks_rsts_manager;
@@ -107,10 +124,11 @@ architecture rtl of clks_rsts_manager is
subtype t_byte is std_logic_vector(7 downto 0);
type t_instr is array (nb_of_reg-1 downto 0) of t_wd;
type t_stream is array (nb_of_reg-1 downto 0) of t_byte;
- type t_pll_init_st is (start, sending_instruction, sending_data, rest, done);
+ type t_pll_init_st is (config_start, sending_dac_word, sending_pll_instruction,
+ sending_pll_data, rest, done);
--- The PLL circuit AD9516-4 needs to be configured through 68 registers. The values and addresses
--- are obtained from a dedicated Analog Devices software and from the datasheet.
+-- The PLL circuit AD9516-4 needs to be configured through 68 registers.
+-- The values and addresses are obtained through the dedicated Analog Devices software & the datasheet.
constant REG_000 : t_byte := x"18";
constant REG_001 : t_byte := x"00";
constant REG_002 : t_byte := x"10";
@@ -194,22 +212,26 @@ architecture rtl of clks_rsts_manager is
-- this value may still need adjustment according to the dispersion
-- in the performance of the PLL observed during the production tests
- signal pll_init_st, nxt_pll_init_st : t_pll_init_st;
- signal config_reg : t_stream;
- signal address : t_instr;
-
- signal spec_clk_buf, tdc_clk_buf : std_logic;
-
- signal acam_refclk_r : std_logic_vector(2 downto 0);
- signal pll_sclk, spec_clk, tdc_clk, internal_rst: std_logic;
- signal pll_ld_synch, internal_rst_synch : std_logic_vector (1 downto 0);
-
- signal bit_being_sent : std_logic;
- signal word_being_sent : t_wd;
- signal bit_index : integer range 15 downto 0;
- signal byte_index : integer range nb_of_reg-1 downto 0;
-
- signal cs_n : std_logic;
+ -- PLL and DAC configuration state machine
+ signal config_st, nxt_config_st : t_pll_init_st;
+ signal config_reg : t_stream;
+ signal addr : t_instr;
+ signal pll_word_being_sent : t_wd;
+ signal pll_bit_being_sent, dac_bit_being_sent : std_logic;
+ signal bit_being_sent, send_dac_word_r_edge_p : std_logic;
+ signal pll_bit_index : integer range 15 downto 0;
+ signal dac_bit_index : integer range 23 downto 0;
+ signal dac_word : std_logic_vector(23 downto 0);
+ signal pll_byte_index : integer range nb_of_reg-1 downto 0;
+ signal pll_cs_n, dac_cs_n : std_logic;
+ -- Synchronizers
+ signal pll_ld_synch, internal_rst_synch, gnum_rst_synch : std_logic_vector (1 downto 0);
+ signal acam_refclk_synch, send_dac_word_p_synch : std_logic_vector (2 downto 0);
+ -- Clock buffers
+ signal spec_clk_buf, tdc_clk_buf : std_logic;
+ signal sclk, spec_clk, tdc_clk : std_logic;
+ -- Resets
+ signal rst, internal_rst, gnum_rst : std_logic;
--=================================================================================================
@@ -219,37 +241,41 @@ begin
---------------------------------------------------------------------------------------------------
--- Clock input buffer instantiations --
+-- Clock buffers instantiations --
---------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------------
tdc_clk125_ibuf : IBUFDS
- generic map
- (DIFF_TERM => false, -- Differential Termination
- IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
- IOSTANDARD => "DEFAULT")
- port map
- (O => tdc_clk_buf, -- Buffer output
- I => tdc_clk_p_i, -- Diff_p buffer input (connect directly to top-level port)
- IB => tdc_clk_n_i); -- Diff_n buffer input (connect directly to top-level port)
+ generic map
+ (DIFF_TERM => false, -- Differential Termination
+ IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
+ IOSTANDARD => "DEFAULT")
+ port map
+ (O => tdc_clk_buf, -- Buffer output
+ I => tdc_clk_p_i, -- Diff_p buffer input (connect directly to top-level port)
+ IB => tdc_clk_n_i); -- Diff_n buffer input (connect directly to top-level port)
tdc_clk125_gbuf : BUFG
- port map
- (O => tdc_clk,
- I => tdc_clk_buf);
+ port map
+ (O => tdc_clk,
+ I => tdc_clk_buf);
+ -- -- -- -- -- -- -- --
+ tdc_clk_o <= tdc_clk;
+
+---------------------------------------------------------------------------------------------------
spec_clk_ibuf : IBUFG
- port map
- (I => spec_clk_i,
- O => spec_clk_buf);
+ port map
+ (I => spec_clk_i,
+ O => spec_clk_buf);
spec_clk_gbuf : BUFG
- port map
- (O => spec_clk,
- I => spec_clk_buf);
+ port map
+ (O => spec_clk,
+ I => spec_clk_buf);
-- -- -- -- -- -- -- --
spec_clk_o <= spec_clk;
- tdc_clk_o <= tdc_clk;
---------------------------------------------------------------------------------------------------
@@ -259,36 +285,51 @@ begin
-- This internal reset is triggered by the reset signal coming from the GNUM chip. The idea is to
-- keep the internal reset asserted until the clock signal received from the PLL is stable.
+---------------------------------------------------------------------------------------------------
+-- Synchronous process rst_n_a_i_synchronizer: Synchronization of the rst_n_a_i input to the
+-- spec_clk, using a set of 2 registers
+ rst_n_a_i_synchronizer: process (spec_clk)
+ begin
+ if rising_edge (spec_clk) then
+ gnum_rst_synch <= gnum_rst_synch(0) & not(rst_n_a_i);
+ end if;
+ end process;
+ -- -- -- -- -- -- -- --
+ gnum_rst <= gnum_rst_synch(1);
+ gnum_rst_o <= gnum_rst_synch(1);
+
---------------------------------------------------------------------------------------------------
-- Synchronous process PLL_LD_synchronizer: Synchronization of the pll_ld_i input to the spec_clk,
-- using a set of 2 registers.
- FD_RXD_synchronizer: process (spec_clk)
+ PLL_LD_synchronizer: process (spec_clk)
begin
if rising_edge (spec_clk) then
- if gnum_rst_i = '1' then
+ if gnum_rst = '1' then
pll_ld_synch <= (others => '0');
else
pll_ld_synch <= pll_ld_synch(0) & pll_ld_i;
end if;
end if;
end process;
+ -- -- -- -- -- -- -- --
+ pll_ld_o <= pll_ld_synch(1);
---------------------------------------------------------------------------------------------------
-- Synchronous process Internal_rst_generation: Generation of a reset signal for as long as the PLL
-- is not locked. As soon as the pll_ld is received the internal reset is released.
--- Note that the level of the pll_ld signal rather than its rising edge is used, as the in case of
+-- Note that the level of the pll_ld signal rather than its rising edge is used, as in the case of
-- a gnum_rst during operation with the pll already locked the pll_ld will remain active and no
-- edge will appear.
- Internal_rst_generation: process (spec_clk)
+ Internal_rst_generator: process (spec_clk)
begin
if rising_edge (spec_clk) then
- if gnum_rst_i = '1' then
- internal_rst <= '1';
+ if gnum_rst = '1' then
+ rst <= '1';
else
if pll_ld_synch(1) = '1' then
- internal_rst <= '0';
+ rst <= '0';
else
- internal_rst <= '1';
+ rst <= '1';
end if;
end if;
end if;
@@ -297,256 +338,360 @@ begin
---------------------------------------------------------------------------------------------------
-- Synchronous process internal_rst_synchronizer: Synchronization of the internal_rst signal to the
-- tdc_clk, using a set of 2 registers.
- internal_rst_synchronizer: process (tdc_clk)
+ Internal_rst_synchronizer: process (tdc_clk)
begin
if rising_edge (tdc_clk) then
- internal_rst_synch <= internal_rst_synch(0) & internal_rst;
+ internal_rst_synch <= internal_rst_synch(0) & rst;
end if;
end process;
+ -- -- -- -- -- -- -- --
+ internal_rst <= internal_rst_synch(1);
+ internal_rst_o <= internal_rst;
- internal_rst_o <= internal_rst_synch(1);
+
+---------------------------------------------------------------------------------------------------
+-- ACAM Reference Clock Synchronizer --
+---------------------------------------------------------------------------------------------------
+ acam_refclk_synchronizer: process (tdc_clk)
+ begin
+ if rising_edge (tdc_clk) then
+ if internal_rst_synch(1) = '1' then
+ acam_refclk_synch <= (others => '0');
+ else
+ acam_refclk_synch <= acam_refclk_synch(1 downto 0) & acam_refclk_i;
+ end if;
+ end if;
+ end process;
+ -- -- -- -- -- -- -- --
+ acam_refclk_r_edge_p_o <= (not acam_refclk_synch(2)) and acam_refclk_synch(1);
---------------------------------------------------------------------------------------------------
--- Processes for initialization of the PLL --
+-- DAC configuration --
---------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------------
+-- Synchronous process send_dac_word_p_synchronizer: Synchronization of the send_dac_word_p_o
+-- input to the spec_clk, using a set of 3 registers.
+ send_dac_word_p_synchronizer: process (spec_clk)
+ begin
+ if rising_edge (spec_clk) then
+ if gnum_rst = '1' then
+ send_dac_word_p_synch <= (others => '0');
+ else
+ send_dac_word_p_synch <= send_dac_word_p_synch(1 downto 0) & send_dac_word_p_i;
+ end if;
+ end if;
+ end process;
+ -- -- -- -- -- -- -- --
+ send_dac_word_r_edge_p <= (not send_dac_word_p_synch(2)) and send_dac_word_p_synch(1);
+
+---------------------------------------------------------------------------------------------------
+-- Synchronous process pll_dac_word: selection of the word to be sent to the DAC.
+-- Upon initialization the default word is being sent; otherwise a word received through the PCI-e
+-- interface on the DAC_WORD register.
+ pll_dac_word: process (spec_clk)
+ begin
+ if rising_edge (spec_clk) then
+ if gnum_rst = '1' then
+ dac_word <= c_DEFAULT_DAC_WORD;
+ elsif send_dac_word_r_edge_p = '1' then
+ dac_word <= dac_word_i;
+ end if;
+ end if;
+ end process;
+
+
---------------------------------------------------------------------------------------------------
- pll_initialization_seq: process (spec_clk)
+-- Processes for configuration of the DAC and PLL --
+---------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------------
+ pll_dac_initialization_seq: process (spec_clk)
begin
if rising_edge (spec_clk) then
- if gnum_rst_i ='1' then
- pll_init_st <= start;
+ if gnum_rst = '1' or send_dac_word_r_edge_p = '1' then
+ config_st <= config_start;
else
- pll_init_st <= nxt_pll_init_st;
+ config_st <= nxt_config_st;
end if;
end if;
end process;
+
---------------------------------------------------------------------------------------------------
- pll_initialization_comb: process (pll_init_st, byte_index, bit_index, pll_sclk)
+ pll_dac_initialization_comb: process (config_st, dac_bit_index, pll_byte_index, pll_bit_index, sclk)
begin
- case pll_init_st is
+ case config_st is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- when start =>
+ when config_start =>
-----------------------------------
- cs_n <= '1';
+ pll_cs_n <= '1';
+ dac_cs_n <= '1';
-----------------------------------
- if pll_sclk ='1' then
- nxt_pll_init_st <= sending_instruction;
- else
- nxt_pll_init_st <= start;
- end if;
+ if sclk = '1' then
+ nxt_config_st <= sending_dac_word;
+ else
+ nxt_config_st <= config_start;
+ end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- when sending_instruction =>
+ when sending_dac_word =>
-----------------------------------
- cs_n <= '0';
+ pll_cs_n <= '1';
+ dac_cs_n <= '0';
-----------------------------------
- if bit_index = 0 and pll_sclk = '1' then
- nxt_pll_init_st <= sending_data;
+ if dac_bit_index = 0 and sclk = '1' then
+ nxt_config_st <= sending_pll_instruction;
else
- nxt_pll_init_st <= sending_instruction;
+ nxt_config_st <= sending_dac_word;
end if;
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- when sending_data =>
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ when sending_pll_instruction =>
-----------------------------------
- cs_n <= '0';
+ pll_cs_n <= '0';
+ dac_cs_n <= '1';
-----------------------------------
+ if pll_bit_index = 0 and sclk = '1' then
+ nxt_config_st <= sending_pll_data;
+ else
+ nxt_config_st <= sending_pll_instruction;
+ end if;
- if bit_index = 0 and pll_sclk = '1' then
- nxt_pll_init_st <= rest;
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ when sending_pll_data =>
+ -----------------------------------
+ pll_cs_n <= '0';
+ dac_cs_n <= '1';
+ -----------------------------------
+ if pll_bit_index = 0 and sclk = '1' then
+ nxt_config_st <= rest;
else
- nxt_pll_init_st <= sending_data;
- end if;
+ nxt_config_st <= sending_pll_data;
+ end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when rest =>
-----------------------------------
- cs_n <= '1';
+ pll_cs_n <= '1';
+ dac_cs_n <= '1';
-----------------------------------
- if pll_sclk = '1' then
- if byte_index = 0 then
- nxt_pll_init_st <= done;
+ if sclk = '1' then
+ if pll_byte_index = 0 then
+ nxt_config_st <= done;
else
- nxt_pll_init_st <= sending_instruction;
+ nxt_config_st <= sending_pll_instruction;
end if;
else
- nxt_pll_init_st <= rest;
+ nxt_config_st <= rest;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when done =>
-----------------------------------
- cs_n <= '1';
+ pll_cs_n <= '1';
+ dac_cs_n <= '1';
-----------------------------------
- nxt_pll_init_st <= done;
+ nxt_config_st <= done;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
-----------------------------------
- cs_n <= '1';
+ pll_cs_n <= '1';
+ dac_cs_n <= '1';
-----------------------------------
- nxt_pll_init_st <= start;
+ nxt_config_st <= config_start;
end case;
end process;
+---------------------------------------------------------------------------------------------------
+ pll_sclk_generator: process (spec_clk) -- transitions take place on the falling edge of sclk
+ begin
+ if rising_edge (spec_clk) then
+ if gnum_rst = '1' then
+ sclk <= '0';
+ else
+ sclk <= not(sclk);
+ end if;
+ end if;
+ end process;
+
+
---------------------------------------------------------------------------------------------------
- index_control: process (spec_clk)
+ pll_index_control: process (spec_clk)
begin
if rising_edge (spec_clk) then
- if gnum_rst_i = '1' then
- bit_index <= 15;
- elsif cs_n = '1' then
- bit_index <= 15;
- elsif pll_sclk = '1' then
- if bit_index = 0 then
- bit_index <= 7;
+ if gnum_rst = '1' then
+ pll_bit_index <= 15;
+
+ elsif pll_cs_n = '1' then
+ pll_bit_index <= 15;
+
+ elsif sclk = '1' then
+ if pll_bit_index = 0 then
+ pll_bit_index <= 7;
else
- bit_index <= bit_index -1;
+ pll_bit_index <= pll_bit_index -1;
end if;
end if;
- if gnum_rst_i = '1' then
- byte_index <= nb_of_reg -1;
- elsif pll_init_st = rest and pll_sclk = '1' then
- if byte_index = 0 then
- byte_index <= nb_of_reg-1;
+ if gnum_rst = '1' then
+ pll_byte_index <= nb_of_reg -1;
+ elsif config_st = rest and sclk = '1' then
+ if pll_byte_index = 0 then
+ pll_byte_index <= nb_of_reg-1;
else
- byte_index <= byte_index -1;
+ pll_byte_index <= pll_byte_index -1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------
- pll_sclk_generator: process (spec_clk) -- transitions take place on the falling edge of sclk
+ -- -- -- -- -- -- -- --
+ pll_bit_being_sent <= pll_word_being_sent(pll_bit_index);
+ pll_word_being_sent <= addr(pll_byte_index) when config_st = sending_pll_instruction
+ else x"00" & config_reg(pll_byte_index);
+
+
+---------------------------------------------------------------------------------------------------
+ dac_index_control: process (spec_clk)
begin
if rising_edge (spec_clk) then
- if gnum_rst_i ='1' then
- pll_sclk <= '0';
- else
- pll_sclk <= not(pll_sclk);
+
+ if gnum_rst = '1' then
+ dac_bit_index <= 23;
+
+ elsif dac_cs_n = '1' then
+ dac_bit_index <= 23;
+
+ elsif sclk = '1' then
+ if dac_bit_index = 0 then
+ dac_bit_index <= 23;
+ else
+ dac_bit_index <= dac_bit_index - 1;
+ end if;
end if;
end if;
end process;
--- -- -- -- -- -- -- --
- bit_being_sent <= word_being_sent(bit_index);
- word_being_sent <= address(byte_index) when pll_init_st = sending_instruction
- else x"00" & config_reg(byte_index);
+ -- -- -- -- -- -- -- --
+ dac_bit_being_sent <= dac_word(dac_bit_index);
+ bit_being_sent <= dac_bit_being_sent when dac_cs_n = '0' else pll_bit_being_sent;
+
---------------------------------------------------------------------------------------------------
Output_regs: process (spec_clk)
begin
if rising_edge (spec_clk) then
- if gnum_rst_i = '1' then
- pll_cs_o <= '1';
- pll_sdi_o <= '0';
+ if gnum_rst = '1' then
+ pll_cs_o <= '1';
+ pll_dac_sync_o <= '1';
+ pll_sdi_o <= '0';
else
- if pll_sclk = '1' then
- pll_cs_o <= cs_n;
- pll_sdi_o <= bit_being_sent;
+ if sclk = '1' then
+ pll_sdi_o <= bit_being_sent;
+ pll_dac_sync_o <= dac_cs_n;
+ pll_cs_o <= pll_cs_n;
+
end if;
end if;
end if;
end process;
- pll_sclk_o <= pll_sclk;
+ -- -- -- -- -- -- -- --
+ pll_sclk_o <= sclk;
+
---------------------------------------------------------------------------------------------------
-- Assignement of the values to be sent for the configurations of the PLL --
---------------------------------------------------------------------------------------------------
-- According to the datasheet the register 232 should be written last to validate the transfer
--- from the buffer to the valid registers.
--- The 16-bit instruction word indicates always a write cycle of byte.
-
+-- from the buffer to the valid registers. The 16-bit instruction word indicates always a write
+-- cycle of byte.
-- -- -- -- -- -- -- -- -- -- -- -- -- --
- address(0) <= x"0232";
- address(1) <= x"0000";
- address(2) <= x"0001";
- address(3) <= x"0002";
- address(4) <= x"0003";
- address(5) <= x"0004";
+ addr(0) <= x"0232";
+ addr(1) <= x"0000";
+ addr(2) <= x"0001";
+ addr(3) <= x"0002";
+ addr(4) <= x"0003";
+ addr(5) <= x"0004";
--------------------------
- address(6) <= x"0010";
- address(7) <= x"0011";
- address(8) <= x"0012";
- address(9) <= x"0013";
- address(10) <= x"0014";
- address(11) <= x"0015";
- address(12) <= x"0016";
- address(13) <= x"0017";
- address(14) <= x"0018";
- address(15) <= x"0019";
- address(16) <= x"001A";
- address(17) <= x"001B";
- address(18) <= x"001C";
- address(19) <= x"001D";
- address(20) <= x"001E";
- address(21) <= x"001F";
+ addr(6) <= x"0010";
+ addr(7) <= x"0011";
+ addr(8) <= x"0012";
+ addr(9) <= x"0013";
+ addr(10) <= x"0014";
+ addr(11) <= x"0015";
+ addr(12) <= x"0016";
+ addr(13) <= x"0017";
+ addr(14) <= x"0018";
+ addr(15) <= x"0019";
+ addr(16) <= x"001A";
+ addr(17) <= x"001B";
+ addr(18) <= x"001C";
+ addr(19) <= x"001D";
+ addr(20) <= x"001E";
+ addr(21) <= x"001F";
--------------------------
- address(22) <= x"00A0";
- address(23) <= x"00A1";
- address(24) <= x"00A2";
- address(25) <= x"00A3";
- address(26) <= x"00A4";
- address(27) <= x"00A5";
- address(28) <= x"00A6";
- address(29) <= x"00A7";
- address(30) <= x"00A8";
- address(31) <= x"00A9";
- address(32) <= x"00AA";
- address(33) <= x"00AB";
+ addr(22) <= x"00A0";
+ addr(23) <= x"00A1";
+ addr(24) <= x"00A2";
+ addr(25) <= x"00A3";
+ addr(26) <= x"00A4";
+ addr(27) <= x"00A5";
+ addr(28) <= x"00A6";
+ addr(29) <= x"00A7";
+ addr(30) <= x"00A8";
+ addr(31) <= x"00A9";
+ addr(32) <= x"00AA";
+ addr(33) <= x"00AB";
--------------------------
- address(34) <= x"00F0";
- address(35) <= x"00F1";
- address(36) <= x"00F2";
- address(37) <= x"00F3";
- address(38) <= x"00F4";
- address(39) <= x"00F5";
+ addr(34) <= x"00F0";
+ addr(35) <= x"00F1";
+ addr(36) <= x"00F2";
+ addr(37) <= x"00F3";
+ addr(38) <= x"00F4";
+ addr(39) <= x"00F5";
--------------------------
- address(40) <= x"0140";
- address(41) <= x"0141";
- address(42) <= x"0142";
- address(43) <= x"0143";
+ addr(40) <= x"0140";
+ addr(41) <= x"0141";
+ addr(42) <= x"0142";
+ addr(43) <= x"0143";
--------------------------
- address(44) <= x"0190";
- address(45) <= x"0191";
- address(46) <= x"0192";
- address(47) <= x"0193";
- address(48) <= x"0194";
- address(49) <= x"0195";
- address(50) <= x"0196";
- address(51) <= x"0197";
- address(52) <= x"0198";
+ addr(44) <= x"0190";
+ addr(45) <= x"0191";
+ addr(46) <= x"0192";
+ addr(47) <= x"0193";
+ addr(48) <= x"0194";
+ addr(49) <= x"0195";
+ addr(50) <= x"0196";
+ addr(51) <= x"0197";
+ addr(52) <= x"0198";
--------------------------
- address(53) <= x"0199";
- address(54) <= x"019A";
- address(55) <= x"019B";
- address(56) <= x"019C";
- address(57) <= x"019D";
- address(58) <= x"019E";
- address(59) <= x"019F";
+ addr(53) <= x"0199";
+ addr(54) <= x"019A";
+ addr(55) <= x"019B";
+ addr(56) <= x"019C";
+ addr(57) <= x"019D";
+ addr(58) <= x"019E";
+ addr(59) <= x"019F";
--------------------------
- address(60) <= x"01A0";
- address(61) <= x"01A1";
- address(62) <= x"01A2";
- address(63) <= x"01A3";
+ addr(60) <= x"01A0";
+ addr(61) <= x"01A1";
+ addr(62) <= x"01A2";
+ addr(63) <= x"01A3";
--------------------------
- address(64) <= x"01E0";
- address(65) <= x"01E1";
+ addr(64) <= x"01E0";
+ addr(65) <= x"01E1";
--------------------------
- address(66) <= x"0230";
- address(67) <= x"0231";
-
+ addr(66) <= x"0230";
+ addr(67) <= x"0231";
-- -- -- -- -- -- -- -- -- -- -- -- -- --
config_reg(0) <= REG_232;
config_reg(1) <= REG_000;
@@ -628,24 +773,6 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- --
----------------------------------------------------------------------------------------------------
--- ACAM Reference Clock Synchronizer --
----------------------------------------------------------------------------------------------------
- acam_refclk_synchronizer: process (tdc_clk)
- begin
- if rising_edge (tdc_clk) then
- if internal_rst_synch(1) = '1' then
- acam_refclk_r <= (others=>'0');
- else
- acam_refclk_r <= acam_refclk_i & acam_refclk_r(2 downto 1);
- end if;
- end if;
- end process;
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- acam_refclk_r_edge_p_o <= acam_refclk_r(1) and not(acam_refclk_r(0));
-
-
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
diff --git a/hdl/spec/src/rtl/data_formatting.vhd b/hdl/spec/src/rtl/data_formatting.vhd
index 159935b..3e818fa 100644
--- a/hdl/spec/src/rtl/data_formatting.vhd
+++ b/hdl/spec/src/rtl/data_formatting.vhd
@@ -64,49 +64,53 @@ entity data_formatting is
port
-- INPUTS
-- Signal from the clk_rst_manager
- (clk_i : in std_logic; -- 125 MHz clk
- rst_i : in std_logic; -- general reset
+ (clk_i : in std_logic; -- 125 MHz clk
+ rst_i : in std_logic; -- general reset
-- Signals from the circular_buffer unit: WISHBONE classic
- tstamp_wr_wb_ack_i : in std_logic; -- tstamp writing WISHBONE acknowledge
- tstamp_wr_dat_i : in std_logic_vector(127 downto 0); -- not used
+ tstamp_wr_wb_ack_i : in std_logic; -- tstamp writing WISHBONE acknowledge
+ tstamp_wr_dat_i : in std_logic_vector(127 downto 0); -- not used
-- Signals from the data_engine unit
- acam_tstamp1_i : in std_logic_vector(31 downto 0); -- 32 bits tstamp to be treated and stored;
+ acam_tstamp1_i : in std_logic_vector(31 downto 0); -- 32 bits tstamp to be treated and stored;
-- includes ef1 & ef2 & lf1 & lf2 & 28 bits tstamp from FIFO1
- acam_tstamp1_ok_p_i : in std_logic; -- tstamp2 valid indicator
- acam_tstamp2_i : in std_logic_vector(31 downto 0); -- 32 bits tstamp to be treated and stored;
+ acam_tstamp1_ok_p_i : in std_logic; -- tstamp2 valid indicator
+ acam_tstamp2_i : in std_logic_vector(31 downto 0); -- 32 bits tstamp to be treated and stored;
-- includes ef1 & ef2 & lf1 & lf2 & 28 bits tstamp from FIFO2
- acam_tstamp2_ok_p_i : in std_logic; -- tstamp2 valid indicator
+ acam_tstamp2_ok_p_i : in std_logic; -- tstamp2 valid indicator
-- Signals from the reg_ctrl unit
- dacapo_c_rst_p_i : in std_logic; -- instruction from PCIe to clear dacapo flag
+ dacapo_c_rst_p_i : in std_logic; -- instruction from PCIe to clear dacapo flag
-- Signals from the one_hz_gen unit
- local_utc_i : in std_logic_vector(31 downto 0); -- local UTC time
+ local_utc_i : in std_logic_vector(31 downto 0); -- local UTC time
-- Signals from the start_retrig_ctrl unit
- clk_i_cycles_offset_i : in std_logic_vector(31 downto 0); -- eva: don t know yet
- current_roll_over_i : in std_logic_vector(31 downto 0); -- eva: don t know yet
- retrig_nb_offset_i : in std_logic_vector(31 downto 0); -- eva: don t know yet
+ roll_over_incr_recent_i : in std_logic;
+ clk_i_cycles_offset_i : in std_logic_vector(31 downto 0);
+ roll_over_nb_i : in std_logic_vector(31 downto 0);
+ retrig_nb_offset_i : in std_logic_vector(31 downto 0);
+
+ -- Signal from the one_hz_generator unit
+ one_hz_p_i : in std_logic;
-- OUTPUTS
-- Signals to the circular_buffer unit: WISHBONE classic
- tstamp_wr_wb_cyc_o : out std_logic; -- tstamp writing WISHBONE cycle
- tstamp_wr_wb_stb_o : out std_logic; -- tstamp writing WISHBONE strobe
- tstamp_wr_wb_we_o : out std_logic; -- tstamp writing WISHBONE write enable
- tstamp_wr_wb_adr_o : out std_logic_vector(7 downto 0); -- WISHBONE adr to write to
- tstamp_wr_dat_o : out std_logic_vector(127 downto 0); -- tstamp to write
+ tstamp_wr_wb_cyc_o : out std_logic; -- tstamp writing WISHBONE cycle
+ tstamp_wr_wb_stb_o : out std_logic; -- tstamp writing WISHBONE strobe
+ tstamp_wr_wb_we_o : out std_logic; -- tstamp writing WISHBONE write enable
+ tstamp_wr_wb_adr_o : out std_logic_vector(7 downto 0); -- WISHBONE adr to write to
+ tstamp_wr_dat_o : out std_logic_vector(127 downto 0); -- tstamp to write
-- Signal to the irq_generator unit
- tstamp_wr_p_o : out std_logic; -- pulse upon storage of a new tstamp
+ tstamp_wr_p_o : out std_logic; -- pulse upon storage of a new tstamp
-- Signal to the reg_ctrl unit
- wr_index_o : out std_logic_vector(31 downto 0)); -- index of last byte written
- -- note that the index is provided
- -- #bytes, as the PCIe expects
- -- (not in #128-bits-words)
+ wr_index_o : out std_logic_vector(31 downto 0)); -- index of last byte written
+ -- note that the index is provided
+ -- #bytes, as the PCIe expects
+ -- (not in #128-bits-words)
end data_formatting;
@@ -135,6 +139,9 @@ architecture rtl of data_formatting is
signal dacapo_counter : unsigned(19 downto 0);
signal wr_index : unsigned(7 downto 0);
+ -- signal previous_clk_i_cycles_offset : std_logic_vector(31 downto 0);
+ -- signal previous_retrig_nb_offset, previous_roll_over_nb : std_logic_vector(31 downto 0);
+
--=================================================================================================
-- architecture begin
@@ -252,7 +259,7 @@ begin
-- each bit represents 81.03 ps
-- [63:32] Coarse time within the current second, caclulated from the: Start number,
--- clk_i_cycles_offset_i, retrig_nb_offset_i, current_roll_over_i
+-- clk_i_cycles_offset_i, retrig_nb_offset_i, roll_over_nb_i
-- each bit represents 8 ns
-- [95:64] Local UTC time coming from the one_hz_generator;
@@ -290,6 +297,23 @@ begin
end if;
end process;
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- reg_info_of_previous_sec: process (clk_i)
+ -- begin
+ -- if rising_edge (clk_i) then
+ -- if rst_i = '1' then
+ -- previous_clk_i_cycles_offset <= (others => '0');
+ -- previous_retrig_nb_offset <= (others => '0');
+ -- previous_roll_over_nb <= (others => '0');
+
+ -- elsif one_hz_p_i = '1' then
+ -- previous_clk_i_cycles_offset <= clk_i_cycles_offset_i;
+ -- previous_retrig_nb_offset <= retrig_nb_offset_i;
+ -- previous_roll_over_nb <= roll_over_nb_i;
+ -- end if;
+ -- end if;
+ -- end process;
+
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
full_timestamp(31 downto 0) <= fine_time;
full_timestamp(63 downto 32) <= coarse_time;
@@ -297,6 +321,27 @@ begin
full_timestamp(127 downto 96) <= metadata;
tstamp_wr_dat_o <= full_timestamp;
+ --un_clk_i_cycles_offset <= unsigned(previous_clk_i_cycles_offset) when retrig_nb_offset_i = acam_start_nb_32
+ -- else unsigned(clk_i_cycles_offset_i);
+ --un_retrig_nb_offset <= unsigned(previous_retrig_nb_offset) when retrig_nb_offset_i = acam_start_nb_32
+ -- else unsigned(retrig_nb_offset_i);
+ --un_roll_over <= unsigned(previous_roll_over_nb) when retrig_nb_offset_i = acam_start_nb_32
+ -- else unsigned(roll_over_nb_i);
+
+ -- all the values needed for the calculations have to be converted to unsigned
+ acam_start_nb_32 <= x"000000" & acam_start_nb;
+ un_acam_start_nb <= unsigned(acam_start_nb_32);
+ un_clk_i_cycles_offset <= unsigned(clk_i_cycles_offset_i);
+ un_retrig_nb_offset <= unsigned(retrig_nb_offset_i);
+ un_roll_over <= unsigned(roll_over_nb_i);
+
+ -- the number of roll-overs of the ACAM internal start retrigger counter is converted to a number
+ -- of internal start retriggers.
+ -- shifted left to multiply by 256
+ un_retrig_from_roll_over <= shift_left(un_roll_over-1, 8) when roll_over_incr_recent_i = '1' and un_acam_start_nb > 192
+ else shift_left(un_roll_over, 8);
+
+
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- fine time: directly provided by ACAM as a number of BINs since the last internal retrigger
fine_time <= x"000" & "000" & acam_fine_timestamp;
@@ -311,39 +356,30 @@ begin
-- and will cancel when substracting timestamps.
coarse_time <= std_logic_vector(un_nb_of_cycles);
- -- all the values needed for the calculations have to be converted to unsigned
- acam_start_nb_32 <= x"000000" & acam_start_nb;
- un_acam_start_nb <= unsigned(acam_start_nb_32);
- un_clk_i_cycles_offset <= unsigned(clk_i_cycles_offset_i);
- un_retrig_nb_offset <= unsigned(retrig_nb_offset_i);
- un_roll_over <= unsigned(current_roll_over_i);
-
- -- the number of roll-overs of the ACAM internal start retrigger counter is converted to a number
- -- of internal start retriggers.
- un_retrig_from_roll_over <= shift_left(un_roll_over,8); -- shifted left to multiply by 256
-
- -- the actual number of internal start retriggers actually occurred is calculated by subtracting the offset number
+ -- the number of internal start retriggers actually occurred is calculated by subtracting the offset number
-- already present when the one_hz_pulse arrives, and adding the start nb provided by the ACAM.
- un_nb_of_retrig <= un_retrig_from_roll_over - un_retrig_nb_offset + (un_acam_start_nb);
+ un_nb_of_retrig <= un_retrig_from_roll_over - un_retrig_nb_offset + un_acam_start_nb;
-- finally, the coarse time is obtained by multiplying by the number of clk_i cycles in an internal
-- start retrigger period and adding the number of clk_i cycles still to be discounted when the
-- one_hz_pulse arrives.
- un_nb_of_cycles <= shift_left(un_nb_of_retrig-1, c_ACAM_RETRIG_PERIOD_SHIFT) + un_clk_i_cycles_offset;
+ un_nb_of_cycles <= shift_left(un_nb_of_retrig-1, c_ACAM_RETRIG_PERIOD_SHIFT) + un_clk_i_cycles_offset;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- metadata: information about the timestamp
- metadata <= x"0000" & -- 16 bits (MSB)
- "000" & acam_fifo_ef & -- 4 bits in total
- "000" & acam_fifo_lf & -- 4 bits in total
+ metadata <= acam_start_nb &
+ roll_over_nb_i(15 downto 0) &
+ -- x"0000" & -- 16 bits (MSB)
+ -- "000" & acam_fifo_ef & -- 4 bits in total
+ -- "000" & acam_fifo_lf & -- 4 bits in total
"000" & acam_slope & -- 4 bits in total
"0" & acam_channel; -- 4 bits in total (LSB)
+
---------------------------------------------------------------------------------------------------
-- Outputs --
---------------------------------------------------------------------------------------------------
-
-- wr_pointer_o <= dacapo_flag & std_logic_vector(wr_index(g_width-6 downto 0)) & x"0";
tstamp_wr_wb_cyc_o <= tstamp_wr_cyc;
diff --git a/hdl/spec/src/rtl/leds_manager.vhd b/hdl/spec/src/rtl/leds_manager.vhd
new file mode 100644
index 0000000..1290754
--- /dev/null
+++ b/hdl/spec/src/rtl/leds_manager.vhd
@@ -0,0 +1,269 @@
+--_________________________________________________________________________________________________
+-- |
+-- |TDC core| |
+-- |
+-- CERN,BE/CO-HT |
+--________________________________________________________________________________________________|
+
+---------------------------------------------------------------------------------------------------
+-- |
+-- leds_manager |
+-- |
+---------------------------------------------------------------------------------------------------
+-- File leds_manager.vhd |
+-- |
+-- Description Generation of the signals that drive the LEDs on the TDC mezzanine and SPEC |
+-- carrier boards. |
+-- There are 6 LEDs on the front panel of the TDC mezzanine board: |
+-- ______ |
+-- | | |
+-- | O O | 1, 2 |
+-- | O O | 3, 4 |
+-- | O O | 5, 6 |
+-- |______| |
+-- |
+-- And further down 2 LEDs on the front panel of the SPEC carrier board: |
+-- ______ |
+-- | O O | 1, 2 |
+-- |______| |
+-- |
+-- TDC LED 1 orange: division of the 125 MHz clock; one hz pulses |
+-- TDC LED 2 orange: Channel 1 terminatio enable |
+-- TDC LED 3 orange: Channel 2 terminatio enable |
+-- TDC LED 4 orange: Channel 3 terminatio enable |
+-- TDC LED 5 orange: Channel 4 terminatio enable |
+-- TDC LED 6 orange: Channel 5 terminatio enable |
+-- SPEC LED 1 green : PLL lock detect |
+-- SPEC LED 2 red : division of the 20 MHz clock |
+-- |
+-- There are also 4 LEDs and 2 buttons on the PCB of the SPEC carrier: |
+-- _______________ |
+-- | O O O O | aux LEDs 1, 2, 3, 4 |
+-- | __ __ | |
+-- | |__| |__| | aux buttons 1, 2 |
+-- |_______________| |
+-- |
+-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
+-- Date 05/2012 |
+-- Version v0.3 |
+-- Depends on |
+-- |
+---------------- |
+-- Last changes |
+-- 05/2012 v0.1 EG First version |
+---------------------------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE |
+-- ------------------------------------ |
+-- This source file is free software; you can redistribute it and/or modify it under the terms of |
+-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
+-- version 2.1 of the License, or (at your option) any later version. |
+-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
+-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
+-- See the GNU Lesser General Public License for more details. |
+-- You should have received a copy of the GNU Lesser General Public License along with this |
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
+---------------------------------------------------------------------------------------------------
+
+
+--=================================================================================================
+-- Libraries & Packages
+--=================================================================================================
+
+-- Standard library
+library IEEE;
+use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
+use IEEE.NUMERIC_STD.all; -- conversion functions
+-- Specific libraries
+library work;
+use work.tdc_core_pkg.all; -- definitions of types, constants, entities
+
+
+
+--=================================================================================================
+-- Entity declaration for leds_manager
+--=================================================================================================
+
+entity leds_manager is
+ generic
+ (g_width : integer := 32;
+ values_for_simulation : boolean := FALSE);
+ port
+ -- INPUTS
+ -- Signals from the clks_rsts_manager
+ (clk_20mhz_i : in std_logic; -- 20 MHz clock
+ clk_125mhz_i : in std_logic; -- 125 MHz clock
+ gnum_rst_i : in std_logic; -- reset from the PCI-e, synched with 20 MHz clk
+ internal_rst_i : in std_logic; -- core internal reset, synched with 125 MHz clk
+
+ -- Signal from the PLL
+ pll_ld_i : in std_logic; -- PLL lock detect
+
+ -- Signals from the buttons on the SPEC PCB
+ spec_aux_butt_1_i : in std_logic; -- SPEC PCB button 1 (PB1)
+ spec_aux_butt_2_i : in std_logic; -- SPEC PCB button 2 (PB2)
+
+ -- Signal from the one_hz_generator unit
+ one_hz_p_i : in std_logic;
+
+ -- Signal from the reg_ctrl unit
+ acam_inputs_en_i : in std_logic_vector(g_width-1 downto 0); -- enable for the ACAM channels;
+ -- activation comes through dedicated reg c_ACAM_INPUTS_EN_ADR
+
+
+ -- OUTPUTS
+ -- Signals to the LEDs on the TDC front panel
+ tdc_led_status_o : out std_logic; -- TDC LED 1: division of 125 MHz
+ tdc_led_trig1_o : out std_logic; -- TDC LED 2: Channel 1 input enable
+ tdc_led_trig2_o : out std_logic; -- TDC LED 3: Channel 2 input enable
+ tdc_led_trig3_o : out std_logic; -- TDC LED 4: Channel 3 input enable
+ tdc_led_trig4_o : out std_logic; -- TDC LED 5: Channel 4 input enable
+ tdc_led_trig5_o : out std_logic; -- TDC LED 6: Channel 5 input enable
+
+ -- Signals to the LEDs on the SPEC front panel
+ spec_led_green_o : out std_logic; -- SPEC LED 1: PLL lock detect
+ spec_led_red_o : out std_logic; -- SPEC LED 2: division of 20 MHz
+
+ -- Signals to the LEDs on the SPEC PCB
+ spec_aux_led_1_o : out std_logic; -- SPEC PCB LED 1 (LD2)
+ spec_aux_led_2_o : out std_logic; -- SPEC PCB LED 2 (LD3)
+ spec_aux_led_3_o : out std_logic; -- SPEC PCB LED 3 (LD4)
+ spec_aux_led_4_o : out std_logic);-- SPEC PCB LED 4 (LD5)
+
+end leds_manager;
+
+
+--=================================================================================================
+-- architecture declaration
+--=================================================================================================
+architecture rtl of leds_manager is
+
+ signal spec_led_blink_done, spec_led_period_done, tdc_led_blink_done : std_logic;
+ signal spec_led_period, visible_blink_length : std_logic_vector(g_width-1 downto 0);
+
+begin
+---------------------------------------------------------------------------------------------------
+-- TDC FRONT PANEL LED 1 --
+---------------------------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------------------------------
+
+ tdc_led_blink_counter: decr_counter
+ port map
+ (clk_i => clk_125mhz_i,
+ rst_i => internal_rst_i,
+ counter_load_i => one_hz_p_i,
+ counter_top_i => visible_blink_length,
+ counter_is_zero_o => tdc_led_blink_done,
+ counter_o => open);
+
+---------------------------------------------------------------------------------------------------
+ tdc_led: process (clk_125mhz_i)
+ begin
+ if rising_edge (clk_125mhz_i) then
+ if internal_rst_i ='1' then
+ tdc_led_status_o <= '0';
+ elsif one_hz_p_i ='1' then
+ tdc_led_status_o <= '1';
+ elsif tdc_led_blink_done = '1' then
+ tdc_led_status_o <= '0';
+ end if;
+ end if;
+ end process;
+
+
+---------------------------------------------------------------------------------------------------
+-- TDC FRONT PANEL LEDs 2-6 --
+---------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------------
+ all_outputs: process (clk_125mhz_i)
+ begin
+ if rising_edge (clk_125mhz_i) then
+ tdc_led_trig5_o <= acam_inputs_en_i(4) and acam_inputs_en_i(7);
+ tdc_led_trig4_o <= acam_inputs_en_i(3) and acam_inputs_en_i(7);
+ tdc_led_trig3_o <= acam_inputs_en_i(2) and acam_inputs_en_i(7);
+ tdc_led_trig2_o <= acam_inputs_en_i(1) and acam_inputs_en_i(7);
+ tdc_led_trig1_o <= acam_inputs_en_i(0) and acam_inputs_en_i(7);
+ end if;
+ end process;
+
+
+---------------------------------------------------------------------------------------------------
+-- SPEC FRONT PANEL LED 1 --
+---------------------------------------------------------------------------------------------------
+ spec_led_green_o <= pll_ld_i;
+
+
+---------------------------------------------------------------------------------------------------
+-- SPEC FRONT PANEL LED 2 --
+---------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------------
+ spec_led_period_counter: free_counter
+ port map
+ (clk_i => clk_20mhz_i,
+ counter_en_i => '1',
+ rst_i => gnum_rst_i,
+ counter_top_i => spec_led_period,
+ counter_is_zero_o => spec_led_period_done,
+ counter_o => open);
+
+ -- -- -- -- -- -- -- --
+ spec_led_period <= c_SPEC_LED_PERIOD_SIM when values_for_simulation else c_SPEC_LED_PERIOD_SYN;
+
+---------------------------------------------------------------------------------------------------
+ spec_led_blink_counter: decr_counter
+ port map
+ (clk_i => clk_20mhz_i,
+ rst_i => gnum_rst_i,
+ counter_load_i => spec_led_period_done,
+ counter_top_i => visible_blink_length,
+ counter_is_zero_o => spec_led_blink_done,
+ counter_o => open);
+
+ -- -- -- -- -- -- -- --
+ visible_blink_length <= c_BLINK_LGTH_SIM when values_for_simulation else c_BLINK_LGTH_SYN;
+
+---------------------------------------------------------------------------------------------------
+ spec_led: process (clk_20mhz_i)
+ begin
+ if rising_edge (clk_20mhz_i) then
+ if gnum_rst_i ='1' then
+ spec_led_red_o <= '0';
+ elsif spec_led_period_done ='1' then
+ spec_led_red_o <= '1';
+ elsif spec_led_blink_done ='1' then
+ spec_led_red_o <= '0';
+ end if;
+ end if;
+ end process;
+
+
+---------------------------------------------------------------------------------------------------
+-- SPEC PCB LEDs and BUTTONs --
+---------------------------------------------------------------------------------------------------
+-- Note: all spec_aux signals are active low
+
+---------------------------------------------------------------------------------------------------
+ button_with_20MHz_clk: process (clk_20mhz_i)
+ begin
+ if rising_edge (clk_20mhz_i) then
+ spec_aux_led_2_o <= spec_aux_butt_1_i;
+ spec_aux_led_1_o <= spec_aux_butt_1_i;
+ end if;
+ end process;
+
+---------------------------------------------------------------------------------------------------
+ button_with_125MHz_clk: process (clk_125mhz_i)
+ begin
+ if rising_edge (clk_125mhz_i) then
+ spec_aux_led_3_o <= spec_aux_butt_2_i;
+ spec_aux_led_4_o <= spec_aux_butt_2_i;
+ end if;
+ end process;
+
+
+end rtl;
+----------------------------------------------------------------------------------------------------
+-- architecture ends
+----------------------------------------------------------------------------------------------------
\ No newline at end of file
diff --git a/hdl/spec/src/rtl/reg_ctrl.vhd b/hdl/spec/src/rtl/reg_ctrl.vhd
index 56d38f6..979c7bc 100644
--- a/hdl/spec/src/rtl/reg_ctrl.vhd
+++ b/hdl/spec/src/rtl/reg_ctrl.vhd
@@ -136,6 +136,10 @@ entity reg_ctrl is
-- Signal to the data_formatting unit
dacapo_c_rst_p_o : out std_logic; -- clears the dacapo counter
+ -- Signals to the clks_resets_manager ubit
+ send_dac_word_p_o : out std_logic; -- starts spi_dac_
+ dac_word_o : out std_logic_vector(23 downto 0);
+
-- Signal to the one_hz_gen unit
load_utc_p_o : out std_logic;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
@@ -157,11 +161,15 @@ end reg_ctrl;
--=================================================================================================
architecture rtl of reg_ctrl is
- signal acam_config : config_vector;
- signal reg_adr : std_logic_vector(7 downto 0);
- signal starting_utc, acam_inputs_en, start_phase, ctrl_reg : std_logic_vector(g_width-1 downto 0);
- signal one_hz_phase, irq_tstamp_threshold, irq_time_threshold : std_logic_vector(g_width-1 downto 0);
- signal clear_ctrl_reg : std_logic;
+ signal acam_config : config_vector;
+ signal reg_adr : std_logic_vector(7 downto 0);
+ signal starting_utc, acam_inputs_en, start_phase : std_logic_vector(g_width-1 downto 0);
+ signal ctrl_reg, one_hz_phase, irq_tstamp_threshold : std_logic_vector(g_width-1 downto 0);
+ signal irq_time_threshold : std_logic_vector(g_width-1 downto 0);
+ signal clear_ctrl_reg, send_dac_word_p : std_logic;
+ signal dac_word : std_logic_vector(23 downto 0);
+ signal pulse_extender_en : std_logic;
+ signal pulse_extender_c : std_logic_vector(2 downto 0);
--=================================================================================================
-- architecture begin
@@ -275,7 +283,7 @@ begin
-- to be loaded locally.
-- The following information is received:
-- o acam_inputs_en: for the activation of the stop signals arriving to the ACAM
--- o starting_utc : think not useful......
+-- o starting_utc
-- o one_hz_phase : think not useful......
-- o start_phase : think not useful......
TDCcore_config_reg_reception: process (clk_i)
@@ -286,8 +294,10 @@ begin
starting_utc <= (others =>'0');
start_phase <= (others =>'0');
one_hz_phase <= (others =>'0');
- irq_tstamp_threshold <= (others =>'0');
- irq_time_threshold <= (others =>'0');
+ irq_tstamp_threshold <= x"00000100"; -- default 256 timestamps: full memory
+ irq_time_threshold <= x"00000078"; -- default 2 minutes
+ dac_word <= c_DEFAULT_DAC_WORD; -- for DAC Vout = 1.65
+
elsif gnum_csr_cyc_i = '1' and gnum_csr_stb_i = '1' and gnum_csr_we_i = '1' then
@@ -307,13 +317,18 @@ begin
one_hz_phase <= gnum_csr_dat_i;
end if;
- if reg_adr = c_IRQ_TSTAMP_THRESHOLD then
+ if reg_adr = c_IRQ_TSTAMP_THRESH_ADR then
irq_tstamp_threshold <= gnum_csr_dat_i;
end if;
- if reg_adr = c_IRQ_TIME_THRESHOLD then
+ if reg_adr = c_IRQ_TIME_THRESH_ADR then
irq_time_threshold <= gnum_csr_dat_i;
end if;
+
+ if reg_adr = c_DAC_WORD_ADR then
+ dac_word <= gnum_csr_dat_i(23 downto 0);
+ end if;
+
end if;
end if;
end process;
@@ -325,6 +340,7 @@ begin
one_hz_phase_o <= one_hz_phase;
irq_tstamp_threshold_o <= irq_tstamp_threshold;
irq_time_threshold_o <= irq_time_threshold;
+ dac_word_o <= dac_word;
@@ -370,9 +386,26 @@ begin
acam_rst_p_o <= ctrl_reg(8);
load_utc_p_o <= ctrl_reg(9);
dacapo_c_rst_p_o <= ctrl_reg(10);
--- ctrl_reg bits 11 to 31 not used for the moment!
-
+ send_dac_word_p <= ctrl_reg(11);
+-- ctrl_reg bits 12 to 31 not used for the moment!
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+-- Pulse_stretcher: Increases the width of the send_dac_word_p pulse so that it can be sampled
+-- by the 20 MHz clock of the clks_rsts_manager that is communication with the DAC.
+
+ Pulse_stretcher: incr_counter
+ generic map
+ (width => 3)
+ port map
+ (clk_i => clk_i,
+ rst_i => send_dac_word_p,
+ counter_top_i => "111",
+ counter_incr_en_i => pulse_extender_en,
+ counter_is_full_o => open,
+ counter_o => pulse_extender_c);
+
+ pulse_extender_en <= '1' when pulse_extender_c < "111" else '0';
+ send_dac_word_p_o <= pulse_extender_en;
---------------------------------------------------------------------------------------------------
-- Delivery of ACAM and TDC core Readback Registers --
@@ -420,8 +453,9 @@ begin
acam_inputs_en when c_ACAM_INPUTS_EN_ADR,
start_phase when c_START_PHASE_ADR,
one_hz_phase when c_ONE_HZ_PHASE_ADR,
- irq_tstamp_threshold when c_IRQ_TSTAMP_THRESHOLD,
- irq_time_threshold when c_IRQ_TIME_THRESHOLD,
+ irq_tstamp_threshold when c_IRQ_TSTAMP_THRESH_ADR,
+ irq_time_threshold when c_IRQ_TIME_THRESH_ADR,
+ x"00" & dac_word when c_DAC_WORD_ADR,
----------------------------------------------------
-- regs written locally by the TDC core units
diff --git a/hdl/spec/src/rtl/start_retrig_ctrl.vhd b/hdl/spec/src/rtl/start_retrig_ctrl.vhd
index d576b82..e9ca552 100644
--- a/hdl/spec/src/rtl/start_retrig_ctrl.vhd
+++ b/hdl/spec/src/rtl/start_retrig_ctrl.vhd
@@ -151,8 +151,9 @@ entity start_retrig_ctrl is
-- OUTPUTS
-- Signals to the data_formatting unit
+ roll_over_incr_recent_o : out std_logic;
clk_i_cycles_offset_o : out std_logic_vector(g_width-1 downto 0);
- current_roll_over_o : out std_logic_vector(g_width-1 downto 0);
+ roll_over_nb_o : out std_logic_vector(g_width-1 downto 0);
retrig_nb_offset_o : out std_logic_vector(g_width-1 downto 0));
end start_retrig_ctrl;
@@ -286,7 +287,7 @@ begin
clk_i_cycles_offset <= (others=>'0');
retrig_nb_offset <= (others=>'0');
- elsif one_hz_p_i ='1' then
+ elsif one_hz_p_i = '1' then
clk_i_cycles_offset <= current_cycles;
retrig_nb_offset <= current_retrig_nb;
end if;
@@ -297,9 +298,11 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- outputs
- clk_i_cycles_offset_o <= clk_i_cycles_offset;
- retrig_nb_offset_o <= retrig_nb_offset;
- current_roll_over_o <= roll_over_c;
+ roll_over_incr_recent_o <= '1' when unsigned(current_retrig_nb) < 64 else '0';
+ clk_i_cycles_offset_o <= clk_i_cycles_offset;
+ retrig_nb_offset_o <= retrig_nb_offset;
+ roll_over_nb_o <= roll_over_c;
+
end architecture rtl;
diff --git a/hdl/spec/src/rtl/start_retrigger_control.vhd b/hdl/spec/src/rtl/start_retrigger_control.vhd
deleted file mode 100644
index 8518a7a..0000000
--- a/hdl/spec/src/rtl/start_retrigger_control.vhd
+++ /dev/null
@@ -1,209 +0,0 @@
-----------------------------------------------------------------------------------------------------
--- CERN-BE-CO-HT
-----------------------------------------------------------------------------------------------------
---
--- unit name : start retrigger control and internal start number offset generator
--- (start_retrigger_control)
--- author : G. Penacoba
--- date : July 2011
--- version : Revision 1
--- description : launches the start pulses and the ACAM generates the internal start retriggers.
--- Also generates the offset to be added to the start number provided by tha Acam
--- by counting the number of times the 1-Byte counter of the Acam is overloaded.
--- The result is then multiplied by 256 (shifted by 8).
--- dependencies:
--- references :
--- modified by :
---
-----------------------------------------------------------------------------------------------------
--- last changes:
-----------------------------------------------------------------------------------------------------
--- to do: NEEDS TO BE COMPLETELY REVAMPED AFTER DECISION FOR UNIQUE START. ROLL OVER COUNTER etc..
-----------------------------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.tdc_core_pkg.all;
-
-----------------------------------------------------------------------------------------------------
--- entity declaration for start_retrigger_control
-----------------------------------------------------------------------------------------------------
-entity start_retrigger_control is
- generic(
- g_width : integer :=32
- );
- port(
- acam_rise_intflag_p_i : in std_logic;
- acam_fall_intflag_p_i : in std_logic;
- clk : in std_logic;
- one_hz_p_i : in std_logic;
- reset_i : in std_logic;
- retrig_period_i : in std_logic_vector(g_width-1 downto 0);
-
- clk_cycles_offset_o : out std_logic_vector(g_width-1 downto 0);
- current_roll_over_o : out std_logic_vector(g_width-1 downto 0);
- retrig_nb_offset_o : out std_logic_vector(g_width-1 downto 0)
- );
-end start_retrigger_control;
-
-----------------------------------------------------------------------------------------------------
--- architecture declaration for start_retrigger_control
-----------------------------------------------------------------------------------------------------
-architecture rtl of start_retrigger_control is
-
- component free_counter is
- generic(
- width : integer :=32
- );
- port(
- clk : in std_logic;
- enable : in std_logic;
- reset : in std_logic;
- start_value : in std_logic_vector(width-1 downto 0);
-
- count_done : out std_logic;
- current_value : out std_logic_vector(width-1 downto 0)
- );
- end component;
-
- component incr_counter
- generic(
- width : integer :=32
- );
- port(
- clk : in std_logic;
- end_value : in std_logic_vector(width-1 downto 0);
- incr : in std_logic;
- reset : in std_logic;
-
- count_done : out std_logic;
- current_value : out std_logic_vector(width-1 downto 0)
- );
- end component;
-
-signal acam_fall_intflag_p : std_logic;
-signal acam_rise_intflag_p : std_logic;
-signal add_roll_over : std_logic;
-signal clk_cycles_offset : std_logic_vector(g_width-1 downto 0);
-signal current_cycles, current_cycles_2 : std_logic_vector(g_width-1 downto 0);
-signal current_cycles_2_2 : unsigned(5 downto 0);
-signal current_retrig_nb : std_logic_vector(g_width-1 downto 0);
-signal one_hz_p : std_logic;
-signal reset : std_logic;
-signal retrig_nb_offset : std_logic_vector(g_width-1 downto 0);
-signal retrig_nb_reset : std_logic;
-signal retrig_p, retrig_p2 : std_logic;
-signal retrig_period : std_logic_vector(g_width-1 downto 0);
-signal retrig_period_reset : std_logic;
-signal roll_over_reset : std_logic;
-signal roll_over_value : std_logic_vector(g_width-1 downto 0);
-signal cycles_c_restart, current_cycles_2_is_full : std_logic;
-----------------------------------------------------------------------------------------------------
--- architecture begins
-----------------------------------------------------------------------------------------------------
-begin
-
- retrig_period_counter: free_counter
- generic map(
- width => g_width
- )
- port map(
- clk => clk,
- enable => '1',
- reset => retrig_period_reset,
- start_value => retrig_period,
-
- count_done => retrig_p,
- current_value => current_cycles
- );
-
------------------------------------------------------------------
- retrig_period_counter2: incr_counter
- generic map
- (width => g_width)
- port map
- (clk => clk,
- reset => cycles_c_restart,
- end_value => retrig_period_i,
- incr => '1',
- -------------------------------------------
- count_done => open,
- current_value => current_cycles_2);
- -------------------------------------------
-
- cycles_c_restart <= acam_fall_intflag_p or current_cycles_2_is_full;
- current_cycles_2_is_full <= '1' when (unsigned(current_cycles_2) = (unsigned(retrig_period_i) - "1")) else '0';
- --(current_cycles_2_2) <= unsigned(current_cycles_2) -1;
-
------------------------------------------------------------------
-
-
- retrig_nb_counter: incr_counter
- generic map(
- width => g_width
- )
- port map(
- clk => clk,
- end_value => x"00000100",
- incr => retrig_p,
- reset => retrig_nb_reset,
-
- count_done => open,
- current_value => current_retrig_nb
- );
- -- These two counters keep a track of the current internal start retrigger
- -- of the Acam in parallel with the Acam itself
-
- roll_over_counter: incr_counter
- generic map(
- width => g_width
- )
- port map(
- clk => clk,
- end_value => x"FFFFFFFF",
- incr => add_roll_over,
- reset => roll_over_reset,
-
- count_done => open,
- current_value => roll_over_value
- );
- -- This counter keeps track of the number of overflows of the Acam counter
- -- for the internal start retrigger
-
- capture_offset: process
- begin
- if reset ='1' then
- clk_cycles_offset <= (others=>'0');
- retrig_nb_offset <= (others=>'0');
- elsif one_hz_p ='1' then
- clk_cycles_offset <= current_cycles;
- retrig_nb_offset <= current_retrig_nb;
- end if;
- wait until clk ='1';
- end process;
- -- When a new second starts, all values are captured and stored as offsets.
- -- when a timestamps arrives, these offset will be subrstracted in order
- -- to base the final timestamp with respect to the current second.
-
- retrig_period_reset <= acam_fall_intflag_p;
- retrig_nb_reset <= acam_fall_intflag_p;
- roll_over_reset <= one_hz_p;
- add_roll_over <= acam_fall_intflag_p;
-
- -- inputs
- acam_fall_intflag_p <= acam_fall_intflag_p_i;
- acam_rise_intflag_p <= acam_rise_intflag_p_i;
- one_hz_p <= one_hz_p_i;
- reset <= reset_i;
- retrig_period <= retrig_period_i;
-
- -- outputs
- clk_cycles_offset_o <= clk_cycles_offset;
- retrig_nb_offset_o <= retrig_nb_offset;
- current_roll_over_o <= roll_over_value;
-
-end rtl;
-----------------------------------------------------------------------------------------------------
--- architecture ends
-----------------------------------------------------------------------------------------------------
diff --git a/hdl/spec/src/rtl/tdc_core_pkg.vhd b/hdl/spec/src/rtl/tdc_core_pkg.vhd
index 993e6ea..7251c01 100644
--- a/hdl/spec/src/rtl/tdc_core_pkg.vhd
+++ b/hdl/spec/src/rtl/tdc_core_pkg.vhd
@@ -71,6 +71,13 @@ package tdc_core_pkg is
constant c_SIM_CLK_PERIOD : std_logic_vector(31 downto 0) := x"0001E848";
+---------------------------------------------------------------------------------------------------
+-- Constant regarding the Mezzanine DAC configuration --
+---------------------------------------------------------------------------------------------------
+ -- Vout = Vref (DAC_WORD/ 65536); for Vout = 1.65V, with Vref = 2.5V the DAC_WORD = xA8F5
+ constant c_DEFAULT_DAC_WORD : std_logic_vector(23 downto 0) := x"00A8F5";
+
+
---------------------------------------------------------------------------------------------------
-- Constants regarding TDC core and GNUM core addressing --
---------------------------------------------------------------------------------------------------
@@ -151,9 +158,10 @@ package tdc_core_pkg is
constant c_START_PHASE_ADR : std_logic_vector(7 downto 0) := x"22"; -- address 20088 of gnum BAR 0
constant c_ONE_HZ_PHASE_ADR : std_logic_vector(7 downto 0) := x"23"; -- address 2008C of gnum BAR 0
- constant c_IRQ_TSTAMP_THRESHOLD : std_logic_vector(7 downto 0) := x"24"; -- address 20090 of gnum BAR 0
- constant c_IRQ_TIME_THRESHOLD : std_logic_vector(7 downto 0) := x"25"; -- address 20090 of gnum BAR 0
--- constant c_RESERVED0 : std_logic_vector(7 downto 0) := x"26"; -- address 20098 of gnum BAR 0
+ constant c_IRQ_TSTAMP_THRESH_ADR: std_logic_vector(7 downto 0) := x"24"; -- address 20090 of gnum BAR 0
+ constant c_IRQ_TIME_THRESH_ADR : std_logic_vector(7 downto 0) := x"25"; -- address 20090 of gnum BAR 0
+ constant c_DAC_WORD_ADR : std_logic_vector(7 downto 0) := x"26"; -- address 20098 of gnum BAR 0
+
-- constant c_RESERVED1 : std_logic_vector(7 downto 0) := x"27"; -- address 2009C of gnum BAR 0
---------------------------------------------------------------------------------------------------
@@ -266,8 +274,9 @@ package tdc_core_pkg is
acam_intflag_f_edge_p_i : in std_logic;
one_hz_p_i : in std_logic;
----------------------------------------------------------------------
+ roll_over_incr_recent_o : out std_logic;
clk_i_cycles_offset_o : out std_logic_vector(g_width-1 downto 0);
- current_roll_over_o : out std_logic_vector(g_width-1 downto 0);
+ roll_over_nb_o : out std_logic_vector(g_width-1 downto 0);
retrig_nb_offset_o : out std_logic_vector(g_width-1 downto 0));
----------------------------------------------------------------------
end component;
@@ -370,6 +379,8 @@ package tdc_core_pkg is
load_utc_p_o : out std_logic;
irq_tstamp_threshold_o : out std_logic_vector(g_width-1 downto 0);
irq_time_threshold_o : out std_logic_vector(g_width-1 downto 0);
+ send_dac_word_p_o : out std_logic;
+ dac_word_o : out std_logic_vector(23 downto 0);
dacapo_c_rst_p_o : out std_logic;
acam_config_o : out config_vector;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
@@ -404,27 +415,29 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
component data_formatting
port
- (tstamp_wr_wb_ack_i : in std_logic;
- tstamp_wr_dat_i : in std_logic_vector(127 downto 0);
- acam_tstamp1_i : in std_logic_vector(31 downto 0);
- acam_tstamp1_ok_p_i : in std_logic;
- acam_tstamp2_i : in std_logic_vector(31 downto 0);
- acam_tstamp2_ok_p_i : in std_logic;
- clk_i : in std_logic;
- dacapo_c_rst_p_i : in std_logic;
- rst_i : in std_logic;
- clk_i_cycles_offset_i : in std_logic_vector(31 downto 0);
- current_roll_over_i : in std_logic_vector(31 downto 0);
- local_utc_i : in std_logic_vector(31 downto 0);
- retrig_nb_offset_i : in std_logic_vector(31 downto 0);
+ (tstamp_wr_wb_ack_i : in std_logic;
+ tstamp_wr_dat_i : in std_logic_vector(127 downto 0);
+ acam_tstamp1_i : in std_logic_vector(31 downto 0);
+ acam_tstamp1_ok_p_i : in std_logic;
+ acam_tstamp2_i : in std_logic_vector(31 downto 0);
+ acam_tstamp2_ok_p_i : in std_logic;
+ clk_i : in std_logic;
+ dacapo_c_rst_p_i : in std_logic;
+ rst_i : in std_logic;
+ roll_over_incr_recent_i : in std_logic;
+ clk_i_cycles_offset_i : in std_logic_vector(31 downto 0);
+ roll_over_nb_i : in std_logic_vector(31 downto 0);
+ local_utc_i : in std_logic_vector(31 downto 0);
+ retrig_nb_offset_i : in std_logic_vector(31 downto 0);
+ one_hz_p_i : in std_logic;
----------------------------------------------------------------------
- tstamp_wr_wb_adr_o : out std_logic_vector(7 downto 0);
- tstamp_wr_wb_cyc_o : out std_logic;
- tstamp_wr_dat_o : out std_logic_vector(127 downto 0);
- tstamp_wr_wb_stb_o : out std_logic;
- tstamp_wr_wb_we_o : out std_logic;
- tstamp_wr_p_o : out std_logic;
- wr_index_o : out std_logic_vector(31 downto 0));
+ tstamp_wr_wb_adr_o : out std_logic_vector(7 downto 0);
+ tstamp_wr_wb_cyc_o : out std_logic;
+ tstamp_wr_dat_o : out std_logic_vector(127 downto 0);
+ tstamp_wr_wb_stb_o : out std_logic;
+ tstamp_wr_wb_we_o : out std_logic;
+ tstamp_wr_p_o : out std_logic;
+ wr_index_o : out std_logic_vector(31 downto 0));
----------------------------------------------------------------------
end component;
@@ -467,30 +480,66 @@ package tdc_core_pkg is
irq_p_o : out std_logic);
end component irq_controller;
+
---------------------------------------------------------------------------------------------------
component clks_rsts_manager
generic
- (nb_of_reg : integer := 68;
- values_for_simulation : boolean := FALSE);
+ (nb_of_reg : integer := 68);
port
- (acam_refclk_i : in std_logic;
- pll_ld_i : in std_logic;
- pll_refmon_i : in std_logic;
- pll_sdo_i : in std_logic;
- pll_status_i : in std_logic;
- gnum_rst_i : in std_logic;
- spec_clk_i : in std_logic;
- tdc_clk_p_i : in std_logic;
- tdc_clk_n_i : in std_logic;
+ (spec_clk_i : in std_logic;
+ acam_refclk_i : in std_logic;
+ tdc_clk_p_i : in std_logic;
+ tdc_clk_n_i : in std_logic;
+ rst_n_a_i : in std_logic;
+ pll_ld_i : in std_logic;
+ pll_refmon_i : in std_logic;
+ pll_sdo_i : in std_logic;
+ pll_status_i : in std_logic;
+ send_dac_word_p_i : in std_logic;
+ dac_word_i : in std_logic_vector(23 downto 0);
----------------------------------------------------------------------
+ tdc_clk_o : out std_logic;
+ internal_rst_o : out std_logic;
+ spec_clk_o : out std_logic;
+ gnum_rst_o : out std_logic;
acam_refclk_r_edge_p_o : out std_logic;
- internal_rst_o : out std_logic;
- pll_cs_o : out std_logic;
- pll_dac_sync_o : out std_logic;
- pll_sdi_o : out std_logic;
- pll_sclk_o : out std_logic;
- spec_clk_o : out std_logic;
- tdc_clk_o : out std_logic);
+ pll_cs_o : out std_logic;
+ pll_dac_sync_o : out std_logic;
+ pll_sdi_o : out std_logic;
+ pll_sclk_o : out std_logic;
+ pll_ld_o : out std_logic);
+ ----------------------------------------------------------------------
+ end component;
+
+
+---------------------------------------------------------------------------------------------------
+ component leds_manager is
+ generic
+ (g_width : integer := 32;
+ values_for_simulation : boolean := FALSE);
+ port
+ (clk_20mhz_i : in std_logic;
+ clk_125mhz_i : in std_logic;
+ gnum_rst_i : in std_logic;
+ internal_rst_i : in std_logic;
+ pll_ld_i : in std_logic;
+ spec_aux_butt_1_i : in std_logic;
+ spec_aux_butt_2_i : in std_logic;
+ one_hz_p_i : in std_logic;
+ acam_inputs_en_i : in std_logic_vector(g_width-1 downto 0);
+ ----------------------------------------------------------------------
+ tdc_led_status_o : out std_logic;
+ tdc_led_trig1_o : out std_logic;
+ tdc_led_trig2_o : out std_logic;
+ tdc_led_trig3_o : out std_logic;
+ tdc_led_trig4_o : out std_logic;
+ tdc_led_trig5_o : out std_logic;
+ spec_led_green_o : out std_logic;
+ spec_led_red_o : out std_logic;
+ spec_aux_led_1_o : out std_logic;
+ spec_aux_led_2_o : out std_logic;
+ spec_aux_led_3_o : out std_logic;
+ spec_aux_led_4_o : out std_logic);
----------------------------------------------------------------------
end component;
diff --git a/hdl/spec/src/rtl/top_tdc.vhd b/hdl/spec/src/rtl/top_tdc.vhd
index 110f80c..3a187a3 100644
--- a/hdl/spec/src/rtl/top_tdc.vhd
+++ b/hdl/spec/src/rtl/top_tdc.vhd
@@ -1,875 +1,886 @@
-----------------------------------------------------------------------------------------------------
--- CERN-BE-CO-HT
-----------------------------------------------------------------------------------------------------
---
--- unit name : TDC top level (top_tdc.vhd)
--- author : G. Penacoba
--- date : May 2011
--- version : Revision 1
--- description : top level of tdc project
--- dependencies:
--- references :
--- modified by :
---
-----------------------------------------------------------------------------------------------------
--- last changes:
--- revamping, comments, renamings etc
--- new gnum core integrated
--- clks_rsts_mnger modified
-----------------------------------------------------------------------------------------------------
--- to do:
-----------------------------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.tdc_core_pkg.all;
-use work.gn4124_core_pkg.all;
-use work.gencores_pkg.all;
-use work.wishbone_pkg.all;
-
-----------------------------------------------------------------------------------------------------
--- entity declaration for top_tdc
-----------------------------------------------------------------------------------------------------
-entity top_tdc is
- generic
- (g_span : integer :=32; -- address span in bus interfaces
- g_width : integer :=32; -- data width in bus interfaces
- values_for_simulation : boolean :=FALSE); -- this generic is set to TRUE
- -- when instantiated in a test-bench
- port
- (-- interface with GNUM
- rst_n_a_i : in std_logic;
- -- P2L Direction
- p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
- p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
- p2l_data_i : in std_logic_vector(15 downto 0);-- Parallel receive data
- p2l_dframe_i : in std_logic; -- Receive Frame
- p2l_valid_i : in std_logic; -- Receive Data Valid
- p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
- p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
- p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
- rx_error_o : out std_logic; -- Receive Error
- vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
- -- L2P Direction
- l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
- l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
- l2p_data_o : out std_logic_vector(15 downto 0);-- Parallel transmit data
- l2p_dframe_o : out std_logic; -- Transmit Data Frame
- l2p_valid_o : out std_logic; -- Transmit Data Valid
- l2p_edb_o : out std_logic; -- Packet termination and discard
- l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
- l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
- p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
- tx_error_i : in std_logic; -- Transmit Error
- irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
- spare_o : out std_logic;
-
- -- interface signals with PLL circuit on TDC mezzanine
- acam_refclk_i : in std_logic; -- 31.25 MHz clock that is also received by ACAM
- pll_ld_i : in std_logic; -- PLL AD9516 interface signals
- pll_refmon_i : in std_logic; --
- pll_sdo_i : in std_logic; --
- pll_status_i : in std_logic; --
- tdc_clk_p_i : in std_logic; -- 125 MHz differential clock : system clock
- tdc_clk_n_i : in std_logic; --
-
- pll_cs_o : out std_logic; -- PLL AD9516 interface signals
- pll_dac_sync_o : out std_logic; --
- pll_sdi_o : out std_logic; --
- pll_sclk_o : out std_logic; --
- -- interface signals with acam (timing) on TDC mezzanine
- err_flag_i : in std_logic; -- error flag signal coming from ACAM
- int_flag_i : in std_logic; -- interrupt flag signal coming from ACAM
- start_dis_o : out std_logic; -- start disable signal for ACAM
- start_from_fpga_o : out std_logic; -- start signal for ACAM
- stop_dis_o : out std_logic; -- stop disable signal for ACAM
- -- interface signals with acam (data) on TDC mezzanine
- data_bus_io : inout std_logic_vector(27 downto 0);
- ef1_i : in std_logic; -- empty flag iFIFO1 signal from ACAM
- ef2_i : in std_logic; -- empty flag iFIFO2 signal from ACAM
- lf1_i : in std_logic; -- load flag iFIFO1 signal from ACAM
- lf2_i : in std_logic; -- load flag iFIFO2 signal from ACAM
-
- address_o : out std_logic_vector(3 downto 0);
- cs_n_o : out std_logic; -- chip select for ACAM
- oe_n_o : out std_logic; -- output enable for ACAM
- rd_n_o : out std_logic; -- read signal for ACAM
- wr_n_o : out std_logic; -- write signal for ACAM
-
- -- other signals on the TDC mezzanine
- tdc_in_fpga_5_i : in std_logic; -- input 5 for ACAM is also received by FPGA
- -- all 4 other stop inputs are miss-routed on PCB
- mute_inputs_o : out std_logic; -- controls all 5 inputs (actual function: ENABLE)
- tdc_led_status_o : out std_logic; -- amber led on front pannel
- tdc_led_trig1_o : out std_logic; -- amber leds on front pannel
- tdc_led_trig2_o : out std_logic; --
- tdc_led_trig3_o : out std_logic; --
- tdc_led_trig4_o : out std_logic; --
- tdc_led_trig5_o : out std_logic; --
- term_en_1_o : out std_logic; -- enable of 50 Ohm termination inputs
- term_en_2_o : out std_logic; --
- term_en_3_o : out std_logic; --
- term_en_4_o : out std_logic; --
- term_en_5_o : out std_logic; --
-
- -- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
- carrier_one_wire_b : inout std_logic;
-
- -- Mezzanine system I2C EEPROM
- sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
- sys_sda_b : inout std_logic; -- Mezzanine system I2C data (EEPROM)
-
- -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
- mezz_one_wire_b : inout std_logic;
-
- -- other signals on the SPEC carrier
- spec_aux0_i : in std_logic; -- buttons on spec card
- spec_aux1_i : in std_logic; --
- spec_aux2_o : out std_logic; -- red leds on spec PCB
- spec_aux3_o : out std_logic; --
- spec_aux4_o : out std_logic; --
- spec_aux5_o : out std_logic; --
- spec_led_green_o : out std_logic; -- green led on spec front pannel
- spec_led_red_o : out std_logic; -- red led on spec front pannel
- spec_clk_i : in std_logic); -- 20 MHz clock from VCXO on spec card
-
-end top_tdc;
-
-----------------------------------------------------------------------------------------------------
--- architecture declaration for top_tdc
-----------------------------------------------------------------------------------------------------
-architecture rtl of top_tdc is
-
-
-
- signal clk, spec_clk : std_logic;
-
--- LEDs
- signal spec_led_blink_done, spec_led_period_done, tdc_led_blink_done : std_logic;
- signal spec_led_period : std_logic_vector(g_width-1 downto 0);
- signal visible_blink_length : std_logic_vector(g_width-1 downto 0);
- signal spec_led_green, spec_led_red, tdc_led_status : std_logic;
-
- signal pulse_delay, window_delay, clk_period : std_logic_vector(g_width-1 downto 0);
-
- signal gnum_rst, gnum_rst_synch : std_logic;
-
-
-
- signal acam_ef1, acam_ef2, acam_ef1_meta, acam_ef2_meta : std_logic;
-
- signal acam_errflag_f_edge_p, acam_errflag_r_edge_p, acam_intflag_f_edge_p, acam_refclk_r_edge_p : std_logic;
-
- signal acam_tstamp1, acam_tstamp2 : std_logic_vector(g_width-1 downto 0);
- signal acam_tstamp1_ok_p, acam_tstamp2_ok_p : std_logic;
-
- signal clk_i_cycles_offset, current_roll_over, retrig_nb_offset : std_logic_vector(g_width-1 downto 0);
- signal general_rst, general_rst_n : std_logic;
- signal one_hz_p : std_logic;
-
- signal acm_adr : std_logic_vector(7 downto 0);
- signal acm_cyc, acm_stb, acm_we, acm_ack : std_logic;
- signal acm_dat_r, acm_dat_w : std_logic_vector(g_width-1 downto 0);
-
- signal dma_irq : std_logic_vector(1 downto 0);
- signal irq_to_gn4124 : std_logic;
-
-
- signal wbm_csr_sel : std_logic_vector(3 downto 0);
- signal wbm_csr_stb, wbm_csr_we : std_logic;
-
-
- signal wbm_csr_dat_wr, wbm_csr_dat_rd, dma_dat_rd, dma_dat_wr : std_logic_vector(31 downto 0);
-
-
- signal dma_stb, dma_cyc, dma_we, dma_ack, dma_stall : std_logic;
- signal dma_adr : std_logic_vector(31 downto 0);
- signal dma_sel : std_logic_vector(3 downto 0);
-
-
- signal mem_class_adr : std_logic_vector(7 downto 0);
- signal mem_class_stb, mem_class_cyc, mem_class_we, mem_class_ack : std_logic;
- signal mem_class_data_wr, mem_class_data_rd : std_logic_vector(4*g_width-1 downto 0);
-
- signal wb_csr_adr_decoded : std_logic_vector(g_span-1 downto 0);
- signal wb_csr_dat_wr_decoded : std_logic_vector(g_width-1 downto 0);
- signal wb_csr_stb_decoded : std_logic;
- signal wb_csr_we_decoded : std_logic;
-
-
- signal activate_acq_p, deactivate_acq_p, load_acam_config, read_acam_config : std_logic;
- signal read_acam_status, read_ififo1, read_ififo2, read_start01, reset_acam : std_logic;
- signal load_utc, clear_dacapo_counter : std_logic;
-
- signal starting_utc : std_logic_vector(g_width-1 downto 0);
- signal acam_inputs_en, irq_tstamp_threshold, irq_time_threshold : std_logic_vector(g_width-1 downto 0);
- signal acam_config : config_vector;
- signal acam_config_rdbk : config_vector;
- signal acam_status, acam_ififo1, acam_ififo2, acam_start01 : std_logic_vector(g_width-1 downto 0);
-
- signal local_utc, irq_code, wr_index, core_status : std_logic_vector(g_width-1 downto 0);
- signal irq_sources : std_logic_vector(g_width-1 downto 0);
-
-
- signal wb_csr_cyc_decoded, wb_all_csr_ack, wb_all_csr_stall : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
- signal wb_all_csr_dat_rd : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0);
-
- signal wb_csr_sel_decoded : std_logic_vector (3 downto 0);
-
- signal wbm_csr_adr : std_logic_vector (31 downto 0);
- signal wbm_csr_cyc, wbm_csr_ack_decoded, wbm_stall : std_logic;
-
- -- Mezzanine 1-wire
- signal mezz_owr_pwren : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
- signal mezz_owr_en : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
- signal mezz_owr_i : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
-
- -- Carrier 1-wire
- signal carrier_owr_en : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
- signal carrier_owr_i : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
-
- -- Mezzanine system I2C for EEPROM
- signal sys_scl_in, sys_scl_out, sys_scl_oe_n : std_logic;
- signal sys_sda_in, sys_sda_out, sys_sda_oe_n : std_logic;
-
- signal tstamp_wr_p, irq_tstamp_p, irq_time_p : std_logic;
-
--- <acam_status_i<31:0>> is never used.
--- <adr_i<7:4>> is never used.
--- <dat_i<31:28>> is never used.
--- <tstamp_wr_dat_i<127:0>> is never used.
--- <acam_tstamp1_i<30:30>> is never used.
--- <acam_tstamp1_i<28:28>> is never used.
--- <acam_tstamp2_i<31:31>> is never used.
--- <acam_tstamp2_i<29:29>> is never used.
--- <gnum_dma_adr_i<31:10>> is never used.
--- <wbm_adr_i<31:18> never used
--- gnum_csr_adr_i<31:8> is never used
-
-----------------------------------------------------------------------------------------------------
--- architecture begins
-----------------------------------------------------------------------------------------------------
-begin
-
----------------------------------------------------------------------------------------------------
--- WISHBONE CSR DECODER --
----------------------------------------------------------------------------------------------------
--- CSR wishbone address decoder
--- 0x00000 -> DMA configuration
--- 0x20000 -> TDC core & ACAM
--- 0x40000 -> Carrier 1-wire master (Unidue ID & Thermometer)
--- 0x60000 -> Mezzanine I2C master (EEPROM)
--- 0x80000 -> Mezzanine 1-wire master (Unidue ID & Thermometer)
--- 0xA0000 -> Interrupt controller
-
- address_decoder:wb_addr_decoder
- generic map
- (g_WINDOW_SIZE => c_BAR0_APERTURE, -- note: c_BAR0_APERTURE = 18
- g_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB) -- note: c_CSR_WB_SLAVES_NB = 5
- port map
- (clk_i => clk,
- rst_n_i => rst_n_a_i,
- -- WISHBONE master interface
- wbm_adr_i => wbm_csr_adr,
- wbm_dat_i => wbm_csr_dat_wr,
- wbm_sel_i => wbm_csr_sel,
- wbm_stb_i => wbm_csr_stb,
- wbm_we_i => wbm_csr_we,
- wbm_cyc_i => wbm_csr_cyc,
- wbm_ack_o => wbm_csr_ack_decoded,
- wbm_dat_o => wbm_csr_dat_rd,
- wbm_stall_o => wbm_stall,
- -- WISHBONE slaves interface
- wb_dat_i => wb_all_csr_dat_rd,
- wb_ack_i => wb_all_csr_ack,
- wb_stall_i => wb_all_csr_stall,
- wb_cyc_o => wb_csr_cyc_decoded,
- wb_stb_o => wb_csr_stb_decoded,
- wb_we_o => wb_csr_we_decoded,
- wb_sel_o => wb_csr_sel_decoded, -- Byte select???
- wb_adr_o => wb_csr_adr_decoded,
- wb_dat_o => wb_csr_dat_wr_decoded);
-
-
----------------------------------------------------------------------------------------------------
--- INTERRUPTS CONTROLLER --
----------------------------------------------------------------------------------------------------
- cmp_irq_controller : irq_controller
- port map
- (clk_i => clk,
- rst_n_i => general_rst_n,
- irq_src_p_i => irq_sources,
- irq_p_o => irq_to_gn4124,
- wb_adr_i => wb_csr_adr_decoded(1 downto 0),
- wb_dat_i => wb_csr_dat_wr_decoded,
- wb_dat_o => wb_all_csr_dat_rd(c_CSR_WB_IRQ_CTRL * 32 + 31 downto c_CSR_WB_IRQ_CTRL * 32),
- wb_cyc_i => wb_csr_cyc_decoded(c_CSR_WB_IRQ_CTRL),
- wb_sel_i => wb_csr_sel_decoded,
- wb_stb_i => wb_csr_stb_decoded,
- wb_we_i => wb_csr_we_decoded,
- wb_ack_o => wb_all_csr_ack(c_CSR_WB_IRQ_CTRL));
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- -- IRQ sources
- irq_sources(1 downto 0) <= dma_irq;
- irq_sources(2) <= irq_tstamp_p;
- irq_sources(3) <= irq_time_p;
- irq_sources(31 downto 4) <= (others => '0');
-
- -- Classic slave supporting single pipelined accesses, stall isn't used
- wb_all_csr_stall(c_CSR_WB_IRQ_CTRL) <= '0';
-
-
----------------------------------------------------------------------------------------------------
--- CARRIER 1-wire MASTER DS18B20 (thermometer + unique ID) --
----------------------------------------------------------------------------------------------------
--- Note: c_CSR_WB_CARRIER_ONE_WIRE = 2
- carrier_OneWire : wb_onewire_master
- generic map
- (g_num_ports => 1,
- g_ow_btp_normal => "5.0",
- g_ow_btp_overdrive => "1.0")
- port map
- (clk_sys_i => clk,
- rst_n_i => general_rst_n,
- wb_adr_i => wb_csr_adr_decoded(2 downto 0),
- wb_dat_i => wb_csr_dat_wr_decoded,
- wb_cyc_i => wb_csr_cyc_decoded(c_CSR_WB_CARRIER_ONE_WIRE),
- wb_sel_i => wb_csr_sel_decoded,
- wb_stb_i => wb_csr_stb_decoded,
- wb_we_i => wb_csr_we_decoded,
-
- wb_dat_o => wb_all_csr_dat_rd(c_CSR_WB_CARRIER_ONE_WIRE * 32 + 31 downto 32 * c_CSR_WB_CARRIER_ONE_WIRE),
- wb_ack_o => wb_all_csr_ack(c_CSR_WB_CARRIER_ONE_WIRE),
- wb_int_o => open,
- owr_pwren_o => open,
- owr_en_o => carrier_owr_en,
- owr_i => carrier_owr_i);
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- carrier_one_wire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
- carrier_owr_i(0) <= carrier_one_wire_b;
-
- -- Classic slave supporting single pipelined accesses, stall isn't used
- wb_all_csr_stall(c_CSR_WB_CARRIER_ONE_WIRE) <= '0';
-
-
----------------------------------------------------------------------------------------------------
--- Mezzanine System managment I2C Master, EEPROM access --
----------------------------------------------------------------------------------------------------
--- Note: c_CSR_WB_FMC_SYS_I2C = 3
- mezzanine_I2C_master_EEPROM : wb_i2c_master
- port map
- (clk_sys_i => clk,
- rst_n_i => general_rst_n,
- wb_adr_i => wb_csr_adr_decoded(4 downto 0),
- wb_dat_i => wb_csr_dat_wr_decoded,
- wb_we_i => wb_csr_we_decoded,
- wb_stb_i => wb_csr_stb_decoded,
- wb_sel_i => wb_csr_sel_decoded,
- wb_cyc_i => wb_csr_cyc_decoded(c_CSR_WB_FMC_SYS_I2C),
- wb_ack_o => wb_all_csr_ack(c_CSR_WB_FMC_SYS_I2C),
- wb_int_o => open,
- wb_dat_o => wb_all_csr_dat_rd(c_CSR_WB_FMC_SYS_I2C * 32 + 31 downto 32 * c_CSR_WB_FMC_SYS_I2C),
-
- scl_pad_i => sys_scl_in,
- scl_pad_o => sys_scl_out,
- scl_padoen_o => sys_scl_oe_n,
- sda_pad_i => sys_sda_in,
- sda_pad_o => sys_sda_out,
- sda_padoen_o => sys_sda_oe_n);
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- -- Classic slave supporting single pipelined accesses, stall isn't used
- wb_all_csr_stall(c_CSR_WB_FMC_SYS_I2C) <= '0';
-
- -- Tri-state buffer for SDA and SCL
- sys_scl_b <= sys_scl_out when sys_scl_oe_n = '0' else 'Z';
- sys_scl_in <= sys_scl_b;
-
- sys_sda_b <= sys_sda_out when sys_sda_oe_n = '0' else 'Z';
- sys_sda_in <= sys_sda_b;
-
----------------------------------------------------------------------------------------------------
--- Mezzanine 1-wire MASTER DS18B20 (thermometer + unique ID) --
----------------------------------------------------------------------------------------------------
---Note: c_CSR_WB_FMC_ONE_WIRE = 4
- cmp_fmc_onewire : wb_onewire_master
- generic map
- (g_num_ports => 1,
- g_ow_btp_normal => "5.0",
- g_ow_btp_overdrive => "1.0")
- port map
- (clk_sys_i => clk,
- rst_n_i => general_rst_n,
- wb_adr_i => wb_csr_adr_decoded(2 downto 0),
- wb_dat_i => wb_csr_dat_wr_decoded,
- wb_we_i => wb_csr_we_decoded,
- wb_stb_i => wb_csr_stb_decoded,
- wb_sel_i => wb_csr_sel_decoded,
- wb_cyc_i => wb_csr_cyc_decoded(c_CSR_WB_FMC_ONE_WIRE),
- wb_ack_o => wb_all_csr_ack(c_CSR_WB_FMC_ONE_WIRE),
- wb_dat_o => wb_all_csr_dat_rd(c_CSR_WB_FMC_ONE_WIRE * 32 + 31 downto 32 * c_CSR_WB_FMC_ONE_WIRE),
- wb_int_o => open,
- owr_pwren_o => mezz_owr_pwren,
- owr_en_o => mezz_owr_en,
- owr_i => mezz_owr_i);
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- mezz_one_wire_b <= '0' when mezz_owr_en(0) = '1' else 'Z';
- mezz_owr_i(0) <= mezz_one_wire_b;
-
- -- Classic slave supporting single pipelined accesses, stall isn't used
- wb_all_csr_stall(c_CSR_WB_FMC_ONE_WIRE) <= '0';
-
-
----------------------------------------------------------------------------------------------------
--- GNUM CORE --
----------------------------------------------------------------------------------------------------
--- Note: c_CSR_WB_DMA_CONFIG = 0
--- <dma_reg_adr_i<31:4>> is never used.
- gnum_interface_block: gn4124_core --cmp_gn4124_core
- port map
- (rst_n_a_i => rst_n_a_i,
- status_o => open,
- p2l_clk_p_i => p2l_clk_p_i,
- p2l_clk_n_i => p2l_clk_n_i,
- p2l_data_i => p2l_data_i,
- p2l_dframe_i => p2l_dframe_i,
- p2l_valid_i => p2l_valid_i,
- p2l_rdy_o => p2l_rdy_o,
- p_wr_req_i => p_wr_req_i,
- p_wr_rdy_o => p_wr_rdy_o,
- rx_error_o => rx_error_o,
- vc_rdy_i => vc_rdy_i,
- l2p_clk_p_o => l2p_clk_p_o,
- l2p_clk_n_o => l2p_clk_n_o,
- l2p_data_o => l2p_data_o ,
- l2p_dframe_o => l2p_dframe_o,
- l2p_valid_o => l2p_valid_o,
- l2p_edb_o => l2p_edb_o,
- l2p_rdy_i => l2p_rdy_i,
- l_wr_rdy_i => l_wr_rdy_i,
- p_rd_d_rdy_i => p_rd_d_rdy_i,
- tx_error_i => tx_error_i,
- irq_p_o => irq_p_o,
- dma_irq_o => dma_irq,
- irq_p_i => irq_to_gn4124,
- -----CSR all registers classic master-----
- csr_clk_i => clk,
- csr_adr_o => wbm_csr_adr,
- csr_cyc_o => wbm_csr_cyc,
- csr_dat_o => wbm_csr_dat_wr,
- csr_sel_o => wbm_csr_sel,
- csr_stb_o => wbm_csr_stb,
- csr_stall_i => wbm_stall, --<<--
- csr_we_o => wbm_csr_we,
- csr_ack_i => wbm_csr_ack_decoded,
- csr_dat_i => wbm_csr_dat_rd,
- ------------DMA pipelined master----------
- dma_clk_i => clk,
- dma_adr_o => dma_adr,
- dma_cyc_o => dma_cyc,
- dma_dat_o => dma_dat_wr,
- dma_sel_o => dma_sel,
- dma_stb_o => dma_stb,
- dma_we_o => dma_we,
- dma_ack_i => dma_ack,
- dma_dat_i => dma_dat_rd,
- dma_stall_i => dma_stall,
- -------DMA registers classic slave--------
- dma_reg_clk_i => clk,
- dma_reg_adr_i => wb_csr_adr_decoded,
- dma_reg_dat_i => wb_csr_dat_wr_decoded,
- dma_reg_sel_i => wb_csr_sel_decoded,
- dma_reg_stb_i => wb_csr_stb_decoded,
- dma_reg_we_i => wb_csr_we_decoded,
- dma_reg_cyc_i => wb_csr_cyc_decoded(c_CSR_WB_DMA_CONFIG),
- dma_reg_dat_o => wb_all_csr_dat_rd(c_CSR_WB_DMA_CONFIG * 32 + 31 downto 32 * c_CSR_WB_DMA_CONFIG),
- dma_reg_ack_o => wb_all_csr_ack(c_CSR_WB_DMA_CONFIG),
- dma_reg_stall_o => wb_all_csr_stall(c_CSR_WB_DMA_CONFIG));
-
-
----------------------------------------------------------------------------------------------------
--- TDC REGISTERS CONTROLLER --
----------------------------------------------------------------------------------------------------
--- Note: c_CSR_WB_TDC_CORE = 1
- reg_control_block: reg_ctrl
- generic map
- (g_span => g_span,
- g_width => g_width)
- port map
- (clk_i => clk,
- rst_i => general_rst,
- gnum_csr_adr_i => wb_csr_adr_decoded,
- gnum_csr_dat_i => wb_csr_dat_wr_decoded,
- gnum_csr_stb_i => wb_csr_stb_decoded,
- gnum_csr_we_i => wb_csr_we_decoded,
- gnum_csr_cyc_i => wb_csr_cyc_decoded(c_CSR_WB_TDC_CORE),
- gnum_csr_ack_o => wb_all_csr_ack(c_CSR_WB_TDC_CORE),
- gnum_csr_dat_o => wb_all_csr_dat_rd(c_CSR_WB_TDC_CORE * 32 + 31 downto 32 * c_CSR_WB_TDC_CORE),
-
- activate_acq_p_o => activate_acq_p,
- deactivate_acq_p_o => deactivate_acq_p,
- acam_wr_config_p_o => load_acam_config,
- acam_rdbk_config_p_o => read_acam_config,
- acam_rdbk_status_p_o => read_acam_status,
- acam_rdbk_ififo1_p_o => read_ififo1,
- acam_rdbk_ififo2_p_o => read_ififo2,
- acam_rdbk_start01_p_o => read_start01,
- acam_rst_p_o => reset_acam,
- load_utc_p_o => load_utc,
- dacapo_c_rst_p_o => clear_dacapo_counter,
- acam_config_rdbk_i => acam_config_rdbk,
- acam_status_i => acam_status,
- acam_ififo1_i => acam_ififo1,
- acam_ififo2_i => acam_ififo2,
- acam_start01_i => acam_start01,
- local_utc_i => local_utc,
- irq_code_i => irq_code,
- core_status_i => core_status,
- wr_index_i => wr_index,
- acam_config_o => acam_config,
- starting_utc_o => starting_utc,
- acam_inputs_en_o => acam_inputs_en,
- start_phase_o => window_delay,
- irq_tstamp_threshold_o=> irq_tstamp_threshold,
- irq_time_threshold_o => irq_time_threshold,
- one_hz_phase_o => pulse_delay);
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- wb_all_csr_stall(c_CSR_WB_TDC_CORE) <= '0';
-
-
----------------------------------------------------------------------------------------------------
--- ONE HZ GENERATOR --
----------------------------------------------------------------------------------------------------
- one_second_block: one_hz_gen
- generic map
- (g_width => g_width)
- port map
- (acam_refclk_r_edge_p_i => acam_refclk_r_edge_p,
- clk_i => clk,
- clk_period_i => clk_period,
- load_utc_p_i => load_utc,
- pulse_delay_i => pulse_delay,
- rst_i => general_rst,
- starting_utc_i => starting_utc,
- local_utc_o => local_utc,
- one_hz_p_o => one_hz_p);
-
-
----------------------------------------------------------------------------------------------------
--- ACAM TIMECONTROL INTERFACE --
----------------------------------------------------------------------------------------------------
- acam_timing_block: acam_timecontrol_interface
- port map(
- err_flag_i => err_flag_i,
- int_flag_i => int_flag_i,
- start_dis_o => start_dis_o,
- start_from_fpga_o => start_from_fpga_o,
- stop_dis_o => stop_dis_o,
- acam_refclk_r_edge_p_i => acam_refclk_r_edge_p,
- clk_i => clk,
- activate_acq_p_i => activate_acq_p,
- rst_i => general_rst,
- window_delay_i => window_delay,
- acam_errflag_f_edge_p_o => acam_errflag_f_edge_p,
- acam_errflag_r_edge_p_o => acam_errflag_r_edge_p,
- acam_intflag_f_edge_p_o => acam_intflag_f_edge_p);
-
-
----------------------------------------------------------------------------------------------------
--- ACAM DATABUS INTERFACE --
----------------------------------------------------------------------------------------------------
- acam_data_block: acam_databus_interface
- port map
- (ef1_i => ef1_i,
- ef2_i => ef2_i,
- lf1_i => lf1_i,
- lf2_i => lf2_i,
- data_bus_io => data_bus_io,
- adr_o => address_o,
- cs_n_o => cs_n_o,
- oe_n_o => oe_n_o,
- rd_n_o => rd_n_o,
- wr_n_o => wr_n_o,
- ef1_o => acam_ef1,
- ef1_synch1_o => acam_ef1_meta,
- ef2_o => acam_ef2,
- ef2_synch1_o => acam_ef2_meta,
- clk_i => clk,
- rst_i => general_rst,
- adr_i => acm_adr,
- cyc_i => acm_cyc,
- dat_i => acm_dat_w,
- stb_i => acm_stb,
- we_i => acm_we,
- ack_o => acm_ack,
- dat_o => acm_dat_r);
-
-
----------------------------------------------------------------------------------------------------
--- ACAM START RETRIGGER CONTROLLER --
----------------------------------------------------------------------------------------------------
- start_retrigger_block: start_retrig_ctrl
- generic map
- (g_width => g_width)
- port map
- (acam_intflag_f_edge_p_i=> acam_intflag_f_edge_p,
- clk_i => clk,
- one_hz_p_i => one_hz_p,
- rst_i => general_rst,
- clk_i_cycles_offset_o => clk_i_cycles_offset,
- current_roll_over_o => current_roll_over,
- retrig_nb_offset_o => retrig_nb_offset);
-
-
----------------------------------------------------------------------------------------------------
--- DATA ENGINE --
----------------------------------------------------------------------------------------------------
- data_engine_block: data_engine
- port map
- (acam_ack_i => acm_ack,
- acam_dat_i => acm_dat_r,
- acam_adr_o => acm_adr,
- acam_cyc_o => acm_cyc,
- acam_dat_o => acm_dat_w,
- acam_stb_o => acm_stb,
- acam_we_o => acm_we,
- clk_i => clk,
- rst_i => general_rst,
- acam_ef1_i => acam_ef1,
- acam_ef1_synch1_i => acam_ef1_meta,
- acam_ef2_i => acam_ef2,
- acam_ef2_synch1_i => acam_ef2_meta,
- activate_acq_p_i => activate_acq_p,
- deactivate_acq_p_i => deactivate_acq_p,
- acam_wr_config_p_i => load_acam_config,
- acam_rdbk_config_p_i => read_acam_config,
- acam_rdbk_status_p_i => read_acam_status,
- acam_rdbk_ififo1_p_i => read_ififo1,
- acam_rdbk_ififo2_p_i => read_ififo2,
- acam_rdbk_start01_p_i => read_start01,
- acam_rst_p_i => reset_acam,
- acam_config_i => acam_config,
- acam_config_rdbk_o => acam_config_rdbk,
- acam_status_o => acam_status,
- acam_ififo1_o => acam_ififo1,
- acam_ififo2_o => acam_ififo2,
- acam_start01_o => acam_start01,
- acam_tstamp1_o => acam_tstamp1,
- acam_tstamp1_ok_p_o => acam_tstamp1_ok_p,
- acam_tstamp2_o => acam_tstamp2,
- acam_tstamp2_ok_p_o => acam_tstamp2_ok_p);
-
-
----------------------------------------------------------------------------------------------------
--- DATA FORMATTING --
----------------------------------------------------------------------------------------------------
- data_formatting_block: data_formatting
- port map
- (clk_i => clk,
- rst_i => general_rst,
- tstamp_wr_wb_ack_i => mem_class_ack,
- tstamp_wr_dat_i => mem_class_data_rd,
- tstamp_wr_wb_adr_o => mem_class_adr,
- tstamp_wr_wb_cyc_o => mem_class_cyc,
- tstamp_wr_dat_o => mem_class_data_wr,
- tstamp_wr_wb_stb_o => mem_class_stb,
- tstamp_wr_wb_we_o => mem_class_we,
- acam_tstamp1_i => acam_tstamp1,
- acam_tstamp1_ok_p_i => acam_tstamp1_ok_p,
- acam_tstamp2_i => acam_tstamp2,
- acam_tstamp2_ok_p_i => acam_tstamp2_ok_p,
- dacapo_c_rst_p_i => clear_dacapo_counter,
- clk_i_cycles_offset_i => clk_i_cycles_offset,
- current_roll_over_i => current_roll_over,
- retrig_nb_offset_i => retrig_nb_offset,
- local_utc_i => local_utc,
- tstamp_wr_p_o => tstamp_wr_p,
- wr_index_o => wr_index);
-
-
----------------------------------------------------------------------------------------------------
--- INTERRUPTS GENERATOR --
----------------------------------------------------------------------------------------------------
- interrupts_generator: irq_generator
- generic map
- (g_width => 32)
- port map
- (clk_i => clk,
- rst_i => general_rst,
- irq_tstamp_threshold_i => irq_tstamp_threshold,
- irq_time_threshold_i => irq_time_threshold,
- activate_acq_p_i => activate_acq_p,
- deactivate_acq_p_i => deactivate_acq_p,
- tstamp_wr_p_i => tstamp_wr_p,
- one_hz_p_i => one_hz_p,
- irq_tstamp_p_o => irq_tstamp_p,
- irq_time_p_o => irq_time_p);
-
-
----------------------------------------------------------------------------------------------------
--- CIRCULAR BUFFER --
----------------------------------------------------------------------------------------------------
- circular_buffer_block: circular_buffer
- port map
- (clk_i => clk,
- tstamp_wr_rst_i => general_rst,
- tstamp_wr_adr_i => mem_class_adr,
- tstamp_wr_cyc_i => mem_class_cyc,
- tstamp_wr_dat_i => mem_class_data_wr,
- tstamp_wr_stb_i => mem_class_stb,
- tstamp_wr_we_i => mem_class_we,
- tstamp_wr_ack_p_o => mem_class_ack,
- tstamp_wr_dat_o => mem_class_data_rd,
- gnum_dma_rst_i => general_rst,
- gnum_dma_adr_i => dma_adr,
- gnum_dma_cyc_i => dma_cyc,
- gnum_dma_dat_i => dma_dat_wr,
- gnum_dma_stb_i => dma_stb,
- gnum_dma_we_i => dma_we,
- gnum_dma_ack_o => dma_ack,
- gnum_dma_dat_o => dma_dat_rd,
- gnum_dma_stall_o => dma_stall);
-
-
----------------------------------------------------------------------------------------------------
--- CLOCKS & RESETS MANAGER --
----------------------------------------------------------------------------------------------------
- clks_rsts_mgment: clks_rsts_manager
- generic map
- (nb_of_reg => 68,
- values_for_simulation => values_for_simulation)
- port map
- (acam_refclk_i => acam_refclk_i,
- pll_ld_i => pll_ld_i,
- pll_refmon_i => pll_refmon_i,
- pll_sdo_i => pll_sdo_i,
- pll_status_i => pll_status_i,
- gnum_rst_i => gnum_rst,
- spec_clk_i => spec_clk_i,
- tdc_clk_p_i => tdc_clk_p_i,
- tdc_clk_n_i => tdc_clk_n_i,
- acam_refclk_r_edge_p_o => acam_refclk_r_edge_p,
- internal_rst_o => general_rst,
- pll_cs_o => pll_cs_o,
- pll_dac_sync_o => pll_dac_sync_o,
- pll_sdi_o => pll_sdi_o,
- pll_sclk_o => pll_sclk_o,
- spec_clk_o => spec_clk,
- tdc_clk_o => clk);
-
-
----------------------------------------------------------------------------------------------------
--- LEDs & more --
----------------------------------------------------------------------------------------------------
-
- spec_led_period_counter: free_counter
- port map
- (clk_i => spec_clk,
- counter_en_i => '1',
- rst_i => gnum_rst,
- counter_top_i => spec_led_period,
- counter_is_zero_o => spec_led_period_done,
- counter_o => open);
-
- spec_led_blink_counter: decr_counter
- port map
- (clk_i => spec_clk,
- rst_i => gnum_rst,
- counter_load_i => spec_led_period_done,
- counter_top_i => visible_blink_length,
- counter_is_zero_o => spec_led_blink_done,
- counter_o => open);
-
- tdc_led_blink_counter: decr_counter
- port map
- (clk_i => clk,
- rst_i => general_rst,
- counter_load_i => one_hz_p,
- counter_top_i => visible_blink_length,
- counter_is_zero_o => tdc_led_blink_done,
- counter_o => open);
-
- spec_led: process
- begin
- if gnum_rst ='1' then
- spec_led_red <= '0';
- elsif spec_led_period_done ='1' then
- spec_led_red <= '1';
- elsif spec_led_blink_done ='1' then
- spec_led_red <= '0';
- end if;
- wait until spec_clk ='1';
- end process;
-
- tdc_led: process
- begin
- if general_rst ='1' then
- tdc_led_status <= '0';
- elsif one_hz_p ='1' then
- tdc_led_status <= '1';
- elsif tdc_led_blink_done = '1' then
- tdc_led_status <= '0';
- end if;
- wait until clk ='1';
- end process;
-
- spec_led_period <= c_SPEC_LED_PERIOD_SIM when values_for_simulation else c_SPEC_LED_PERIOD_SYN;
- visible_blink_length <= c_BLINK_LGTH_SIM when values_for_simulation else c_BLINK_LGTH_SYN;
- clk_period <= c_SIM_CLK_PERIOD when values_for_simulation else c_SYN_CLK_PERIOD;
-
- spec_led_green <= pll_ld_i;
-
- -- inputs
- sync_gnum_reset: process
- begin
- gnum_rst_synch <= not(rst_n_a_i);
- gnum_rst <= gnum_rst_synch;
- wait until spec_clk ='1';
- end process;
-
- general_rst_n <= not general_rst;
-
- -- outputs
- process
- begin
- mute_inputs_o <= acam_inputs_en(7);
- term_en_5_o <= acam_inputs_en(4);
- term_en_4_o <= acam_inputs_en(3);
- term_en_3_o <= acam_inputs_en(2);
- term_en_2_o <= acam_inputs_en(1);
- term_en_1_o <= acam_inputs_en(0);
- spec_led_green_o <= spec_led_green;
- spec_led_red_o <= spec_led_red;
- tdc_led_status_o <= tdc_led_status;
- tdc_led_trig5_o <= acam_inputs_en(4) and acam_inputs_en(7);
- tdc_led_trig4_o <= acam_inputs_en(3) and acam_inputs_en(7);
- tdc_led_trig3_o <= acam_inputs_en(2) and acam_inputs_en(7);
- tdc_led_trig2_o <= acam_inputs_en(1) and acam_inputs_en(7);
- tdc_led_trig1_o <= acam_inputs_en(0) and acam_inputs_en(7);
- wait until clk ='1';
- end process;
-
- -- note: all spec_aux signals are active low
- button_with_spec_clk_i: process
- begin
- spec_aux3_o <= spec_aux0_i;
- spec_aux2_o <= spec_aux0_i;
- wait until spec_clk ='1';
- end process;
-
- button_with_tdc_clk_i: process
- begin
- spec_aux4_o <= spec_aux1_i;
- spec_aux5_o <= spec_aux1_i;
- wait until clk ='1';
- end process;
-
-end rtl;
-----------------------------------------------------------------------------------------------------
--- architecture ends
-----------------------------------------------------------------------------------------------------
+--_________________________________________________________________________________________________
+-- |
+-- |TDC core| |
+-- |
+-- CERN,BE/CO-HT |
+--________________________________________________________________________________________________|
+
+---------------------------------------------------------------------------------------------------
+-- |
+-- top_tdc |
+-- |
+---------------------------------------------------------------------------------------------------
+-- File top_tdc.vhd |
+-- |
+-- Description TDC top level |
+-- |
+-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
+-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
+-- Date 06/2012 |
+-- Version v2 |
+-- Depends on |
+-- |
+---------------- |
+-- Last changes |
+-- 05/2011 v1 GP First version |
+-- 06/2012 v2 EG Revamping; Comments added, signals renamed |
+-- removed LEDs from top level |
+-- new gnum core integrated |
+-- carrier 1 wire master added |
+-- mezzanine I2C master added |
+-- mezzanine 1 wire master added |
+-- interrupts generator added |
+-- changed generation of general_rst |
+-- DAC reconfiguration+needed regs added |
+
+----------------------------------------------/!\-------------------------------------------------|
+-- TODO!! |
+-- Data formatting unit, line 341: If a new tstamp has arrived from the ACAM when the roll_over |
+-- has just been increased, there are chances the tstamp belongs to the previous roll-over value. |
+-- This is because the moment the IrFlag is taken into account in the FPGA is different from the |
+-- moment the tstamp has arrived to the ACAM. So if in a timestamp the start_nb from the ACAM is |
+-- close to the upper end (close to 255) and on the moment the timestamp is being treated in the |
+-- FPGA the IrFlag has recently been tripped it means that for the formatting of the tstamp the |
+-- previous value of the roll_over_c should be considered (before the IrFlag tripping). |
+-- Have to calculate the amount of tstamps that could have been accumulated before the rollover |
+-- changes; the current value we put "192" is not well studied for all cases!! |
+-- |
+-- Data formatting unit, lines 300-315: for the case that in line 365: |
+-- un_retrig_from_roll_over - un_retrig_nb_offset + un_acam_start_nb = 0 for the data_formatting |
+-- we should consider the values (offsets and value of roll_over_c just before the arrival of |
+-- the new sec) that characterize the previous second!! |
+-- Commented lines have not been tested at aaaaaall |
+-- |
+---------------------------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE |
+-- ------------------------------------ |
+-- This source file is free software; you can redistribute it and/or modify it under the terms of |
+-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
+-- version 2.1 of the License, or (at your option) any later version. |
+-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
+-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
+-- See the GNU Lesser General Public License for more details. |
+-- You should have received a copy of the GNU Lesser General Public License along with this |
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
+---------------------------------------------------------------------------------------------------
+
+
+
+--
+----------------------------------------------------------------------------------------------------
+-- last changes:
+-- revamping, comments, renamings etc
+--
+-- clks_rsts_mnger modified
+----------------------------------------------------------------------------------------------------
+-- to do:
+----------------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.tdc_core_pkg.all;
+use work.gn4124_core_pkg.all;
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+
+----------------------------------------------------------------------------------------------------
+-- entity declaration for top_tdc
+----------------------------------------------------------------------------------------------------
+entity top_tdc is
+ generic
+ (g_span : integer :=32; -- address span in bus interfaces
+ g_width : integer :=32; -- data width in bus interfaces
+ values_for_simulation : boolean :=FALSE); -- this generic is set to TRUE
+ -- when instantiated in a test-bench
+ port
+ (-- interface with GNUM
+ rst_n_a_i : in std_logic;
+ -- P2L Direction
+ p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
+ p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
+ p2l_data_i : in std_logic_vector(15 downto 0);-- Parallel receive data
+ p2l_dframe_i : in std_logic; -- Receive Frame
+ p2l_valid_i : in std_logic; -- Receive Data Valid
+ p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
+ p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
+ p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
+ rx_error_o : out std_logic; -- Receive Error
+ vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
+ -- L2P Direction
+ l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
+ l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
+ l2p_data_o : out std_logic_vector(15 downto 0);-- Parallel transmit data
+ l2p_dframe_o : out std_logic; -- Transmit Data Frame
+ l2p_valid_o : out std_logic; -- Transmit Data Valid
+ l2p_edb_o : out std_logic; -- Packet termination and discard
+ l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
+ l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
+ p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
+ tx_error_i : in std_logic; -- Transmit Error
+ irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
+ spare_o : out std_logic;
+
+ -- interface signals with PLL circuit on TDC mezzanine
+ acam_refclk_i : in std_logic; -- 31.25 MHz clock that is also received by ACAM
+ pll_ld_i : in std_logic; -- PLL AD9516 interface signals
+ pll_refmon_i : in std_logic; --
+ pll_sdo_i : in std_logic; --
+ pll_status_i : in std_logic; --
+ tdc_clk_p_i : in std_logic; -- 125 MHz differential clock : system clock
+ tdc_clk_n_i : in std_logic; --
+
+ pll_cs_o : out std_logic; -- PLL AD9516 interface signals
+ pll_dac_sync_o : out std_logic; --
+ pll_sdi_o : out std_logic; --
+ pll_sclk_o : out std_logic; --
+ -- interface signals with acam (timing) on TDC mezzanine
+ err_flag_i : in std_logic; -- error flag signal coming from ACAM
+ int_flag_i : in std_logic; -- interrupt flag signal coming from ACAM
+ start_dis_o : out std_logic; -- start disable signal for ACAM
+ start_from_fpga_o : out std_logic; -- start signal for ACAM
+ stop_dis_o : out std_logic; -- stop disable signal for ACAM
+ -- interface signals with acam (data) on TDC mezzanine
+ data_bus_io : inout std_logic_vector(27 downto 0);
+ ef1_i : in std_logic; -- empty flag iFIFO1 signal from ACAM
+ ef2_i : in std_logic; -- empty flag iFIFO2 signal from ACAM
+ lf1_i : in std_logic; -- load flag iFIFO1 signal from ACAM
+ lf2_i : in std_logic; -- load flag iFIFO2 signal from ACAM
+
+ address_o : out std_logic_vector(3 downto 0);
+ cs_n_o : out std_logic; -- chip select for ACAM
+ oe_n_o : out std_logic; -- output enable for ACAM
+ rd_n_o : out std_logic; -- read signal for ACAM
+ wr_n_o : out std_logic; -- write signal for ACAM
+
+ -- other signals on the TDC mezzanine
+ tdc_in_fpga_5_i : in std_logic; -- input 5 for ACAM is also received by FPGA
+ -- all 4 other stop inputs are miss-routed on PCB
+ mute_inputs_o : out std_logic; -- controls all 5 inputs (actual function: ENABLE)
+ tdc_led_status_o : out std_logic; -- amber led on front pannel
+ tdc_led_trig1_o : out std_logic; -- amber leds on front pannel
+ tdc_led_trig2_o : out std_logic; --
+ tdc_led_trig3_o : out std_logic; --
+ tdc_led_trig4_o : out std_logic; --
+ tdc_led_trig5_o : out std_logic; --
+ term_en_1_o : out std_logic; -- enable of 50 Ohm termination inputs
+ term_en_2_o : out std_logic; --
+ term_en_3_o : out std_logic; --
+ term_en_4_o : out std_logic; --
+ term_en_5_o : out std_logic; --
+
+ -- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
+ carrier_one_wire_b : inout std_logic;
+
+ -- Mezzanine system I2C EEPROM
+ sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
+ sys_sda_b : inout std_logic; -- Mezzanine system I2C data (EEPROM)
+
+ -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
+ mezz_one_wire_b : inout std_logic;
+
+ -- other signals on the SPEC carrier
+ spec_aux0_i : in std_logic; -- buttons on spec card
+ spec_aux1_i : in std_logic; --
+ spec_aux2_o : out std_logic; -- red leds on spec PCB
+ spec_aux3_o : out std_logic; --
+ spec_aux4_o : out std_logic; --
+ spec_aux5_o : out std_logic; --
+ spec_led_green_o : out std_logic; -- green led on spec front pannel
+ spec_led_red_o : out std_logic; -- red led on spec front pannel
+ spec_clk_i : in std_logic); -- 20 MHz clock from VCXO on spec card
+
+end top_tdc;
+
+----------------------------------------------------------------------------------------------------
+-- architecture declaration for top_tdc
+----------------------------------------------------------------------------------------------------
+architecture rtl of top_tdc is
+
+
+
+ signal clk, spec_clk, pll_ld : std_logic;
+
+-- LEDs
+
+ signal pulse_delay, window_delay, clk_period : std_logic_vector(g_width-1 downto 0);
+
+ signal gnum_rst : std_logic;
+
+ signal irq_code, core_status : std_logic_vector(g_width-1 downto 0);
+
+ signal acam_ef1, acam_ef2, acam_ef1_meta, acam_ef2_meta : std_logic;
+
+ signal acam_errflag_f_edge_p, acam_errflag_r_edge_p, acam_intflag_f_edge_p, acam_refclk_r_edge_p : std_logic;
+
+ signal acam_tstamp1, acam_tstamp2 : std_logic_vector(g_width-1 downto 0);
+ signal acam_tstamp1_ok_p, acam_tstamp2_ok_p : std_logic;
+
+ signal clk_i_cycles_offset, roll_over_nb, retrig_nb_offset : std_logic_vector(g_width-1 downto 0);
+ signal general_rst, general_rst_n : std_logic;
+ signal one_hz_p : std_logic;
+
+ signal acm_adr : std_logic_vector(7 downto 0);
+ signal acm_cyc, acm_stb, acm_we, acm_ack : std_logic;
+ signal acm_dat_r, acm_dat_w : std_logic_vector(g_width-1 downto 0);
+
+ signal dma_irq : std_logic_vector(1 downto 0);
+ signal irq_to_gn4124 : std_logic;
+
+
+ signal wbm_csr_sel : std_logic_vector(3 downto 0);
+ signal wbm_csr_stb, wbm_csr_we : std_logic;
+
+
+ signal wbm_csr_dat_wr, wbm_csr_dat_rd, dma_dat_rd, dma_dat_wr : std_logic_vector(31 downto 0);
+
+
+ signal dma_stb, dma_cyc, dma_we, dma_ack, dma_stall : std_logic;
+ signal dma_adr : std_logic_vector(31 downto 0);
+ signal dma_sel : std_logic_vector(3 downto 0);
+
+
+ signal mem_class_adr : std_logic_vector(7 downto 0);
+ signal mem_class_stb, mem_class_cyc, mem_class_we, mem_class_ack : std_logic;
+ signal mem_class_data_wr, mem_class_data_rd : std_logic_vector(4*g_width-1 downto 0);
+
+ signal wb_csr_adr_decoded : std_logic_vector(g_span-1 downto 0);
+ signal wb_csr_dat_wr_decoded : std_logic_vector(g_width-1 downto 0);
+ signal wb_csr_stb_decoded : std_logic;
+ signal wb_csr_we_decoded : std_logic;
+
+
+ signal activate_acq_p, deactivate_acq_p, load_acam_config, read_acam_config : std_logic;
+ signal read_acam_status, read_ififo1, read_ififo2, read_start01, reset_acam : std_logic;
+ signal load_utc, clear_dacapo_counter, roll_over_incr_recent : std_logic;
+
+ signal starting_utc : std_logic_vector(g_width-1 downto 0);
+ signal acam_inputs_en, irq_tstamp_threshold, irq_time_threshold : std_logic_vector(g_width-1 downto 0);
+ signal acam_config : config_vector;
+ signal acam_config_rdbk : config_vector;
+ signal acam_status, acam_ififo1, acam_ififo2, acam_start01 : std_logic_vector(g_width-1 downto 0);
+
+ signal local_utc, wr_index : std_logic_vector(g_width-1 downto 0);
+ signal irq_sources : std_logic_vector(g_width-1 downto 0);
+
+
+ signal wb_csr_cyc_decoded, wb_all_csr_ack, wb_all_csr_stall : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
+ signal wb_all_csr_dat_rd : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0);
+
+ signal wb_csr_sel_decoded : std_logic_vector (3 downto 0);
+
+ signal wbm_csr_adr : std_logic_vector (31 downto 0);
+ signal wbm_csr_cyc, wbm_csr_ack_decoded, wbm_stall : std_logic;
+
+ -- Mezzanine 1-wire
+ signal mezz_owr_pwren : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
+ signal mezz_owr_en : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
+ signal mezz_owr_i : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
+
+ -- Carrier 1-wire
+ signal carrier_owr_en : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
+ signal carrier_owr_i : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
+
+ -- Mezzanine system I2C for EEPROM
+ signal sys_scl_in, sys_scl_out, sys_scl_oe_n : std_logic;
+ signal sys_sda_in, sys_sda_out, sys_sda_oe_n : std_logic;
+
+ signal tstamp_wr_p, irq_tstamp_p, irq_time_p, send_dac_word_p : std_logic;
+ signal pll_dac_word : std_logic_vector(23 downto 0);
+
+-- <acam_status_i<31:0>> is never used.
+-- <adr_i<7:4>> is never used.
+-- <dat_i<31:28>> is never used.
+-- <tstamp_wr_dat_i<127:0>> is never used.
+-- <acam_tstamp1_i<30:30>> is never used.
+-- <acam_tstamp1_i<28:28>> is never used.
+-- <acam_tstamp2_i<31:31>> is never used.
+-- <acam_tstamp2_i<29:29>> is never used.
+-- <gnum_dma_adr_i<31:10>> is never used.
+-- <wbm_adr_i<31:18> never used
+-- gnum_csr_adr_i<31:8> is never used
+
+----------------------------------------------------------------------------------------------------
+-- architecture begins
+----------------------------------------------------------------------------------------------------
+begin
+
+ general_rst_n <= not (general_rst);
+---------------------------------------------------------------------------------------------------
+-- WISHBONE CSR DECODER --
+---------------------------------------------------------------------------------------------------
+-- CSR wishbone address decoder
+-- 0x00000 -> DMA configuration
+-- 0x20000 -> TDC core & ACAM
+-- 0x40000 -> Carrier 1-wire master (Unidue ID & Thermometer)
+-- 0x60000 -> Mezzanine I2C master (EEPROM)
+-- 0x80000 -> Mezzanine 1-wire master (Unidue ID & Thermometer)
+-- 0xA0000 -> Interrupt controller
+
+ address_decoder:wb_addr_decoder
+ generic map
+ (g_WINDOW_SIZE => c_BAR0_APERTURE, -- note: c_BAR0_APERTURE = 18
+ g_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB) -- note: c_CSR_WB_SLAVES_NB = 5
+ port map
+ (clk_i => clk,
+ rst_n_i => rst_n_a_i,
+ -- WISHBONE master interface
+ wbm_adr_i => wbm_csr_adr,
+ wbm_dat_i => wbm_csr_dat_wr,
+ wbm_sel_i => wbm_csr_sel,
+ wbm_stb_i => wbm_csr_stb,
+ wbm_we_i => wbm_csr_we,
+ wbm_cyc_i => wbm_csr_cyc,
+ wbm_ack_o => wbm_csr_ack_decoded,
+ wbm_dat_o => wbm_csr_dat_rd,
+ wbm_stall_o => wbm_stall,
+ -- WISHBONE slaves interface
+ wb_dat_i => wb_all_csr_dat_rd,
+ wb_ack_i => wb_all_csr_ack,
+ wb_stall_i => wb_all_csr_stall,
+ wb_cyc_o => wb_csr_cyc_decoded,
+ wb_stb_o => wb_csr_stb_decoded,
+ wb_we_o => wb_csr_we_decoded,
+ wb_sel_o => wb_csr_sel_decoded, -- Byte select???
+ wb_adr_o => wb_csr_adr_decoded,
+ wb_dat_o => wb_csr_dat_wr_decoded);
+
+
+---------------------------------------------------------------------------------------------------
+-- INTERRUPTS CONTROLLER --
+---------------------------------------------------------------------------------------------------
+ cmp_irq_controller : irq_controller
+ port map
+ (clk_i => clk,
+ rst_n_i => general_rst_n,
+ irq_src_p_i => irq_sources,
+ irq_p_o => irq_to_gn4124,
+ wb_adr_i => wb_csr_adr_decoded(1 downto 0),
+ wb_dat_i => wb_csr_dat_wr_decoded,
+ wb_dat_o => wb_all_csr_dat_rd(c_CSR_WB_IRQ_CTRL * 32 + 31 downto c_CSR_WB_IRQ_CTRL * 32),
+ wb_cyc_i => wb_csr_cyc_decoded(c_CSR_WB_IRQ_CTRL),
+ wb_sel_i => wb_csr_sel_decoded,
+ wb_stb_i => wb_csr_stb_decoded,
+ wb_we_i => wb_csr_we_decoded,
+ wb_ack_o => wb_all_csr_ack(c_CSR_WB_IRQ_CTRL));
+
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- IRQ sources
+ irq_sources(1 downto 0) <= dma_irq;
+ irq_sources(2) <= irq_tstamp_p;
+ irq_sources(3) <= irq_time_p;
+ irq_sources(31 downto 4) <= (others => '0');
+
+ -- Classic slave supporting single pipelined accesses, stall isn't used
+ wb_all_csr_stall(c_CSR_WB_IRQ_CTRL) <= '0';
+
+
+---------------------------------------------------------------------------------------------------
+-- CARRIER 1-wire MASTER DS18B20 (thermometer + unique ID) --
+---------------------------------------------------------------------------------------------------
+-- Note: c_CSR_WB_CARRIER_ONE_WIRE = 2
+ carrier_OneWire : wb_onewire_master
+ generic map
+ (g_num_ports => 1,
+ g_ow_btp_normal => "5.0",
+ g_ow_btp_overdrive => "1.0")
+ port map
+ (clk_sys_i => clk,
+ rst_n_i => general_rst_n,
+ wb_adr_i => wb_csr_adr_decoded(2 downto 0),
+ wb_dat_i => wb_csr_dat_wr_decoded,
+ wb_cyc_i => wb_csr_cyc_decoded(c_CSR_WB_CARRIER_ONE_WIRE),
+ wb_sel_i => wb_csr_sel_decoded,
+ wb_stb_i => wb_csr_stb_decoded,
+ wb_we_i => wb_csr_we_decoded,
+
+ wb_dat_o => wb_all_csr_dat_rd(c_CSR_WB_CARRIER_ONE_WIRE * 32 + 31 downto 32 * c_CSR_WB_CARRIER_ONE_WIRE),
+ wb_ack_o => wb_all_csr_ack(c_CSR_WB_CARRIER_ONE_WIRE),
+ wb_int_o => open,
+ owr_pwren_o => open,
+ owr_en_o => carrier_owr_en,
+ owr_i => carrier_owr_i);
+
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ carrier_one_wire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
+ carrier_owr_i(0) <= carrier_one_wire_b;
+
+ -- Classic slave supporting single pipelined accesses, stall isn't used
+ wb_all_csr_stall(c_CSR_WB_CARRIER_ONE_WIRE) <= '0';
+
+
+---------------------------------------------------------------------------------------------------
+-- Mezzanine System managment I2C Master, EEPROM access --
+---------------------------------------------------------------------------------------------------
+-- Note: c_CSR_WB_FMC_SYS_I2C = 3
+ mezzanine_I2C_master_EEPROM : wb_i2c_master
+ port map
+ (clk_sys_i => clk,
+ rst_n_i => general_rst_n,
+ wb_adr_i => wb_csr_adr_decoded(4 downto 0),
+ wb_dat_i => wb_csr_dat_wr_decoded,
+ wb_we_i => wb_csr_we_decoded,
+ wb_stb_i => wb_csr_stb_decoded,
+ wb_sel_i => wb_csr_sel_decoded,
+ wb_cyc_i => wb_csr_cyc_decoded(c_CSR_WB_FMC_SYS_I2C),
+ wb_ack_o => wb_all_csr_ack(c_CSR_WB_FMC_SYS_I2C),
+ wb_int_o => open,
+ wb_dat_o => wb_all_csr_dat_rd(c_CSR_WB_FMC_SYS_I2C * 32 + 31 downto 32 * c_CSR_WB_FMC_SYS_I2C),
+
+ scl_pad_i => sys_scl_in,
+ scl_pad_o => sys_scl_out,
+ scl_padoen_o => sys_scl_oe_n,
+ sda_pad_i => sys_sda_in,
+ sda_pad_o => sys_sda_out,
+ sda_padoen_o => sys_sda_oe_n);
+
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- Classic slave supporting single pipelined accesses, stall isn't used
+ wb_all_csr_stall(c_CSR_WB_FMC_SYS_I2C) <= '0';
+
+ -- Tri-state buffer for SDA and SCL
+ sys_scl_b <= sys_scl_out when sys_scl_oe_n = '0' else 'Z';
+ sys_scl_in <= sys_scl_b;
+
+ sys_sda_b <= sys_sda_out when sys_sda_oe_n = '0' else 'Z';
+ sys_sda_in <= sys_sda_b;
+
+---------------------------------------------------------------------------------------------------
+-- Mezzanine 1-wire MASTER DS18B20 (thermometer + unique ID) --
+---------------------------------------------------------------------------------------------------
+--Note: c_CSR_WB_FMC_ONE_WIRE = 4
+ cmp_fmc_onewire : wb_onewire_master
+ generic map
+ (g_num_ports => 1,
+ g_ow_btp_normal => "5.0",
+ g_ow_btp_overdrive => "1.0")
+ port map
+ (clk_sys_i => clk,
+ rst_n_i => general_rst_n,
+ wb_adr_i => wb_csr_adr_decoded(2 downto 0),
+ wb_dat_i => wb_csr_dat_wr_decoded,
+ wb_we_i => wb_csr_we_decoded,
+ wb_stb_i => wb_csr_stb_decoded,
+ wb_sel_i => wb_csr_sel_decoded,
+ wb_cyc_i => wb_csr_cyc_decoded(c_CSR_WB_FMC_ONE_WIRE),
+ wb_ack_o => wb_all_csr_ack(c_CSR_WB_FMC_ONE_WIRE),
+ wb_dat_o => wb_all_csr_dat_rd(c_CSR_WB_FMC_ONE_WIRE * 32 + 31 downto 32 * c_CSR_WB_FMC_ONE_WIRE),
+ wb_int_o => open,
+ owr_pwren_o => mezz_owr_pwren,
+ owr_en_o => mezz_owr_en,
+ owr_i => mezz_owr_i);
+
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ mezz_one_wire_b <= '0' when mezz_owr_en(0) = '1' else 'Z';
+ mezz_owr_i(0) <= mezz_one_wire_b;
+
+ -- Classic slave supporting single pipelined accesses, stall isn't used
+ wb_all_csr_stall(c_CSR_WB_FMC_ONE_WIRE) <= '0';
+
+
+---------------------------------------------------------------------------------------------------
+-- GNUM CORE --
+---------------------------------------------------------------------------------------------------
+-- Note: c_CSR_WB_DMA_CONFIG = 0
+-- <dma_reg_adr_i<31:4>> is never used.
+ gnum_interface_block: gn4124_core --cmp_gn4124_core
+ port map
+ (rst_n_a_i => rst_n_a_i,
+ status_o => open,
+ p2l_clk_p_i => p2l_clk_p_i,
+ p2l_clk_n_i => p2l_clk_n_i,
+ p2l_data_i => p2l_data_i,
+ p2l_dframe_i => p2l_dframe_i,
+ p2l_valid_i => p2l_valid_i,
+ p2l_rdy_o => p2l_rdy_o,
+ p_wr_req_i => p_wr_req_i,
+ p_wr_rdy_o => p_wr_rdy_o,
+ rx_error_o => rx_error_o,
+ vc_rdy_i => vc_rdy_i,
+ l2p_clk_p_o => l2p_clk_p_o,
+ l2p_clk_n_o => l2p_clk_n_o,
+ l2p_data_o => l2p_data_o ,
+ l2p_dframe_o => l2p_dframe_o,
+ l2p_valid_o => l2p_valid_o,
+ l2p_edb_o => l2p_edb_o,
+ l2p_rdy_i => l2p_rdy_i,
+ l_wr_rdy_i => l_wr_rdy_i,
+ p_rd_d_rdy_i => p_rd_d_rdy_i,
+ tx_error_i => tx_error_i,
+ irq_p_o => irq_p_o,
+ dma_irq_o => dma_irq,
+ irq_p_i => irq_to_gn4124,
+ -----CSR all registers classic master-----
+ csr_clk_i => clk,
+ csr_adr_o => wbm_csr_adr,
+ csr_cyc_o => wbm_csr_cyc,
+ csr_dat_o => wbm_csr_dat_wr,
+ csr_sel_o => wbm_csr_sel,
+ csr_stb_o => wbm_csr_stb,
+ csr_stall_i => wbm_stall, --<<--
+ csr_we_o => wbm_csr_we,
+ csr_ack_i => wbm_csr_ack_decoded,
+ csr_dat_i => wbm_csr_dat_rd,
+ ------------DMA pipelined master----------
+ dma_clk_i => clk,
+ dma_adr_o => dma_adr,
+ dma_cyc_o => dma_cyc,
+ dma_dat_o => dma_dat_wr,
+ dma_sel_o => dma_sel,
+ dma_stb_o => dma_stb,
+ dma_we_o => dma_we,
+ dma_ack_i => dma_ack,
+ dma_dat_i => dma_dat_rd,
+ dma_stall_i => dma_stall,
+ -------DMA registers classic slave--------
+ dma_reg_clk_i => clk,
+ dma_reg_adr_i => wb_csr_adr_decoded,
+ dma_reg_dat_i => wb_csr_dat_wr_decoded,
+ dma_reg_sel_i => wb_csr_sel_decoded,
+ dma_reg_stb_i => wb_csr_stb_decoded,
+ dma_reg_we_i => wb_csr_we_decoded,
+ dma_reg_cyc_i => wb_csr_cyc_decoded(c_CSR_WB_DMA_CONFIG),
+ dma_reg_dat_o => wb_all_csr_dat_rd(c_CSR_WB_DMA_CONFIG * 32 + 31 downto 32 * c_CSR_WB_DMA_CONFIG),
+ dma_reg_ack_o => wb_all_csr_ack(c_CSR_WB_DMA_CONFIG),
+ dma_reg_stall_o => wb_all_csr_stall(c_CSR_WB_DMA_CONFIG));
+
+
+---------------------------------------------------------------------------------------------------
+-- TDC REGISTERS CONTROLLER --
+---------------------------------------------------------------------------------------------------
+-- Note: c_CSR_WB_TDC_CORE = 1
+ reg_control_block: reg_ctrl
+ generic map
+ (g_span => g_span,
+ g_width => g_width)
+ port map
+ (clk_i => clk,
+ rst_i => general_rst,
+ gnum_csr_adr_i => wb_csr_adr_decoded,
+ gnum_csr_dat_i => wb_csr_dat_wr_decoded,
+ gnum_csr_stb_i => wb_csr_stb_decoded,
+ gnum_csr_we_i => wb_csr_we_decoded,
+ gnum_csr_cyc_i => wb_csr_cyc_decoded(c_CSR_WB_TDC_CORE),
+ gnum_csr_ack_o => wb_all_csr_ack(c_CSR_WB_TDC_CORE),
+ gnum_csr_dat_o => wb_all_csr_dat_rd(c_CSR_WB_TDC_CORE * 32 + 31 downto 32 * c_CSR_WB_TDC_CORE),
+
+ activate_acq_p_o => activate_acq_p,
+ deactivate_acq_p_o => deactivate_acq_p,
+ acam_wr_config_p_o => load_acam_config,
+ acam_rdbk_config_p_o => read_acam_config,
+ acam_rdbk_status_p_o => read_acam_status,
+ acam_rdbk_ififo1_p_o => read_ififo1,
+ acam_rdbk_ififo2_p_o => read_ififo2,
+ acam_rdbk_start01_p_o => read_start01,
+ acam_rst_p_o => reset_acam,
+ load_utc_p_o => load_utc,
+ dacapo_c_rst_p_o => clear_dacapo_counter,
+ acam_config_rdbk_i => acam_config_rdbk,
+ acam_status_i => acam_status,
+ acam_ififo1_i => acam_ififo1,
+ acam_ififo2_i => acam_ififo2,
+ acam_start01_i => acam_start01,
+ local_utc_i => local_utc,
+ irq_code_i => irq_code,
+ core_status_i => core_status,
+ wr_index_i => wr_index,
+ acam_config_o => acam_config,
+ starting_utc_o => starting_utc,
+ acam_inputs_en_o => acam_inputs_en,
+ start_phase_o => window_delay,
+ irq_tstamp_threshold_o=> irq_tstamp_threshold,
+ irq_time_threshold_o => irq_time_threshold,
+ send_dac_word_p_o => send_dac_word_p,
+ dac_word_o => pll_dac_word,
+ one_hz_phase_o => pulse_delay);
+
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ wb_all_csr_stall(c_CSR_WB_TDC_CORE) <= '0';
+
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ term_enable_regs: process (clk)
+ begin
+ if rising_edge (clk) then
+ if general_rst = '1' then
+ mute_inputs_o <= '0';
+ term_en_5_o <= '0';
+ term_en_4_o <= '0';
+ term_en_3_o <= '0';
+ term_en_2_o <= '0';
+ term_en_1_o <= '0';
+ else
+ mute_inputs_o <= acam_inputs_en(7);
+ term_en_5_o <= acam_inputs_en(4);
+ term_en_4_o <= acam_inputs_en(3);
+ term_en_3_o <= acam_inputs_en(2);
+ term_en_2_o <= acam_inputs_en(1);
+ term_en_1_o <= acam_inputs_en(0);
+ end if;
+ end if;
+ end process;
+
+---------------------------------------------------------------------------------------------------
+-- ONE HZ GENERATOR --
+---------------------------------------------------------------------------------------------------
+ one_second_block: one_hz_gen
+ generic map
+ (g_width => g_width)
+ port map
+ (acam_refclk_r_edge_p_i => acam_refclk_r_edge_p,
+ clk_i => clk,
+ clk_period_i => clk_period,
+ load_utc_p_i => load_utc,
+ pulse_delay_i => pulse_delay,
+ rst_i => general_rst,
+ starting_utc_i => starting_utc,
+ local_utc_o => local_utc,
+ one_hz_p_o => one_hz_p);
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ clk_period <= c_SIM_CLK_PERIOD when values_for_simulation else c_SYN_CLK_PERIOD;
+
+---------------------------------------------------------------------------------------------------
+-- ACAM TIMECONTROL INTERFACE --
+---------------------------------------------------------------------------------------------------
+ acam_timing_block: acam_timecontrol_interface
+ port map(
+ err_flag_i => err_flag_i,
+ int_flag_i => int_flag_i,
+ start_dis_o => start_dis_o,
+ start_from_fpga_o => start_from_fpga_o,
+ stop_dis_o => stop_dis_o,
+ acam_refclk_r_edge_p_i => acam_refclk_r_edge_p,
+ clk_i => clk,
+ activate_acq_p_i => activate_acq_p,
+ rst_i => general_rst,
+ window_delay_i => window_delay,
+ acam_errflag_f_edge_p_o => acam_errflag_f_edge_p,
+ acam_errflag_r_edge_p_o => acam_errflag_r_edge_p,
+ acam_intflag_f_edge_p_o => acam_intflag_f_edge_p);
+
+
+---------------------------------------------------------------------------------------------------
+-- ACAM DATABUS INTERFACE --
+---------------------------------------------------------------------------------------------------
+ acam_data_block: acam_databus_interface
+ port map
+ (ef1_i => ef1_i,
+ ef2_i => ef2_i,
+ lf1_i => lf1_i,
+ lf2_i => lf2_i,
+ data_bus_io => data_bus_io,
+ adr_o => address_o,
+ cs_n_o => cs_n_o,
+ oe_n_o => oe_n_o,
+ rd_n_o => rd_n_o,
+ wr_n_o => wr_n_o,
+ ef1_o => acam_ef1,
+ ef1_synch1_o => acam_ef1_meta,
+ ef2_o => acam_ef2,
+ ef2_synch1_o => acam_ef2_meta,
+ clk_i => clk,
+ rst_i => general_rst,
+ adr_i => acm_adr,
+ cyc_i => acm_cyc,
+ dat_i => acm_dat_w,
+ stb_i => acm_stb,
+ we_i => acm_we,
+ ack_o => acm_ack,
+ dat_o => acm_dat_r);
+
+
+---------------------------------------------------------------------------------------------------
+-- ACAM START RETRIGGER CONTROLLER --
+---------------------------------------------------------------------------------------------------
+ start_retrigger_block: start_retrig_ctrl
+ generic map
+ (g_width => g_width)
+ port map
+ (acam_intflag_f_edge_p_i => acam_intflag_f_edge_p,
+ clk_i => clk,
+ one_hz_p_i => one_hz_p,
+ rst_i => general_rst,
+ roll_over_incr_recent_o => roll_over_incr_recent,
+ clk_i_cycles_offset_o => clk_i_cycles_offset,
+ roll_over_nb_o => roll_over_nb,
+ retrig_nb_offset_o => retrig_nb_offset);
+
+
+---------------------------------------------------------------------------------------------------
+-- DATA ENGINE --
+---------------------------------------------------------------------------------------------------
+ data_engine_block: data_engine
+ port map
+ (acam_ack_i => acm_ack,
+ acam_dat_i => acm_dat_r,
+ acam_adr_o => acm_adr,
+ acam_cyc_o => acm_cyc,
+ acam_dat_o => acm_dat_w,
+ acam_stb_o => acm_stb,
+ acam_we_o => acm_we,
+ clk_i => clk,
+ rst_i => general_rst,
+ acam_ef1_i => acam_ef1,
+ acam_ef1_synch1_i => acam_ef1_meta,
+ acam_ef2_i => acam_ef2,
+ acam_ef2_synch1_i => acam_ef2_meta,
+ activate_acq_p_i => activate_acq_p,
+ deactivate_acq_p_i => deactivate_acq_p,
+ acam_wr_config_p_i => load_acam_config,
+ acam_rdbk_config_p_i => read_acam_config,
+ acam_rdbk_status_p_i => read_acam_status,
+ acam_rdbk_ififo1_p_i => read_ififo1,
+ acam_rdbk_ififo2_p_i => read_ififo2,
+ acam_rdbk_start01_p_i => read_start01,
+ acam_rst_p_i => reset_acam,
+ acam_config_i => acam_config,
+ acam_config_rdbk_o => acam_config_rdbk,
+ acam_status_o => acam_status,
+ acam_ififo1_o => acam_ififo1,
+ acam_ififo2_o => acam_ififo2,
+ acam_start01_o => acam_start01,
+ acam_tstamp1_o => acam_tstamp1,
+ acam_tstamp1_ok_p_o => acam_tstamp1_ok_p,
+ acam_tstamp2_o => acam_tstamp2,
+ acam_tstamp2_ok_p_o => acam_tstamp2_ok_p);
+
+
+---------------------------------------------------------------------------------------------------
+-- DATA FORMATTING --
+---------------------------------------------------------------------------------------------------
+ data_formatting_block: data_formatting
+ port map
+ (clk_i => clk,
+ rst_i => general_rst,
+ tstamp_wr_wb_ack_i => mem_class_ack,
+ tstamp_wr_dat_i => mem_class_data_rd,
+ tstamp_wr_wb_adr_o => mem_class_adr,
+ tstamp_wr_wb_cyc_o => mem_class_cyc,
+ tstamp_wr_dat_o => mem_class_data_wr,
+ tstamp_wr_wb_stb_o => mem_class_stb,
+ tstamp_wr_wb_we_o => mem_class_we,
+ acam_tstamp1_i => acam_tstamp1,
+ acam_tstamp1_ok_p_i => acam_tstamp1_ok_p,
+ acam_tstamp2_i => acam_tstamp2,
+ acam_tstamp2_ok_p_i => acam_tstamp2_ok_p,
+ dacapo_c_rst_p_i => clear_dacapo_counter,
+ roll_over_incr_recent_i => roll_over_incr_recent,
+ clk_i_cycles_offset_i => clk_i_cycles_offset,
+ roll_over_nb_i => roll_over_nb,
+ retrig_nb_offset_i => retrig_nb_offset,
+ one_hz_p_i => one_hz_p,
+ local_utc_i => local_utc,
+ tstamp_wr_p_o => tstamp_wr_p,
+ wr_index_o => wr_index);
+
+
+---------------------------------------------------------------------------------------------------
+-- INTERRUPTS GENERATOR --
+---------------------------------------------------------------------------------------------------
+ interrupts_generator: irq_generator
+ generic map
+ (g_width => 32)
+ port map
+ (clk_i => clk,
+ rst_i => general_rst,
+ irq_tstamp_threshold_i => irq_tstamp_threshold,
+ irq_time_threshold_i => irq_time_threshold,
+ activate_acq_p_i => activate_acq_p,
+ deactivate_acq_p_i => deactivate_acq_p,
+ tstamp_wr_p_i => tstamp_wr_p,
+ one_hz_p_i => one_hz_p,
+ irq_tstamp_p_o => irq_tstamp_p,
+ irq_time_p_o => irq_time_p);
+
+
+---------------------------------------------------------------------------------------------------
+-- CIRCULAR BUFFER --
+---------------------------------------------------------------------------------------------------
+ circular_buffer_block: circular_buffer
+ port map
+ (clk_i => clk,
+ tstamp_wr_rst_i => general_rst,
+ tstamp_wr_adr_i => mem_class_adr,
+ tstamp_wr_cyc_i => mem_class_cyc,
+ tstamp_wr_dat_i => mem_class_data_wr,
+ tstamp_wr_stb_i => mem_class_stb,
+ tstamp_wr_we_i => mem_class_we,
+ tstamp_wr_ack_p_o => mem_class_ack,
+ tstamp_wr_dat_o => mem_class_data_rd,
+ gnum_dma_rst_i => general_rst,
+ gnum_dma_adr_i => dma_adr,
+ gnum_dma_cyc_i => dma_cyc,
+ gnum_dma_dat_i => dma_dat_wr,
+ gnum_dma_stb_i => dma_stb,
+ gnum_dma_we_i => dma_we,
+ gnum_dma_ack_o => dma_ack,
+ gnum_dma_dat_o => dma_dat_rd,
+ gnum_dma_stall_o => dma_stall);
+
+
+---------------------------------------------------------------------------------------------------
+-- CLOCKS & RESETS MANAGER --
+---------------------------------------------------------------------------------------------------
+ clks_rsts_mgment: clks_rsts_manager
+ generic map
+ (nb_of_reg => 68)
+ port map
+ (spec_clk_i => spec_clk_i,
+ acam_refclk_i => acam_refclk_i,
+ tdc_clk_p_i => tdc_clk_p_i,
+ tdc_clk_n_i => tdc_clk_n_i,
+ rst_n_a_i => rst_n_a_i,
+ pll_ld_i => pll_ld_i,
+ pll_refmon_i => pll_refmon_i,
+ pll_sdo_i => pll_sdo_i,
+ pll_status_i => pll_status_i,
+ send_dac_word_p_i => send_dac_word_p,
+ dac_word_i => pll_dac_word,
+ acam_refclk_r_edge_p_o => acam_refclk_r_edge_p,
+ internal_rst_o => general_rst,
+ pll_cs_o => pll_cs_o,
+ pll_dac_sync_o => pll_dac_sync_o,
+ pll_sdi_o => pll_sdi_o,
+ pll_sclk_o => pll_sclk_o,
+ spec_clk_o => spec_clk,
+ tdc_clk_o => clk,
+ gnum_rst_o => gnum_rst,
+ pll_ld_o => pll_ld);
+
+
+---------------------------------------------------------------------------------------------------
+-- LEDs & BUTTONS --
+---------------------------------------------------------------------------------------------------
+ leds_and_buttons: leds_manager
+ generic map
+ (g_width => 32,
+ values_for_simulation => values_for_simulation)
+ port map
+ (clk_20mhz_i => spec_clk,
+ clk_125mhz_i => clk,
+ gnum_rst_i => gnum_rst,
+ internal_rst_i => general_rst,
+ pll_ld_i => pll_ld,
+ spec_aux_butt_1_i => spec_aux0_i,
+ spec_aux_butt_2_i => spec_aux1_i,
+ one_hz_p_i => one_hz_p,
+ acam_inputs_en_i => acam_inputs_en,
+ tdc_led_status_o => tdc_led_status_o,
+ tdc_led_trig1_o => tdc_led_trig1_o,
+ tdc_led_trig2_o => tdc_led_trig2_o,
+ tdc_led_trig3_o => tdc_led_trig3_o,
+ tdc_led_trig4_o => tdc_led_trig4_o,
+ tdc_led_trig5_o => tdc_led_trig5_o,
+ spec_led_green_o => spec_led_green_o,
+ spec_led_red_o => spec_led_red_o,
+ spec_aux_led_1_o => spec_aux2_o,
+ spec_aux_led_2_o => spec_aux3_o,
+ spec_aux_led_3_o => spec_aux4_o,
+ spec_aux_led_4_o => spec_aux5_o);
+
+
+end rtl;
+----------------------------------------------------------------------------------------------------
+-- architecture ends
+----------------------------------------------------------------------------------------------------
\ No newline at end of file
--
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