diff --git a/hdl/ip_cores/VMEcore/VME64xCore_Top.vhd b/hdl/ip_cores/VMEcore/VME64xCore_Top.vhd
index 569e5b54243861dbfe2ac9ab250a99d3e66a4b14..1912dc0c06fec35f070fb6f4f10a180a69a9b4bb 100644
--- a/hdl/ip_cores/VMEcore/VME64xCore_Top.vhd
+++ b/hdl/ip_cores/VMEcore/VME64xCore_Top.vhd
@@ -430,14 +430,15 @@ begin
--------------------------------------------------------------------------------
-- Interrupter
Inst_VME_IRQ_Controller : VME_IRQ_Controller
+ generic map (
+ g_retry_timeout => 62500 -- 1ms timeout
+ )
port map(
clk_i => clk_i,
reset_n_i => s_reset_IRQ, -- asserted when low
VME_IACKIN_n_i => VME_IACKIN_n_oversampled,
VME_AS_n_i => VME_AS_n_oversampled,
- VME_AS1_n_i => VME_AS_n_i,
VME_DS_n_i => VME_DS_n_oversampled,
- VME_LWORD_n_i => VME_LWORD_n_i,
VME_ADDR_123_i => VME_ADDR_i(3 downto 1),
INT_Level_i => s_INT_Level,
INT_Vector_i => s_INT_Vector ,
diff --git a/hdl/ip_cores/VMEcore/VME_IRQ_Controller.vhd b/hdl/ip_cores/VMEcore/VME_IRQ_Controller.vhd
index 12dd4d113c008a0d5ea437766821f29722f26eff..594cb130b5567894e7a9d7fd69986830eb4d1e59 100644
--- a/hdl/ip_cores/VMEcore/VME_IRQ_Controller.vhd
+++ b/hdl/ip_cores/VMEcore/VME_IRQ_Controller.vhd
@@ -123,9 +123,9 @@ entity VME_IRQ_Controller is
reset_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_AS_n_i : in std_logic;
- VME_AS1_n_i : in std_logic; -- this is the AS* not triple sampled
+ --VME_AS1_n_i : in std_logic; -- this is the AS* not triple sampled
VME_DS_n_i : in std_logic_vector (1 downto 0);
- VME_LWORD_n_i : in std_logic;
+ --VME_LWORD_n_i : in std_logic;
VME_ADDR_123_i : in std_logic_vector (2 downto 0);
INT_Level_i : in std_logic_vector (7 downto 0);
INT_Vector_i : in std_logic_vector (7 downto 0);
@@ -141,372 +141,188 @@ end VME_IRQ_Controller;
-- Architecture declaration
--===========================================================================
architecture Behavioral of VME_IRQ_Controller is
+
+ function f_select_irq_line (level : std_logic_vector) return std_logic_vector is
+ begin
+ case level(7 downto 0) is
+ when x"01" => return "1111110";
+ when x"02" => return "1111101";
+ when x"03" => return "1111011";
+ when x"04" => return "1110111";
+ when x"05" => return "1101111";
+ when x"06" => return "1011111";
+ when x"07" => return "0111111";
+ when others => return "1111111";
+ end case;
+ end f_select_irq_Line;
+
--input signals
-- signal s_INT_Req_sample : std_logic;
- signal int_trigger_p : std_logic;
- signal retry_count : unsigned(23 downto 0);
- type t_retry_state is (R_IDLE, R_IRQ, R_WAIT_RETRY);
- signal retry_state : t_retry_state;
---output signals
- signal s_DTACK_OE_o : std_logic;
- signal s_enable : std_logic;
- signal s_IRQ : std_logic_vector(6 downto 0);
- signal s_Data : std_logic_vector(31 downto 0);
---
- signal s_AS_FallingEdge : std_logic;
- signal s_AS_RisingEdge : std_logic;
- type t_MainFSM is (IDLE, IRQ, WAIT_AS, WAIT_DS, CHECK, DATA_OUT, DTACK, IACKOUT1, IACKOUT2);
- signal s_currs, s_nexts : t_MainFSM;
- signal s_ack_int : std_logic;
- signal s_VME_ADDR_123_latched : std_logic_vector(2 downto 0);
- signal s_VME_DS_latched : std_logic_vector(1 downto 0);
- signal s_ADDRmatch : std_logic;
- signal s_FSM_IRQ : t_FSM_IRQ;
+-- signal int_trigger_p : std_logic;
+-- signal retry_count : unsigned(23 downto 0);
+-- type t_retry_state is (R_IDLE, R_IRQ, R_WAIT_RETRY);
+ type t_retry_state is (WAIT_IRQ, WAIT_RETRY);
+ type t_main_state is (IDLE, IRQ, WAIT_AS, WAIT_DS, CHECK, DATA_OUT, DTACK, IACKOUT1, IACKOUT2, SCHEDULE_IRQ);
+ signal as_n_d0 : std_logic;
+ signal as_rising_p, as_falling_p : std_logic;
+ signal vme_addr_latched : std_logic_vector(2 downto 0);
+ signal state : t_main_state;
+ signal retry_state : t_retry_state;
+ signal retry_count : unsigned(23 downto 0);
+ signal retry_mask : std_logic;
+
--===========================================================================
-- Architecture begin
--===========================================================================
begin
--- Input sampling and edge detection
- ASrisingEdge : RisEdgeDetection
- port map (
- sig_i => VME_AS_n_i,
- clk_i => clk_i,
- RisEdge_o => s_AS_RisingEdge
- );
-
- ASfallingEdge : FallingEdgeDetection
- port map (
- sig_i => VME_AS_n_i,
- clk_i => clk_i,
- FallEdge_o => s_AS_FallingEdge
- );
-
--- INT_ReqinputSample : process(clk_i)
- p_int_retry : process(clk_i)
+ p_detect_as_edges : process(clk_i)
begin
if rising_edge(clk_i) then
- if reset_n_i = '0' then
- int_trigger_p <= '0';
- retry_count <= (others => '0');
- retry_state <= R_IDLE;
- else
- case retry_state is
- when R_IDLE =>
- if(INT_Req_i = '1') then
- retry_state <= R_IRQ;
- end if;
-
- when R_IRQ =>
- retry_count <= (others => '0');
- int_trigger_p <= '1';
- retry_state <= R_WAIT_RETRY;
-
- when R_WAIT_RETRY =>
- int_trigger_p <= '0';
-
- if(INT_Req_i = '1') then
- retry_count <= retry_count + 1;
- if(retry_count = g_retry_timeout) then
- retry_state <= R_IRQ;
- end if;
- else
- retry_state <= R_IDLE;
- end if;
- end case;
- end if;
- --s_INT_Req_sample <= INT_Req_i;
+ as_n_d0 <= VME_AS_n_i;
+ as_rising_p <= not as_n_d0 and VME_AS_n_i;
+ as_falling_p <= as_n_d0 and not VME_AS_n_i;
end if;
end process;
--Output registers:
- DTACKOutputSample : process(clk_i)
- begin
- if rising_edge(clk_i) then
- VME_DTACK_n_o <= s_FSM_IRQ.s_DTACK;
- end if;
- end process;
-
- DataDirOutputSample : process(clk_i)
- begin
- if rising_edge(clk_i) then
- VME_DATA_DIR_o <= s_FSM_IRQ.s_DataDir;
- end if;
- end process;
-
- DTACKOEOutputSample : process(clk_i)
- begin
- if rising_edge(clk_i) then
- s_DTACK_OE_o <= s_FSM_IRQ.s_DTACK_OE;
- end if;
- end process;
-
process(clk_i)
begin
if rising_edge(clk_i) then
- if s_FSM_IRQ.s_resetIRQ = '1' then
- VME_IRQ_n_o <= (others => '1');
- elsif s_FSM_IRQ.s_enableIRQ = '1' then
- VME_IRQ_n_o <= s_IRQ;
+ if as_falling_p = '1' then
+ vme_addr_latched <= VME_ADDR_123_i;
end if;
end if;
end process;
- process(clk_i)
+-- DataDirOutputSample : process(clk_i)
+ p_retry_fsm : process(clk_i)
begin
if rising_edge(clk_i) then
- VME_DATA_o <= s_Data;
- end if;
- end process;
+ if reset_n_i = '0' then
+ retry_mask <= '1';
+ retry_state <= WAIT_IRQ;
+ else
+ case retry_state is
+ when WAIT_IRQ =>
+ if(state = IRQ and INT_Req_i = '1') then
+ retry_state <= WAIT_RETRY;
+ retry_count <= (others => '0');
+ retry_mask <= '0';
+ else
+ retry_mask <= '1';
+ end if;
+ when WAIT_RETRY =>
+ if(INT_Req_i = '0') then
+ retry_state <= WAIT_IRQ;
+ else
+ retry_count <= retry_count + 1;
+ if(retry_count = g_retry_timeout) then
+ retry_state <= WAIT_IRQ;
+ end if;
+ end if;
+ end case;
+ end if;
+ end if;
+ end process;
--- Update current state
- process(clk_i)
+ p_main_fsm : process(clk_i)
begin
if rising_edge(clk_i) then
if reset_n_i = '0' then
- s_currs <= IDLE;
+ state <= IDLE;
+ VME_IACKOUT_n_o <= '1';
+ VME_DATA_DIR_o <= '0';
+ VME_DTACK_n_o <= '1';
+ VME_DTACK_OE_o <= '0';
else
- s_currs <= s_nexts;
- end if;
- end if;
- end process;
--- Update next state
- process(s_currs, int_trigger_p, VME_AS_n_i, VME_DS_n_i, s_ack_int, VME_IACKIN_n_i, s_AS_RisingEdge)
- begin
- case s_currs is
- when IDLE =>
- --if s_INT_Req_sample = '1' and VME_IACKIN_n_i = '1' then
- if int_trigger_p = '1' and VME_IACKIN_n_i = '1' then
- s_nexts <= IRQ;
- elsif VME_IACKIN_n_i = '0' then
- s_nexts <= IACKOUT2;
- else
- s_nexts <= IDLE;
- end if;
+ case state is
+ when IDLE =>
- when IRQ =>
- if VME_IACKIN_n_i = '0' then -- Each Interrupter who is driving an interrupt request line
- -- low waits for a falling edge on IACKIN input -->
- -- the IRQ_Controller have to detect a falling edge on the IACKIN.
- s_nexts <= WAIT_AS;
- else
- s_nexts <= IRQ;
- end if;
+ VME_IACKOUT_n_o <= '1';
+ VME_DATA_DIR_o <= '0';
+ VME_DTACK_n_o <= '1';
+ VME_DTACK_OE_o <= '0';
+ VME_IRQ_n_o <= (others => '1');
- when WAIT_AS =>
- if VME_AS_n_i = '0' then -- NOT USE FALLING EDGE HERE!
- s_nexts <= WAIT_DS;
- else
- s_nexts <= WAIT_AS;
- end if;
-
- when WAIT_DS =>
- if VME_DS_n_i /= "11" then
- s_nexts <= CHECK;
- else
- s_nexts <= WAIT_DS;
- end if;
--- when LATCH_DS => -- this state is necessary only for D16 ans D32 Interrupters
--- s_nexts <= CHECK;
--- If the interrupter is D16 or D32 add a generic number of LATCH_DS state like in the VME_bus component.
- when CHECK =>
- if s_ack_int = '1' then
- s_nexts <= DATA_OUT; -- The Interrupter send the INT_Vector
- else
- s_nexts <= IACKOUT1; -- the Interrupter must pass a falling edge on the IACKOUT output
- end if;
-
- when IACKOUT1 =>
- if s_AS_RisingEdge = '1' then
- s_nexts <= IRQ;
- else
- s_nexts <= IACKOUT1;
- end if;
-
-
- when DATA_OUT =>
- s_nexts <= DTACK;
-
- when IACKOUT2 =>
- if s_AS_RisingEdge = '1' then
- s_nexts <= IDLE;
- else
- s_nexts <= IACKOUT2;
- end if;
-
- when DTACK =>
- if s_AS_RisingEdge = '1' then
- s_nexts <= IDLE;
- else
- s_nexts <= DTACK;
- end if;
- when others => null;
- end case;
-
- end process;
--- Update Outputs
--- Mealy FSM
- process(s_currs, VME_AS1_n_i)
- begin
-
- case s_currs is
- when IDLE =>
-
- s_FSM_IRQ.s_IACKOUT <= '1';
- s_FSM_IRQ.s_DataDir <= '0';
- s_FSM_IRQ.s_DTACK <= '1';
- s_FSM_IRQ.s_enableIRQ <= '0';
- s_FSM_IRQ.s_resetIRQ <= '1';
- s_FSM_IRQ.s_DSlatch <= '0';
- s_FSM_IRQ.s_DTACK_OE <= '0';
-
- when IRQ =>
- s_FSM_IRQ.s_IACKOUT <= '1';
- s_FSM_IRQ.s_DataDir <= '0';
- s_FSM_IRQ.s_DTACK <= '1';
- s_FSM_IRQ.s_DSlatch <= '0';
- s_FSM_IRQ.s_DTACK_OE <= '0';
- s_FSM_IRQ.s_enableIRQ <= '1';
- s_FSM_IRQ.s_resetIRQ <= '0';
-
- when WAIT_AS =>
-
- s_FSM_IRQ.s_IACKOUT <= '1';
- s_FSM_IRQ.s_DataDir <= '0';
- s_FSM_IRQ.s_DTACK <= '1';
- s_FSM_IRQ.s_enableIRQ <= '0';
- s_FSM_IRQ.s_DSlatch <= '0';
- s_FSM_IRQ.s_DTACK_OE <= '0';
- s_FSM_IRQ.s_resetIRQ <= '0';
-
- when WAIT_DS =>
- s_FSM_IRQ.s_IACKOUT <= '1';
- s_FSM_IRQ.s_DataDir <= '0';
- s_FSM_IRQ.s_DTACK <= '1';
- s_FSM_IRQ.s_enableIRQ <= '0';
- s_FSM_IRQ.s_DSlatch <= '0';
- s_FSM_IRQ.s_DTACK_OE <= '0';
- s_FSM_IRQ.s_resetIRQ <= '0';
-
--- when LATCH_DS =>
--- s_IACKOUT <= '1';
--- s_DataDir <= '0';
--- s_DTACK <= '1';
--- s_enableIRQ <= '0';
--- s_resetIRQ <= '0';
--- s_DSlatch <= '1';
--- s_DTACK_OE <= '0';
-
- when CHECK =>
- s_FSM_IRQ.s_IACKOUT <= '1';
- s_FSM_IRQ.s_DataDir <= '0';
- s_FSM_IRQ.s_DTACK <= '1';
- s_FSM_IRQ.s_enableIRQ <= '0';
- s_FSM_IRQ.s_DSlatch <= '0';
- s_FSM_IRQ.s_DTACK_OE <= '0';
- s_FSM_IRQ.s_resetIRQ <= '0';
-
- when IACKOUT1 =>
- s_FSM_IRQ. s_DataDir <= '0';
- s_FSM_IRQ. s_DTACK <= '1';
- s_FSM_IRQ. s_enableIRQ <= '0';
- s_FSM_IRQ. s_DSlatch <= '0';
- s_FSM_IRQ. s_DTACK_OE <= '0';
- s_FSM_IRQ.s_resetIRQ <= '0';
- s_FSM_IRQ.s_IACKOUT <= '0';
-
- when IACKOUT2 =>
- s_FSM_IRQ. s_DataDir <= '0';
- s_FSM_IRQ. s_DTACK <= '1';
- s_FSM_IRQ. s_enableIRQ <= '0';
- s_FSM_IRQ. s_DSlatch <= '0';
- s_FSM_IRQ. s_DTACK_OE <= '0';
- s_FSM_IRQ.s_resetIRQ <= '0';
- s_FSM_IRQ.s_IACKOUT <= '0';
-
- when DATA_OUT =>
- s_FSM_IRQ.s_IACKOUT <= '1';
- s_FSM_IRQ. s_DTACK <= '1';
- s_FSM_IRQ. s_enableIRQ <= '0';
- s_FSM_IRQ. s_DSlatch <= '0';
- s_FSM_IRQ.s_DataDir <= '1';
- s_FSM_IRQ.s_resetIRQ <= '0';
- s_FSM_IRQ.s_DTACK_OE <= '1';
+ if INT_Req_i = '1' and retry_mask = '1' then
+ if VME_IACKIN_n_i /= '0' then
+ state <= IRQ;
+ VME_IRQ_n_o <= f_select_irq_line(INT_Level_i);
+ else
+ -- IACK in progress, wait until idle
+ state <= SCHEDULE_IRQ;
+ end if;
+ -- just forward IACK to the next card in the daisy chain.
+ elsif VME_IACKIN_n_i = '0' and VME_DS_n_i /= "11" then
+ VME_IACKOUT_n_o <= '0';
+ state <= IACKOUT2;
+ end if;
+ when SCHEDULE_IRQ =>
+ if(VME_IACKIN_n_i /= '0') then
+ VME_IRQ_n_o <= f_select_irq_line(INT_Level_i);
+ state <= IRQ;
+ end if;
+
+ when IRQ =>
+ if VME_IACKIN_n_i = '0' then
+ -- Each Interrupter who is driving an interrupt request line
+ -- low waits for a falling edge on IACKIN input -->
+ -- the IRQ_Controller have to detect a falling edge on the IACKIN.
+ state <= WAIT_AS;
+ end if;
- when DTACK =>
- s_FSM_IRQ.s_IACKOUT <= '1';
- s_FSM_IRQ. s_enableIRQ <= '0';
- s_FSM_IRQ. s_resetIRQ <= '1';
- s_FSM_IRQ. s_DSlatch <= '0';
- s_FSM_IRQ.s_DataDir <= '1';
- s_FSM_IRQ.s_DTACK <= '0';
- s_FSM_IRQ.s_DTACK_OE <= '1';
+ when WAIT_AS =>
+ if VME_AS_n_i = '0' then
+ state <= WAIT_DS;
+ end if;
--- when others => null;
- end case;
- end process;
+ when WAIT_DS =>
+ if VME_DS_n_i /= "11" then
+ state <= CHECK;
+ end if;
--- This process provides the IRQ vector
- process(INT_Level_i)
- begin
- case (INT_Level_i) is
- when "00000001" => s_IRQ <= "1111110";
- when "00000010" => s_IRQ <= "1111101";
- when "00000011" => s_IRQ <= "1111011";
- when "00000100" => s_IRQ <= "1110111";
- when "00000101" => s_IRQ <= "1101111";
- when "00000110" => s_IRQ <= "1011111";
- when "00000111" => s_IRQ <= "0111111";
- when others => s_IRQ <= "1111111";
- end case;
- end process;
+ when CHECK =>
+ if vme_addr_latched = INT_Level_i(2 downto 0) then
+ state <= DATA_OUT; -- The Interrupter send the INT_Vector
+ VME_DATA_DIR_o <= '1';
+ VME_DTACK_OE_o <= '1';
+ VME_DTACK_n_o <= '1';
+ else
+ state <= IACKOUT1; -- the Interrupter must pass a falling edge on the IACKOUT output
+ VME_IACKOUT_n_o <= '0';
+ end if;
--- This process sampling the address lines on AS falling edge
- process(clk_i)
- begin
- if rising_edge(clk_i) then
- if reset_n_i = '0' then
- s_VME_ADDR_123_latched <= (others => '0');
- elsif s_AS_FallingEdge = '1' then
- s_VME_ADDR_123_latched <= VME_ADDR_123_i;
- end if;
- end if;
- end process;
+ when IACKOUT1 =>
+ if as_rising_p = '1' then
+ VME_IACKOUT_n_o <= '1';
+ state <= IRQ;
+ end if;
--- Data strobo latch
- process(clk_i)
- begin
- if rising_edge(clk_i) then
- if reset_n_i = '0' then
- s_VME_DS_latched <= (others => '0');
- elsif s_FSM_IRQ.s_DSlatch = '1' then
- s_VME_DS_latched <= VME_DS_n_i;
- end if;
- end if;
- end process;
+ when IACKOUT2 =>
+ if VME_AS_n_i = '1' then
+ VME_IACKOUT_n_o <= '1';
+ state <= IDLE;
+ end if;
+
+ when DATA_OUT =>
+ VME_DTACK_n_o <= '0';
+ VME_IRQ_n_o <= (others => '1');
+ state <= DTACK;
+
+ when DTACK =>
+ if as_rising_p = '1' then
+ VME_DTACK_OE_o <= '0';
+ VME_DATA_DIR_o <= '0';
+ state <= IDLE;
+ end if;
+ end case;
+ end if;
+ end if;
+ end process;
---This process check the A01 A02 A03:
- process(clk_i)
- begin
- if rising_edge(clk_i) then
- if reset_n_i = '0' then
- s_ADDRmatch <= '0';
- elsif unsigned(INT_Level_i) = unsigned(s_VME_ADDR_123_latched) then
- s_ADDRmatch <= '1';
- else
- s_ADDRmatch <= '0';
- end if;
- end if;
- end process;
- s_ack_int <= s_ADDRmatch; --D08 Interrupter
- -- s_ack_int <= (not(s_VME_DS_latched(1))) and s_ADDRmatch and (not(VME_LWORD_n_i))
- -- for a D32 Interrupter
+ VME_DATA_o <= x"000000" & INT_Vector_i;
- s_Data <= x"000000" & INT_Vector_i;
- s_enable <= ((not s_FSM_IRQ.s_DTACK) and (s_AS_RisingEdge));
- -- the INT_Vector is in the D0:D7 lines (byte3 in big endian order)
- VME_DTACK_OE_o <= s_DTACK_OE_o;
- VME_IACKOUT_n_o <= s_FSM_IRQ.s_IACKOUT;
end Behavioral;
--===========================================================================
-- Architecture end
diff --git a/hdl/ip_cores/VMEcore/vme64x_pack.vhd b/hdl/ip_cores/VMEcore/vme64x_pack.vhd
index 6b312c608f2ec998e90817cccd85cdd7cb3a8027..afe38db429e01489ecb1a00f111ae829250e9d1f 100644
--- a/hdl/ip_cores/VMEcore/vme64x_pack.vhd
+++ b/hdl/ip_cores/VMEcore/vme64x_pack.vhd
@@ -361,6 +361,7 @@ constant c_STOP : integer := (to_integer("00" & c_FUNC7_ADER_0_addr(18 downto 2)
DECIDE_NEXT_CYCLE,
INCREMENT_ADDR,
SET_DATA_PHASE
+-- UGLY_WAIT_TO_MAKE_DECODING_WORK
-- uncomment for using 2e modes:
-- WAIT_FOR_DS_2e,
-- ADDR_PHASE_1,
@@ -812,26 +813,25 @@ constant c_STOP : integer := (to_integer("00" & c_FUNC7_ADER_0_addr(18 downto 2)
component VME_IRQ_Controller is
+ generic(
+ g_retry_timeout : integer range 1024 to 16777215);
port(
clk_i : in std_logic;
reset_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_AS_n_i : in std_logic;
- VME_AS1_n_i : in std_logic;
- VME_DS_n_i : in std_logic_vector(1 downto 0);
- VME_LWORD_n_i : in std_logic;
- VME_ADDR_123_i : in std_logic_vector(2 downto 0);
- INT_Level_i : in std_logic_vector(7 downto 0);
- INT_Vector_i : in std_logic_vector(7 downto 0);
+ VME_DS_n_i : in std_logic_vector (1 downto 0);
+ VME_ADDR_123_i : in std_logic_vector (2 downto 0);
+ INT_Level_i : in std_logic_vector (7 downto 0);
+ INT_Vector_i : in std_logic_vector (7 downto 0);
INT_Req_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
- VME_DATA_o : out std_logic_vector(31 downto 0);
- VME_DATA_DIR_o : out std_logic
- );
- end component VME_IRQ_Controller;
+ VME_DATA_o : out std_logic_vector (31 downto 0);
+ VME_DATA_DIR_o : out std_logic);
+ end component;
component VME_CRAM is
generic (dl : integer := 8;
diff --git a/hdl/syn/svec/svec-tdc-fmc.gise b/hdl/syn/svec/svec-tdc-fmc.gise
index 143eb2a9701d781ebd007b4a6a3114fc5f2768d7..b673f20d0da3d93f705447b1c49c352b97084d55 100644
--- a/hdl/syn/svec/svec-tdc-fmc.gise
+++ b/hdl/syn/svec/svec-tdc-fmc.gise
@@ -103,7 +103,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1385128254" xil_pn:in_ck="5268971704634117961" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7543648610729664005" xil_pn:start_ts="1385128088">
+ <transform xil_pn:end_ts="1385649337" xil_pn:in_ck="5268971704634117961" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7543648610729664005" xil_pn:start_ts="1385649161">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -125,7 +125,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1385128269" xil_pn:in_ck="-3760130385703199631" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="8504525175841796663" xil_pn:start_ts="1385128254">
+ <transform xil_pn:end_ts="1385649353" xil_pn:in_ck="-3760130385703199631" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="8504525175841796663" xil_pn:start_ts="1385649337">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -135,7 +135,7 @@
<outfile xil_pn:name="top_tdc.ngd"/>
<outfile xil_pn:name="top_tdc_ngdbuild.xrpt"/>
</transform>
- <transform xil_pn:end_ts="1385128482" xil_pn:in_ck="-7440346353620165565" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7568465460566446564" xil_pn:start_ts="1385128269">
+ <transform xil_pn:end_ts="1385649562" xil_pn:in_ck="-7440346353620165565" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7568465460566446564" xil_pn:start_ts="1385649353">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
@@ -148,7 +148,7 @@
<outfile xil_pn:name="top_tdc_summary.xml"/>
<outfile xil_pn:name="top_tdc_usage.xml"/>
</transform>
- <transform xil_pn:end_ts="1385128706" xil_pn:in_ck="4998236143670007004" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-7978487711023391987" xil_pn:start_ts="1385128482">
+ <transform xil_pn:end_ts="1385649703" xil_pn:in_ck="4998236143670007004" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-7978487711023391987" xil_pn:start_ts="1385649562">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -163,7 +163,7 @@
<outfile xil_pn:name="top_tdc_pad.txt"/>
<outfile xil_pn:name="top_tdc_par.xrpt"/>
</transform>
- <transform xil_pn:end_ts="1385128766" xil_pn:in_ck="182976557419624816" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5293564962942599218" xil_pn:start_ts="1385128706">
+ <transform xil_pn:end_ts="1385649768" xil_pn:in_ck="182976557419624816" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5293564962942599218" xil_pn:start_ts="1385649703">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
@@ -175,7 +175,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
- <transform xil_pn:end_ts="1385128706" xil_pn:in_ck="-7440346353620165697" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1385128683">
+ <transform xil_pn:end_ts="1385649703" xil_pn:in_ck="-7440346353620165697" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1385649681">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
diff --git a/hdl/syn/svec/top_tdc.bin b/hdl/syn/svec/top_tdc.bin
index 44e260b755c7edbf00d26ed849199f1728754e4b..9b755a7b90bc3bd29d84d1a92ad1d1e992651649 100644
Binary files a/hdl/syn/svec/top_tdc.bin and b/hdl/syn/svec/top_tdc.bin differ
diff --git a/hdl/syn/svec/top_tdc.twr b/hdl/syn/svec/top_tdc.twr
index 0b4d0587d535705e9df73bf39ceb21c06bcf3417..016ceb85d8df815834450fa33f7f450878d2d32b 100644
--- a/hdl/syn/svec/top_tdc.twr
+++ b/hdl/syn/svec/top_tdc.twr
@@ -43,99 +43,99 @@ For more information, see From:To (Multicycle) Analysis in the Timing Closure Us
11 paths analyzed, 11 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is 4.804ns.
+ Maximum delay is 6.225ns.
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_2 (SLICE_X56Y75.CX), 1 path
+Paths for end point cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_3 (SLICE_X44Y59.BX), 1 path
--------------------------------------------------------------------------------
-Slack (setup paths): 15.196ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_2 (FF)
- Destination: cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_2 (FF)
+Slack (setup paths): 13.775ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_3 (FF)
+ Destination: cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_3 (FF)
Requirement: 20.000ns
- Data Path Delay: 4.804ns (Levels of Logic = 0)
+ Data Path Delay: 6.225ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: clk_62m5_sys rising
Clock Uncertainty: 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_2 to cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_2
+ Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_3 to cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X57Y145.DQ Tcko 0.391 cmp_tdc1_clks_crossing/sfifo/w_idx_gray<2>
- cmp_tdc1_clks_crossing/sfifo/w_idx_gray_2
- SLICE_X56Y75.CX net (fanout=1) 4.458 cmp_tdc1_clks_crossing/sfifo/w_idx_gray<2>
- SLICE_X56Y75.CLK Tds -0.045 cmp_tdc2_clks_crossing/mfifo/r_idx_shift_w_3<1>
- cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_2
+ SLICE_X70Y135.DMUX Tshcko 0.455 cmp_tdc1_clks_crossing/sfifo/w_idx_bnry<4>
+ cmp_tdc1_clks_crossing/sfifo/w_idx_gray_3
+ SLICE_X44Y59.BX net (fanout=1) 5.850 cmp_tdc1_clks_crossing/sfifo/w_idx_gray<3>
+ SLICE_X44Y59.CLK Tds -0.080 cmp_tdc2_clks_crossing/mfifo/r_idx_shift_w_3<1>
+ cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_3
------------------------------------------------- ---------------------------
- Total 4.804ns (0.346ns logic, 4.458ns route)
- (7.2% logic, 92.8% route)
+ Total 6.225ns (0.375ns logic, 5.850ns route)
+ (6.0% logic, 94.0% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_3 (SLICE_X56Y75.BX), 1 path
+Paths for end point cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_2 (SLICE_X44Y59.CX), 1 path
--------------------------------------------------------------------------------
-Slack (setup paths): 15.263ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_3 (FF)
- Destination: cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_3 (FF)
+Slack (setup paths): 13.826ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_2 (FF)
+ Destination: cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_2 (FF)
Requirement: 20.000ns
- Data Path Delay: 4.737ns (Levels of Logic = 0)
+ Data Path Delay: 6.174ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: clk_62m5_sys rising
Clock Uncertainty: 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_3 to cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_3
+ Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_2 to cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X57Y144.DMUX Tshcko 0.461 cmp_tdc1_clks_crossing/sfifo/w_idx_bnry<4>
- cmp_tdc1_clks_crossing/sfifo/w_idx_gray_3
- SLICE_X56Y75.BX net (fanout=1) 4.356 cmp_tdc1_clks_crossing/sfifo/w_idx_gray<3>
- SLICE_X56Y75.CLK Tds -0.080 cmp_tdc2_clks_crossing/mfifo/r_idx_shift_w_3<1>
- cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_3
+ SLICE_X71Y135.DQ Tcko 0.391 cmp_tdc1_clks_crossing/sfifo/w_idx_gray<2>
+ cmp_tdc1_clks_crossing/sfifo/w_idx_gray_2
+ SLICE_X44Y59.CX net (fanout=1) 5.828 cmp_tdc1_clks_crossing/sfifo/w_idx_gray<2>
+ SLICE_X44Y59.CLK Tds -0.045 cmp_tdc2_clks_crossing/mfifo/r_idx_shift_w_3<1>
+ cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_2
------------------------------------------------- ---------------------------
- Total 4.737ns (0.381ns logic, 4.356ns route)
- (8.0% logic, 92.0% route)
+ Total 6.174ns (0.346ns logic, 5.828ns route)
+ (5.6% logic, 94.4% route)
--------------------------------------------------------------------------------
-Paths for end point tdc1_irq_synch_0 (SLICE_X59Y114.AX), 1 path
+Paths for end point cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_4 (SLICE_X44Y112.BX), 1 path
--------------------------------------------------------------------------------
-Slack (setup paths): 17.201ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1/cmp_irq_controller/eic_irq_controller_inst/wb_irq_o (FF)
- Destination: tdc1_irq_synch_0 (FF)
+Slack (setup paths): 16.839ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1_clks_crossing/sfifo/w_idx_bnry_4 (FF)
+ Destination: cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_4 (FF)
Requirement: 20.000ns
- Data Path Delay: 2.799ns (Levels of Logic = 0)
+ Data Path Delay: 3.161ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: clk_62m5_sys rising
Clock Uncertainty: 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_irq_controller/eic_irq_controller_inst/wb_irq_o to tdc1_irq_synch_0
+ Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_crossing/sfifo/w_idx_bnry_4 to cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_4
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X68Y140.DQ Tcko 0.447 cmp_tdc1/cmp_irq_controller/eic_irq_controller_inst/wb_irq_o
- cmp_tdc1/cmp_irq_controller/eic_irq_controller_inst/wb_irq_o
- SLICE_X59Y114.AX net (fanout=1) 2.289 cmp_tdc1/cmp_irq_controller/eic_irq_controller_inst/wb_irq_o
- SLICE_X59Y114.CLK Tdick 0.063 tdc1_irq_synch<1>
- tdc1_irq_synch_0
+ SLICE_X70Y135.DQ Tcko 0.408 cmp_tdc1_clks_crossing/sfifo/w_idx_bnry<4>
+ cmp_tdc1_clks_crossing/sfifo/w_idx_bnry_4
+ SLICE_X44Y112.BX net (fanout=2) 2.833 cmp_tdc1_clks_crossing/sfifo/w_idx_bnry<4>
+ SLICE_X44Y112.CLK Tds -0.080 cmp_tdc1_clks_crossing/sfifo/r_idx_shift_a_3<1>
+ cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_4
------------------------------------------------- ---------------------------
- Total 2.799ns (0.510ns logic, 2.289ns route)
- (18.2% logic, 81.8% route)
+ Total 3.161ns (0.328ns logic, 2.833ns route)
+ (10.4% logic, 89.6% route)
--------------------------------------------------------------------------------
Hold Paths: ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP "tdc1_clk_125m" TO TIMEGRP "clk_62m5_sys" 20 ns DATAPATHONLY;
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_3 (SLICE_X72Y123.AX), 1 path
+Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_3 (SLICE_X72Y118.AX), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.931ns (requirement - (clock path skew + uncertainty - data path))
+Slack (hold path): 0.975ns (requirement - (clock path skew + uncertainty - data path))
Source: cmp_tdc1_clks_crossing/mfifo/r_idx_gray_3 (FF)
Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_3 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.931ns (Levels of Logic = 0)
+ Data Path Delay: 0.975ns (Levels of Logic = 0)
Positive Clock Path Skew: 0.000ns
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: clk_62m5_sys rising
@@ -145,66 +145,66 @@ Slack (hold path): 0.931ns (requirement - (clock path skew + uncertainty -
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X77Y136.BMUX Tshcko 0.244 cmp_tdc1_clks_crossing/mfifo/r_idx_bnry<4>
+ SLICE_X80Y131.BMUX Tshcko 0.266 cmp_tdc1_clks_crossing/mfifo/r_idx_bnry<4>
cmp_tdc1_clks_crossing/mfifo/r_idx_gray_3
- SLICE_X72Y123.AX net (fanout=2) 0.757 cmp_tdc1_clks_crossing/mfifo/r_idx_gray<3>
- SLICE_X72Y123.CLK Tdh (-Th) 0.070 cmp_tdc1_clks_crossing/mfifo/r_idx_shift_w_3<4>
+ SLICE_X72Y118.AX net (fanout=2) 0.779 cmp_tdc1_clks_crossing/mfifo/r_idx_gray<3>
+ SLICE_X72Y118.CLK Tdh (-Th) 0.070 cmp_tdc1_clks_crossing/mfifo/r_idx_shift_w_3<4>
cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_3
------------------------------------------------- ---------------------------
- Total 0.931ns (0.174ns logic, 0.757ns route)
- (18.7% logic, 81.3% route)
+ Total 0.975ns (0.196ns logic, 0.779ns route)
+ (20.1% logic, 79.9% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_1 (SLICE_X72Y123.CX), 1 path
+Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_4 (SLICE_X72Y118.DI), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.934ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc1_clks_crossing/mfifo/r_idx_gray_1 (FF)
- Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_1 (FF)
+Slack (hold path): 1.008ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc1_clks_crossing/mfifo/r_idx_bnry_4 (FF)
+ Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_4 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.934ns (Levels of Logic = 0)
+ Data Path Delay: 1.008ns (Levels of Logic = 0)
Positive Clock Path Skew: 0.000ns
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: clk_62m5_sys rising
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/mfifo/r_idx_gray_1 to cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_1
+ Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/mfifo/r_idx_bnry_4 to cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_4
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X77Y137.CQ Tcko 0.198 cmp_tdc1_clks_crossing/mfifo/r_idx_gray<2>
- cmp_tdc1_clks_crossing/mfifo/r_idx_gray_1
- SLICE_X72Y123.CX net (fanout=2) 0.781 cmp_tdc1_clks_crossing/mfifo/r_idx_gray<1>
- SLICE_X72Y123.CLK Tdh (-Th) 0.045 cmp_tdc1_clks_crossing/mfifo/r_idx_shift_w_3<4>
- cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_1
+ SLICE_X80Y131.BQ Tcko 0.234 cmp_tdc1_clks_crossing/mfifo/r_idx_bnry<4>
+ cmp_tdc1_clks_crossing/mfifo/r_idx_bnry_4
+ SLICE_X72Y118.DI net (fanout=3) 0.741 cmp_tdc1_clks_crossing/mfifo/r_idx_bnry<4>
+ SLICE_X72Y118.CLK Tdh (-Th) -0.033 cmp_tdc1_clks_crossing/mfifo/r_idx_shift_w_3<4>
+ cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_4
------------------------------------------------- ---------------------------
- Total 0.934ns (0.153ns logic, 0.781ns route)
- (16.4% logic, 83.6% route)
+ Total 1.008ns (0.267ns logic, 0.741ns route)
+ (26.5% logic, 73.5% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_0 (SLICE_X72Y123.DX), 1 path
+Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_2 (SLICE_X72Y118.BX), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.946ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc1_clks_crossing/mfifo/r_idx_gray_0 (FF)
- Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_0 (FF)
+Slack (hold path): 1.022ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc1_clks_crossing/mfifo/r_idx_gray_2 (FF)
+ Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_2 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.946ns (Levels of Logic = 0)
+ Data Path Delay: 1.022ns (Levels of Logic = 0)
Positive Clock Path Skew: 0.000ns
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: clk_62m5_sys rising
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/mfifo/r_idx_gray_0 to cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_0
+ Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/mfifo/r_idx_gray_2 to cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X76Y137.BMUX Tshcko 0.266 cmp_tdc1_clks_crossing/mfifo/r_idx_bnry<3>
- cmp_tdc1_clks_crossing/mfifo/r_idx_gray_0
- SLICE_X72Y123.DX net (fanout=2) 0.780 cmp_tdc1_clks_crossing/mfifo/r_idx_gray<0>
- SLICE_X72Y123.CLK Tdh (-Th) 0.100 cmp_tdc1_clks_crossing/mfifo/r_idx_shift_w_3<4>
- cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_0
+ SLICE_X81Y133.DQ Tcko 0.198 cmp_tdc1_clks_crossing/mfifo/r_idx_gray<2>
+ cmp_tdc1_clks_crossing/mfifo/r_idx_gray_2
+ SLICE_X72Y118.BX net (fanout=2) 0.904 cmp_tdc1_clks_crossing/mfifo/r_idx_gray<2>
+ SLICE_X72Y118.CLK Tdh (-Th) 0.080 cmp_tdc1_clks_crossing/mfifo/r_idx_shift_w_3<4>
+ cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_2
------------------------------------------------- ---------------------------
- Total 0.946ns (0.166ns logic, 0.780ns route)
- (17.5% logic, 82.5% route)
+ Total 1.022ns (0.118ns logic, 0.904ns route)
+ (11.5% logic, 88.5% route)
--------------------------------------------------------------------------------
================================================================================
@@ -214,70 +214,70 @@ For more information, see From:To (Multicycle) Analysis in the Timing Closure Us
5 paths analyzed, 5 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is 1.191ns.
+ Maximum delay is 1.218ns.
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_1 (SLICE_X76Y135.DI), 1 path
+Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_3 (SLICE_X80Y130.BI), 1 path
--------------------------------------------------------------------------------
-Slack (setup paths): 18.809ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_1 (FF)
- Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_1 (FF)
+Slack (setup paths): 18.782ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_3 (FF)
+ Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_3 (FF)
Requirement: 20.000ns
- Data Path Delay: 1.191ns (Levels of Logic = 0)
+ Data Path Delay: 1.218ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: tdc1_clk_125m rising at 0.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_1 to cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_1
+ Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_3 to cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X85Y135.AQ Tcko 0.391 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<2>
- cmp_tdc1_clks_crossing/mfifo/w_idx_gray_1
- SLICE_X76Y135.DI net (fanout=2) 0.772 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<1>
- SLICE_X76Y135.CLK Tds 0.028 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
- cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_1
+ SLICE_X77Y129.BMUX Tshcko 0.461 cmp_tdc1_clks_crossing/mfifo/w_idx_bnry<1>
+ cmp_tdc1_clks_crossing/mfifo/w_idx_gray_3
+ SLICE_X80Y130.BI net (fanout=2) 0.727 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<3>
+ SLICE_X80Y130.CLK Tds 0.030 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
+ cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_3
------------------------------------------------- ---------------------------
- Total 1.191ns (0.419ns logic, 0.772ns route)
- (35.2% logic, 64.8% route)
+ Total 1.218ns (0.491ns logic, 0.727ns route)
+ (40.3% logic, 59.7% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_2 (SLICE_X76Y135.CI), 1 path
+Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_0 (SLICE_X80Y130.AX), 1 path
--------------------------------------------------------------------------------
-Slack (setup paths): 18.820ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_2 (FF)
- Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_2 (FF)
+Slack (setup paths): 18.946ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_0 (FF)
+ Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_0 (FF)
Requirement: 20.000ns
- Data Path Delay: 1.180ns (Levels of Logic = 0)
+ Data Path Delay: 1.054ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: tdc1_clk_125m rising at 0.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_2 to cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_2
+ Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_0 to cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X85Y135.BQ Tcko 0.391 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<2>
- cmp_tdc1_clks_crossing/mfifo/w_idx_gray_2
- SLICE_X76Y135.CI net (fanout=2) 0.724 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<2>
- SLICE_X76Y135.CLK Tds 0.065 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
- cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_2
+ SLICE_X77Y129.DMUX Tshcko 0.461 cmp_tdc1_clks_crossing/mfifo/w_idx_bnry<1>
+ cmp_tdc1_clks_crossing/mfifo/w_idx_gray_0
+ SLICE_X80Y130.AX net (fanout=2) 0.653 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<0>
+ SLICE_X80Y130.CLK Tds -0.060 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
+ cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_0
------------------------------------------------- ---------------------------
- Total 1.180ns (0.456ns logic, 0.724ns route)
- (38.6% logic, 61.4% route)
+ Total 1.054ns (0.401ns logic, 0.653ns route)
+ (38.0% logic, 62.0% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_4 (SLICE_X76Y135.AI), 1 path
+Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_4 (SLICE_X80Y130.AI), 1 path
--------------------------------------------------------------------------------
-Slack (setup paths): 18.906ns (requirement - (data path - clock path skew + uncertainty))
+Slack (setup paths): 19.067ns (requirement - (data path - clock path skew + uncertainty))
Source: cmp_tdc1_clks_crossing/mfifo/w_idx_bnry_4 (FF)
Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_4 (FF)
Requirement: 20.000ns
- Data Path Delay: 1.094ns (Levels of Logic = 0)
+ Data Path Delay: 0.933ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: tdc1_clk_125m rising at 0.000ns
@@ -287,78 +287,78 @@ Slack (setup paths): 18.906ns (requirement - (data path - clock path skew + u
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X77Y135.BQ Tcko 0.391 cmp_tdc1_clks_crossing/mfifo/w_idx_bnry<1>
+ SLICE_X77Y129.BQ Tcko 0.391 cmp_tdc1_clks_crossing/mfifo/w_idx_bnry<1>
cmp_tdc1_clks_crossing/mfifo/w_idx_bnry_4
- SLICE_X76Y135.AI net (fanout=3) 0.665 cmp_tdc1_clks_crossing/mfifo/w_idx_bnry<4>
- SLICE_X76Y135.CLK Tds 0.038 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
+ SLICE_X80Y130.AI net (fanout=3) 0.504 cmp_tdc1_clks_crossing/mfifo/w_idx_bnry<4>
+ SLICE_X80Y130.CLK Tds 0.038 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_4
------------------------------------------------- ---------------------------
- Total 1.094ns (0.429ns logic, 0.665ns route)
- (39.2% logic, 60.8% route)
+ Total 0.933ns (0.429ns logic, 0.504ns route)
+ (46.0% logic, 54.0% route)
--------------------------------------------------------------------------------
Hold Paths: ts_ignore_xclock3 = MAXDELAY FROM TIMEGRP "clk_62m5_sys" TO TIMEGRP "tdc1_clk_125m" 20 ns DATAPATHONLY;
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_3 (SLICE_X76Y135.BI), 1 path
+Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_2 (SLICE_X80Y130.CI), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.427ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_3 (FF)
- Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_3 (FF)
+Slack (hold path): 0.403ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_2 (FF)
+ Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_2 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.427ns (Levels of Logic = 0)
+ Data Path Delay: 0.403ns (Levels of Logic = 0)
Positive Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: tdc1_clk_125m rising at 0.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_3 to cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_3
+ Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_2 to cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X77Y135.BMUX Tshcko 0.244 cmp_tdc1_clks_crossing/mfifo/w_idx_bnry<1>
- cmp_tdc1_clks_crossing/mfifo/w_idx_gray_3
- SLICE_X76Y135.BI net (fanout=2) 0.154 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<3>
- SLICE_X76Y135.CLK Tdh (-Th) -0.029 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
- cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_3
+ SLICE_X81Y130.BQ Tcko 0.198 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<2>
+ cmp_tdc1_clks_crossing/mfifo/w_idx_gray_2
+ SLICE_X80Y130.CI net (fanout=2) 0.155 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<2>
+ SLICE_X80Y130.CLK Tdh (-Th) -0.050 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
+ cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_2
------------------------------------------------- ---------------------------
- Total 0.427ns (0.273ns logic, 0.154ns route)
- (63.9% logic, 36.1% route)
+ Total 0.403ns (0.248ns logic, 0.155ns route)
+ (61.5% logic, 38.5% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_0 (SLICE_X76Y135.AX), 1 path
+Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_1 (SLICE_X80Y130.DI), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.491ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_0 (FF)
- Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_0 (FF)
+Slack (hold path): 0.425ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_1 (FF)
+ Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_1 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.491ns (Levels of Logic = 0)
+ Data Path Delay: 0.425ns (Levels of Logic = 0)
Positive Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: tdc1_clk_125m rising at 0.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_0 to cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_0
+ Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_1 to cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X77Y135.DMUX Tshcko 0.244 cmp_tdc1_clks_crossing/mfifo/w_idx_bnry<1>
- cmp_tdc1_clks_crossing/mfifo/w_idx_gray_0
- SLICE_X76Y135.AX net (fanout=2) 0.317 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<0>
- SLICE_X76Y135.CLK Tdh (-Th) 0.070 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
- cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_0
+ SLICE_X81Y130.AQ Tcko 0.198 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<2>
+ cmp_tdc1_clks_crossing/mfifo/w_idx_gray_1
+ SLICE_X80Y130.DI net (fanout=2) 0.194 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<1>
+ SLICE_X80Y130.CLK Tdh (-Th) -0.033 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
+ cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_1
------------------------------------------------- ---------------------------
- Total 0.491ns (0.174ns logic, 0.317ns route)
- (35.4% logic, 64.6% route)
+ Total 0.425ns (0.231ns logic, 0.194ns route)
+ (54.4% logic, 45.6% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_4 (SLICE_X76Y135.AI), 1 path
+Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_4 (SLICE_X80Y130.AI), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.569ns (requirement - (clock path skew + uncertainty - data path))
+Slack (hold path): 0.472ns (requirement - (clock path skew + uncertainty - data path))
Source: cmp_tdc1_clks_crossing/mfifo/w_idx_bnry_4 (FF)
Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_4 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.569ns (Levels of Logic = 0)
+ Data Path Delay: 0.472ns (Levels of Logic = 0)
Positive Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: tdc1_clk_125m rising at 0.000ns
@@ -368,14 +368,14 @@ Slack (hold path): 0.569ns (requirement - (clock path skew + uncertainty -
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X77Y135.BQ Tcko 0.198 cmp_tdc1_clks_crossing/mfifo/w_idx_bnry<1>
+ SLICE_X77Y129.BQ Tcko 0.198 cmp_tdc1_clks_crossing/mfifo/w_idx_bnry<1>
cmp_tdc1_clks_crossing/mfifo/w_idx_bnry_4
- SLICE_X76Y135.AI net (fanout=3) 0.341 cmp_tdc1_clks_crossing/mfifo/w_idx_bnry<4>
- SLICE_X76Y135.CLK Tdh (-Th) -0.030 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
+ SLICE_X80Y130.AI net (fanout=3) 0.244 cmp_tdc1_clks_crossing/mfifo/w_idx_bnry<4>
+ SLICE_X80Y130.CLK Tdh (-Th) -0.030 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_4
------------------------------------------------- ---------------------------
- Total 0.569ns (0.228ns logic, 0.341ns route)
- (40.1% logic, 59.9% route)
+ Total 0.472ns (0.228ns logic, 0.244ns route)
+ (48.3% logic, 51.7% route)
--------------------------------------------------------------------------------
================================================================================
@@ -385,189 +385,189 @@ For more information, see From:To (Multicycle) Analysis in the Timing Closure Us
8 paths analyzed, 4 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is 6.134ns.
+ Maximum delay is 7.445ns.
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2_clks_rsts_mgment/rst_in_synch_1 (SLICE_X84Y39.SR), 2 paths
+Paths for end point cmp_tdc1_clks_rsts_mgment/rst_in_synch_1 (SLICE_X56Y138.SR), 2 paths
--------------------------------------------------------------------------------
-Slack (setup paths): 193.866ns (requirement - (data path - clock path skew + uncertainty))
+Slack (setup paths): 192.555ns (requirement - (data path - clock path skew + uncertainty))
Source: rst_n_sys (FF)
- Destination: cmp_tdc2_clks_rsts_mgment/rst_in_synch_1 (FF)
+ Destination: cmp_tdc1_clks_rsts_mgment/rst_in_synch_1 (FF)
Requirement: 200.000ns
- Data Path Delay: 6.134ns (Levels of Logic = 1)
+ Data Path Delay: 7.445ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path at Slow Process Corner: rst_n_sys to cmp_tdc2_clks_rsts_mgment/rst_in_synch_1
+ Maximum Data Path at Slow Process Corner: rst_n_sys to cmp_tdc1_clks_rsts_mgment/rst_in_synch_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X69Y98.CQ Tcko 0.391 rst_n_sys
+ SLICE_X68Y98.CQ Tcko 0.447 rst_n_sys
rst_n_sys
- SLICE_X64Y92.D3 net (fanout=89) 1.120 rst_n_sys
- SLICE_X64Y92.D Tilo 0.203 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
- cmp_tdc2_clks_rsts_mgment/rst_n_i_inv1
- SLICE_X84Y39.SR net (fanout=1) 4.175 cmp_tdc2_clks_rsts_mgment/rst_n_i_inv
- SLICE_X84Y39.CLK Trck 0.245 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
- cmp_tdc2_clks_rsts_mgment/rst_in_synch_1
+ SLICE_X76Y79.D5 net (fanout=91) 2.011 rst_n_sys
+ SLICE_X76Y79.DMUX Tilo 0.261 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
+ cmp_tdc1_clks_rsts_mgment/rst_n_i_inv1
+ SLICE_X56Y138.SR net (fanout=1) 4.481 cmp_tdc1_clks_rsts_mgment/rst_n_i_inv
+ SLICE_X56Y138.CLK Trck 0.245 cmp_tdc1_clks_rsts_mgment/rst_in_synch<1>
+ cmp_tdc1_clks_rsts_mgment/rst_in_synch_1
------------------------------------------------- ---------------------------
- Total 6.134ns (0.839ns logic, 5.295ns route)
- (13.7% logic, 86.3% route)
+ Total 7.445ns (0.953ns logic, 6.492ns route)
+ (12.8% logic, 87.2% route)
--------------------------------------------------------------------------------
-Slack (setup paths): 194.495ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_carrier_csr/carrier_csr_ctrl_reserved_int_1 (FF)
- Destination: cmp_tdc2_clks_rsts_mgment/rst_in_synch_1 (FF)
+Slack (setup paths): 194.103ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_carrier_csr/carrier_csr_ctrl_reserved_int_0 (FF)
+ Destination: cmp_tdc1_clks_rsts_mgment/rst_in_synch_1 (FF)
Requirement: 200.000ns
- Data Path Delay: 5.505ns (Levels of Logic = 1)
+ Data Path Delay: 5.897ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_carrier_csr/carrier_csr_ctrl_reserved_int_1 to cmp_tdc2_clks_rsts_mgment/rst_in_synch_1
+ Maximum Data Path at Slow Process Corner: cmp_carrier_csr/carrier_csr_ctrl_reserved_int_0 to cmp_tdc1_clks_rsts_mgment/rst_in_synch_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X64Y92.CMUX Tshcko 0.488 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
- cmp_carrier_csr/carrier_csr_ctrl_reserved_int_1
- SLICE_X64Y92.D5 net (fanout=2) 0.394 cmp_carrier_csr/carrier_csr_ctrl_reserved_int<1>
- SLICE_X64Y92.D Tilo 0.203 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
- cmp_tdc2_clks_rsts_mgment/rst_n_i_inv1
- SLICE_X84Y39.SR net (fanout=1) 4.175 cmp_tdc2_clks_rsts_mgment/rst_n_i_inv
- SLICE_X84Y39.CLK Trck 0.245 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
- cmp_tdc2_clks_rsts_mgment/rst_in_synch_1
+ SLICE_X76Y81.AQ Tcko 0.447 cmp_carrier_csr/carrier_csr_ctrl_reserved_int<6>
+ cmp_carrier_csr/carrier_csr_ctrl_reserved_int_0
+ SLICE_X76Y79.D4 net (fanout=2) 0.463 cmp_carrier_csr/carrier_csr_ctrl_reserved_int<0>
+ SLICE_X76Y79.DMUX Tilo 0.261 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
+ cmp_tdc1_clks_rsts_mgment/rst_n_i_inv1
+ SLICE_X56Y138.SR net (fanout=1) 4.481 cmp_tdc1_clks_rsts_mgment/rst_n_i_inv
+ SLICE_X56Y138.CLK Trck 0.245 cmp_tdc1_clks_rsts_mgment/rst_in_synch<1>
+ cmp_tdc1_clks_rsts_mgment/rst_in_synch_1
------------------------------------------------- ---------------------------
- Total 5.505ns (0.936ns logic, 4.569ns route)
- (17.0% logic, 83.0% route)
+ Total 5.897ns (0.953ns logic, 4.944ns route)
+ (16.2% logic, 83.8% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2_clks_rsts_mgment/rst_in_synch_0 (SLICE_X84Y39.SR), 2 paths
+Paths for end point cmp_tdc1_clks_rsts_mgment/rst_in_synch_0 (SLICE_X56Y138.SR), 2 paths
--------------------------------------------------------------------------------
-Slack (setup paths): 193.883ns (requirement - (data path - clock path skew + uncertainty))
+Slack (setup paths): 192.572ns (requirement - (data path - clock path skew + uncertainty))
Source: rst_n_sys (FF)
- Destination: cmp_tdc2_clks_rsts_mgment/rst_in_synch_0 (FF)
+ Destination: cmp_tdc1_clks_rsts_mgment/rst_in_synch_0 (FF)
Requirement: 200.000ns
- Data Path Delay: 6.117ns (Levels of Logic = 1)
+ Data Path Delay: 7.428ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path at Slow Process Corner: rst_n_sys to cmp_tdc2_clks_rsts_mgment/rst_in_synch_0
+ Maximum Data Path at Slow Process Corner: rst_n_sys to cmp_tdc1_clks_rsts_mgment/rst_in_synch_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X69Y98.CQ Tcko 0.391 rst_n_sys
+ SLICE_X68Y98.CQ Tcko 0.447 rst_n_sys
rst_n_sys
- SLICE_X64Y92.D3 net (fanout=89) 1.120 rst_n_sys
- SLICE_X64Y92.D Tilo 0.203 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
- cmp_tdc2_clks_rsts_mgment/rst_n_i_inv1
- SLICE_X84Y39.SR net (fanout=1) 4.175 cmp_tdc2_clks_rsts_mgment/rst_n_i_inv
- SLICE_X84Y39.CLK Trck 0.228 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
- cmp_tdc2_clks_rsts_mgment/rst_in_synch_0
+ SLICE_X76Y79.D5 net (fanout=91) 2.011 rst_n_sys
+ SLICE_X76Y79.DMUX Tilo 0.261 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
+ cmp_tdc1_clks_rsts_mgment/rst_n_i_inv1
+ SLICE_X56Y138.SR net (fanout=1) 4.481 cmp_tdc1_clks_rsts_mgment/rst_n_i_inv
+ SLICE_X56Y138.CLK Trck 0.228 cmp_tdc1_clks_rsts_mgment/rst_in_synch<1>
+ cmp_tdc1_clks_rsts_mgment/rst_in_synch_0
------------------------------------------------- ---------------------------
- Total 6.117ns (0.822ns logic, 5.295ns route)
- (13.4% logic, 86.6% route)
+ Total 7.428ns (0.936ns logic, 6.492ns route)
+ (12.6% logic, 87.4% route)
--------------------------------------------------------------------------------
-Slack (setup paths): 194.512ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_carrier_csr/carrier_csr_ctrl_reserved_int_1 (FF)
- Destination: cmp_tdc2_clks_rsts_mgment/rst_in_synch_0 (FF)
+Slack (setup paths): 194.120ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_carrier_csr/carrier_csr_ctrl_reserved_int_0 (FF)
+ Destination: cmp_tdc1_clks_rsts_mgment/rst_in_synch_0 (FF)
Requirement: 200.000ns
- Data Path Delay: 5.488ns (Levels of Logic = 1)
+ Data Path Delay: 5.880ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_carrier_csr/carrier_csr_ctrl_reserved_int_1 to cmp_tdc2_clks_rsts_mgment/rst_in_synch_0
+ Maximum Data Path at Slow Process Corner: cmp_carrier_csr/carrier_csr_ctrl_reserved_int_0 to cmp_tdc1_clks_rsts_mgment/rst_in_synch_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X64Y92.CMUX Tshcko 0.488 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
- cmp_carrier_csr/carrier_csr_ctrl_reserved_int_1
- SLICE_X64Y92.D5 net (fanout=2) 0.394 cmp_carrier_csr/carrier_csr_ctrl_reserved_int<1>
- SLICE_X64Y92.D Tilo 0.203 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
- cmp_tdc2_clks_rsts_mgment/rst_n_i_inv1
- SLICE_X84Y39.SR net (fanout=1) 4.175 cmp_tdc2_clks_rsts_mgment/rst_n_i_inv
- SLICE_X84Y39.CLK Trck 0.228 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
- cmp_tdc2_clks_rsts_mgment/rst_in_synch_0
+ SLICE_X76Y81.AQ Tcko 0.447 cmp_carrier_csr/carrier_csr_ctrl_reserved_int<6>
+ cmp_carrier_csr/carrier_csr_ctrl_reserved_int_0
+ SLICE_X76Y79.D4 net (fanout=2) 0.463 cmp_carrier_csr/carrier_csr_ctrl_reserved_int<0>
+ SLICE_X76Y79.DMUX Tilo 0.261 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
+ cmp_tdc1_clks_rsts_mgment/rst_n_i_inv1
+ SLICE_X56Y138.SR net (fanout=1) 4.481 cmp_tdc1_clks_rsts_mgment/rst_n_i_inv
+ SLICE_X56Y138.CLK Trck 0.228 cmp_tdc1_clks_rsts_mgment/rst_in_synch<1>
+ cmp_tdc1_clks_rsts_mgment/rst_in_synch_0
------------------------------------------------- ---------------------------
- Total 5.488ns (0.919ns logic, 4.569ns route)
- (16.7% logic, 83.3% route)
+ Total 5.880ns (0.936ns logic, 4.944ns route)
+ (15.9% logic, 84.1% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_rsts_mgment/rst_in_synch_1 (SLICE_X59Y151.SR), 2 paths
+Paths for end point cmp_tdc2_clks_rsts_mgment/rst_in_synch_1 (SLICE_X82Y41.SR), 2 paths
--------------------------------------------------------------------------------
-Slack (setup paths): 194.013ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_carrier_csr/carrier_csr_ctrl_reserved_int_0 (FF)
- Destination: cmp_tdc1_clks_rsts_mgment/rst_in_synch_1 (FF)
+Slack (setup paths): 193.743ns (requirement - (data path - clock path skew + uncertainty))
+ Source: rst_n_sys (FF)
+ Destination: cmp_tdc2_clks_rsts_mgment/rst_in_synch_1 (FF)
Requirement: 200.000ns
- Data Path Delay: 5.987ns (Levels of Logic = 1)
+ Data Path Delay: 6.257ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_carrier_csr/carrier_csr_ctrl_reserved_int_0 to cmp_tdc1_clks_rsts_mgment/rst_in_synch_1
+ Maximum Data Path at Slow Process Corner: rst_n_sys to cmp_tdc2_clks_rsts_mgment/rst_in_synch_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X54Y94.AQ Tcko 0.408 cmp_carrier_csr/carrier_csr_ctrl_reserved_int<6>
- cmp_carrier_csr/carrier_csr_ctrl_reserved_int_0
- SLICE_X64Y92.D2 net (fanout=2) 1.159 cmp_carrier_csr/carrier_csr_ctrl_reserved_int<0>
- SLICE_X64Y92.DMUX Tilo 0.261 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
- cmp_tdc1_clks_rsts_mgment/rst_n_i_inv1
- SLICE_X59Y151.SR net (fanout=1) 3.855 cmp_tdc1_clks_rsts_mgment/rst_n_i_inv
- SLICE_X59Y151.CLK Trck 0.304 cmp_tdc1_clks_rsts_mgment/rst_in_synch<1>
- cmp_tdc1_clks_rsts_mgment/rst_in_synch_1
+ SLICE_X68Y98.CQ Tcko 0.447 rst_n_sys
+ rst_n_sys
+ SLICE_X76Y79.D5 net (fanout=91) 2.011 rst_n_sys
+ SLICE_X76Y79.D Tilo 0.203 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
+ cmp_tdc2_clks_rsts_mgment/rst_n_i_inv1
+ SLICE_X82Y41.SR net (fanout=1) 3.311 cmp_tdc2_clks_rsts_mgment/rst_n_i_inv
+ SLICE_X82Y41.CLK Trck 0.285 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
+ cmp_tdc2_clks_rsts_mgment/rst_in_synch_1
------------------------------------------------- ---------------------------
- Total 5.987ns (0.973ns logic, 5.014ns route)
- (16.3% logic, 83.7% route)
+ Total 6.257ns (0.935ns logic, 5.322ns route)
+ (14.9% logic, 85.1% route)
--------------------------------------------------------------------------------
-Slack (setup paths): 194.069ns (requirement - (data path - clock path skew + uncertainty))
- Source: rst_n_sys (FF)
- Destination: cmp_tdc1_clks_rsts_mgment/rst_in_synch_1 (FF)
+Slack (setup paths): 195.384ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_carrier_csr/carrier_csr_ctrl_reserved_int_1 (FF)
+ Destination: cmp_tdc2_clks_rsts_mgment/rst_in_synch_1 (FF)
Requirement: 200.000ns
- Data Path Delay: 5.931ns (Levels of Logic = 1)
+ Data Path Delay: 4.616ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path at Slow Process Corner: rst_n_sys to cmp_tdc1_clks_rsts_mgment/rst_in_synch_1
+ Maximum Data Path at Slow Process Corner: cmp_carrier_csr/carrier_csr_ctrl_reserved_int_1 to cmp_tdc2_clks_rsts_mgment/rst_in_synch_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X69Y98.CQ Tcko 0.391 rst_n_sys
- rst_n_sys
- SLICE_X64Y92.D3 net (fanout=89) 1.120 rst_n_sys
- SLICE_X64Y92.DMUX Tilo 0.261 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
- cmp_tdc1_clks_rsts_mgment/rst_n_i_inv1
- SLICE_X59Y151.SR net (fanout=1) 3.855 cmp_tdc1_clks_rsts_mgment/rst_n_i_inv
- SLICE_X59Y151.CLK Trck 0.304 cmp_tdc1_clks_rsts_mgment/rst_in_synch<1>
- cmp_tdc1_clks_rsts_mgment/rst_in_synch_1
+ SLICE_X76Y79.CMUX Tshcko 0.488 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
+ cmp_carrier_csr/carrier_csr_ctrl_reserved_int_1
+ SLICE_X76Y79.D3 net (fanout=2) 0.329 cmp_carrier_csr/carrier_csr_ctrl_reserved_int<1>
+ SLICE_X76Y79.D Tilo 0.203 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
+ cmp_tdc2_clks_rsts_mgment/rst_n_i_inv1
+ SLICE_X82Y41.SR net (fanout=1) 3.311 cmp_tdc2_clks_rsts_mgment/rst_n_i_inv
+ SLICE_X82Y41.CLK Trck 0.285 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
+ cmp_tdc2_clks_rsts_mgment/rst_in_synch_1
------------------------------------------------- ---------------------------
- Total 5.931ns (0.956ns logic, 4.975ns route)
- (16.1% logic, 83.9% route)
+ Total 4.616ns (0.976ns logic, 3.640ns route)
+ (21.1% logic, 78.9% route)
--------------------------------------------------------------------------------
Hold Paths: ts_ignore_xclock4 = MAXDELAY FROM TIMEGRP "clk_62m5_sys" TO TIMEGRP "clk_20m_vcxo_i" 200 ns DATAPATHONLY;
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2_clks_rsts_mgment/rst_in_synch_0 (SLICE_X84Y39.SR), 2 paths
+Paths for end point cmp_tdc2_clks_rsts_mgment/rst_in_synch_0 (SLICE_X82Y41.SR), 2 paths
--------------------------------------------------------------------------------
-Slack (hold path): 3.270ns (requirement - (clock path skew + uncertainty - data path))
+Slack (hold path): 2.708ns (requirement - (clock path skew + uncertainty - data path))
Source: cmp_carrier_csr/carrier_csr_ctrl_reserved_int_1 (FF)
Destination: cmp_tdc2_clks_rsts_mgment/rst_in_synch_0 (FF)
Requirement: 0.000ns
- Data Path Delay: 3.270ns (Levels of Logic = 1)
+ Data Path Delay: 2.708ns (Levels of Logic = 1)
Positive Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
@@ -577,23 +577,23 @@ Slack (hold path): 3.270ns (requirement - (clock path skew + uncertainty -
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X64Y92.CMUX Tshcko 0.266 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
+ SLICE_X76Y79.CMUX Tshcko 0.266 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
cmp_carrier_csr/carrier_csr_ctrl_reserved_int_1
- SLICE_X64Y92.D5 net (fanout=2) 0.210 cmp_carrier_csr/carrier_csr_ctrl_reserved_int<1>
- SLICE_X64Y92.D Tilo 0.156 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
+ SLICE_X76Y79.D3 net (fanout=2) 0.165 cmp_carrier_csr/carrier_csr_ctrl_reserved_int<1>
+ SLICE_X76Y79.D Tilo 0.156 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
cmp_tdc2_clks_rsts_mgment/rst_n_i_inv1
- SLICE_X84Y39.SR net (fanout=1) 2.533 cmp_tdc2_clks_rsts_mgment/rst_n_i_inv
- SLICE_X84Y39.CLK Tremck (-Th) -0.105 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
+ SLICE_X82Y41.SR net (fanout=1) 1.966 cmp_tdc2_clks_rsts_mgment/rst_n_i_inv
+ SLICE_X82Y41.CLK Tremck (-Th) -0.155 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
cmp_tdc2_clks_rsts_mgment/rst_in_synch_0
------------------------------------------------- ---------------------------
- Total 3.270ns (0.527ns logic, 2.743ns route)
- (16.1% logic, 83.9% route)
+ Total 2.708ns (0.577ns logic, 2.131ns route)
+ (21.3% logic, 78.7% route)
--------------------------------------------------------------------------------
-Slack (hold path): 3.717ns (requirement - (clock path skew + uncertainty - data path))
+Slack (hold path): 3.709ns (requirement - (clock path skew + uncertainty - data path))
Source: rst_n_sys (FF)
Destination: cmp_tdc2_clks_rsts_mgment/rst_in_synch_0 (FF)
Requirement: 0.000ns
- Data Path Delay: 3.717ns (Levels of Logic = 1)
+ Data Path Delay: 3.709ns (Levels of Logic = 1)
Positive Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
@@ -603,26 +603,26 @@ Slack (hold path): 3.717ns (requirement - (clock path skew + uncertainty -
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X69Y98.CQ Tcko 0.198 rst_n_sys
+ SLICE_X68Y98.CQ Tcko 0.234 rst_n_sys
rst_n_sys
- SLICE_X64Y92.D3 net (fanout=89) 0.725 rst_n_sys
- SLICE_X64Y92.D Tilo 0.156 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
+ SLICE_X76Y79.D5 net (fanout=91) 1.198 rst_n_sys
+ SLICE_X76Y79.D Tilo 0.156 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
cmp_tdc2_clks_rsts_mgment/rst_n_i_inv1
- SLICE_X84Y39.SR net (fanout=1) 2.533 cmp_tdc2_clks_rsts_mgment/rst_n_i_inv
- SLICE_X84Y39.CLK Tremck (-Th) -0.105 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
+ SLICE_X82Y41.SR net (fanout=1) 1.966 cmp_tdc2_clks_rsts_mgment/rst_n_i_inv
+ SLICE_X82Y41.CLK Tremck (-Th) -0.155 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
cmp_tdc2_clks_rsts_mgment/rst_in_synch_0
------------------------------------------------- ---------------------------
- Total 3.717ns (0.459ns logic, 3.258ns route)
- (12.3% logic, 87.7% route)
+ Total 3.709ns (0.545ns logic, 3.164ns route)
+ (14.7% logic, 85.3% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2_clks_rsts_mgment/rst_in_synch_1 (SLICE_X84Y39.SR), 2 paths
+Paths for end point cmp_tdc2_clks_rsts_mgment/rst_in_synch_1 (SLICE_X82Y41.SR), 2 paths
--------------------------------------------------------------------------------
-Slack (hold path): 3.318ns (requirement - (clock path skew + uncertainty - data path))
+Slack (hold path): 2.729ns (requirement - (clock path skew + uncertainty - data path))
Source: cmp_carrier_csr/carrier_csr_ctrl_reserved_int_1 (FF)
Destination: cmp_tdc2_clks_rsts_mgment/rst_in_synch_1 (FF)
Requirement: 0.000ns
- Data Path Delay: 3.318ns (Levels of Logic = 1)
+ Data Path Delay: 2.729ns (Levels of Logic = 1)
Positive Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
@@ -632,26 +632,26 @@ Slack (hold path): 3.318ns (requirement - (clock path skew + uncertainty -
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X64Y92.CMUX Tshcko 0.266 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
+ SLICE_X76Y79.CMUX Tshcko 0.266 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
cmp_carrier_csr/carrier_csr_ctrl_reserved_int_1
- SLICE_X64Y92.D5 net (fanout=2) 0.210 cmp_carrier_csr/carrier_csr_ctrl_reserved_int<1>
- SLICE_X64Y92.D Tilo 0.156 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
+ SLICE_X76Y79.D3 net (fanout=2) 0.165 cmp_carrier_csr/carrier_csr_ctrl_reserved_int<1>
+ SLICE_X76Y79.D Tilo 0.156 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
cmp_tdc2_clks_rsts_mgment/rst_n_i_inv1
- SLICE_X84Y39.SR net (fanout=1) 2.533 cmp_tdc2_clks_rsts_mgment/rst_n_i_inv
- SLICE_X84Y39.CLK Tremck (-Th) -0.153 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
+ SLICE_X82Y41.SR net (fanout=1) 1.966 cmp_tdc2_clks_rsts_mgment/rst_n_i_inv
+ SLICE_X82Y41.CLK Tremck (-Th) -0.176 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
cmp_tdc2_clks_rsts_mgment/rst_in_synch_1
------------------------------------------------- ---------------------------
- Total 3.318ns (0.575ns logic, 2.743ns route)
- (17.3% logic, 82.7% route)
+ Total 2.729ns (0.598ns logic, 2.131ns route)
+ (21.9% logic, 78.1% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2_clks_rsts_mgment/rst_in_synch_1 (SLICE_X84Y39.SR), 2 paths
+Paths for end point cmp_tdc2_clks_rsts_mgment/rst_in_synch_1 (SLICE_X82Y41.SR), 2 paths
--------------------------------------------------------------------------------
-Slack (hold path): 3.765ns (requirement - (clock path skew + uncertainty - data path))
+Slack (hold path): 3.730ns (requirement - (clock path skew + uncertainty - data path))
Source: rst_n_sys (FF)
Destination: cmp_tdc2_clks_rsts_mgment/rst_in_synch_1 (FF)
Requirement: 0.000ns
- Data Path Delay: 3.765ns (Levels of Logic = 1)
+ Data Path Delay: 3.730ns (Levels of Logic = 1)
Positive Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
@@ -661,26 +661,26 @@ Slack (hold path): 3.765ns (requirement - (clock path skew + uncertainty -
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X69Y98.CQ Tcko 0.198 rst_n_sys
+ SLICE_X68Y98.CQ Tcko 0.234 rst_n_sys
rst_n_sys
- SLICE_X64Y92.D3 net (fanout=89) 0.725 rst_n_sys
- SLICE_X64Y92.D Tilo 0.156 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
+ SLICE_X76Y79.D5 net (fanout=91) 1.198 rst_n_sys
+ SLICE_X76Y79.D Tilo 0.156 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
cmp_tdc2_clks_rsts_mgment/rst_n_i_inv1
- SLICE_X84Y39.SR net (fanout=1) 2.533 cmp_tdc2_clks_rsts_mgment/rst_n_i_inv
- SLICE_X84Y39.CLK Tremck (-Th) -0.153 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
+ SLICE_X82Y41.SR net (fanout=1) 1.966 cmp_tdc2_clks_rsts_mgment/rst_n_i_inv
+ SLICE_X82Y41.CLK Tremck (-Th) -0.176 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
cmp_tdc2_clks_rsts_mgment/rst_in_synch_1
------------------------------------------------- ---------------------------
- Total 3.765ns (0.507ns logic, 3.258ns route)
- (13.5% logic, 86.5% route)
+ Total 3.730ns (0.566ns logic, 3.164ns route)
+ (15.2% logic, 84.8% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_rsts_mgment/rst_in_synch_0 (SLICE_X59Y151.SR), 2 paths
+Paths for end point cmp_tdc1_clks_rsts_mgment/rst_in_synch_0 (SLICE_X56Y138.SR), 2 paths
--------------------------------------------------------------------------------
-Slack (hold path): 3.480ns (requirement - (clock path skew + uncertainty - data path))
+Slack (hold path): 3.436ns (requirement - (clock path skew + uncertainty - data path))
Source: cmp_carrier_csr/carrier_csr_ctrl_reserved_int_0 (FF)
Destination: cmp_tdc1_clks_rsts_mgment/rst_in_synch_0 (FF)
Requirement: 0.000ns
- Data Path Delay: 3.480ns (Levels of Logic = 1)
+ Data Path Delay: 3.436ns (Levels of Logic = 1)
Positive Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
@@ -690,26 +690,26 @@ Slack (hold path): 3.480ns (requirement - (clock path skew + uncertainty -
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X54Y94.AQ Tcko 0.200 cmp_carrier_csr/carrier_csr_ctrl_reserved_int<6>
+ SLICE_X76Y81.AQ Tcko 0.234 cmp_carrier_csr/carrier_csr_ctrl_reserved_int<6>
cmp_carrier_csr/carrier_csr_ctrl_reserved_int_0
- SLICE_X64Y92.D2 net (fanout=2) 0.672 cmp_carrier_csr/carrier_csr_ctrl_reserved_int<0>
- SLICE_X64Y92.DMUX Tilo 0.191 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
+ SLICE_X76Y79.D4 net (fanout=2) 0.224 cmp_carrier_csr/carrier_csr_ctrl_reserved_int<0>
+ SLICE_X76Y79.DMUX Tilo 0.191 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
cmp_tdc1_clks_rsts_mgment/rst_n_i_inv1
- SLICE_X59Y151.SR net (fanout=1) 2.238 cmp_tdc1_clks_rsts_mgment/rst_n_i_inv
- SLICE_X59Y151.CLK Tremck (-Th) -0.179 cmp_tdc1_clks_rsts_mgment/rst_in_synch<1>
+ SLICE_X56Y138.SR net (fanout=1) 2.682 cmp_tdc1_clks_rsts_mgment/rst_n_i_inv
+ SLICE_X56Y138.CLK Tremck (-Th) -0.105 cmp_tdc1_clks_rsts_mgment/rst_in_synch<1>
cmp_tdc1_clks_rsts_mgment/rst_in_synch_0
------------------------------------------------- ---------------------------
- Total 3.480ns (0.570ns logic, 2.910ns route)
- (16.4% logic, 83.6% route)
+ Total 3.436ns (0.530ns logic, 2.906ns route)
+ (15.4% logic, 84.6% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_rsts_mgment/rst_in_synch_0 (SLICE_X59Y151.SR), 2 paths
+Paths for end point cmp_tdc1_clks_rsts_mgment/rst_in_synch_0 (SLICE_X56Y138.SR), 2 paths
--------------------------------------------------------------------------------
-Slack (hold path): 3.531ns (requirement - (clock path skew + uncertainty - data path))
+Slack (hold path): 4.410ns (requirement - (clock path skew + uncertainty - data path))
Source: rst_n_sys (FF)
Destination: cmp_tdc1_clks_rsts_mgment/rst_in_synch_0 (FF)
Requirement: 0.000ns
- Data Path Delay: 3.531ns (Levels of Logic = 1)
+ Data Path Delay: 4.410ns (Levels of Logic = 1)
Positive Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
@@ -719,17 +719,17 @@ Slack (hold path): 3.531ns (requirement - (clock path skew + uncertainty -
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X69Y98.CQ Tcko 0.198 rst_n_sys
+ SLICE_X68Y98.CQ Tcko 0.234 rst_n_sys
rst_n_sys
- SLICE_X64Y92.D3 net (fanout=89) 0.725 rst_n_sys
- SLICE_X64Y92.DMUX Tilo 0.191 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
+ SLICE_X76Y79.D5 net (fanout=91) 1.198 rst_n_sys
+ SLICE_X76Y79.DMUX Tilo 0.191 cmp_carrier_csr/carrier_csr_ctrl_dac_clr_n_int
cmp_tdc1_clks_rsts_mgment/rst_n_i_inv1
- SLICE_X59Y151.SR net (fanout=1) 2.238 cmp_tdc1_clks_rsts_mgment/rst_n_i_inv
- SLICE_X59Y151.CLK Tremck (-Th) -0.179 cmp_tdc1_clks_rsts_mgment/rst_in_synch<1>
+ SLICE_X56Y138.SR net (fanout=1) 2.682 cmp_tdc1_clks_rsts_mgment/rst_n_i_inv
+ SLICE_X56Y138.CLK Tremck (-Th) -0.105 cmp_tdc1_clks_rsts_mgment/rst_in_synch<1>
cmp_tdc1_clks_rsts_mgment/rst_in_synch_0
------------------------------------------------- ---------------------------
- Total 3.531ns (0.568ns logic, 2.963ns route)
- (16.1% logic, 83.9% route)
+ Total 4.410ns (0.530ns logic, 3.880ns route)
+ (12.0% logic, 88.0% route)
--------------------------------------------------------------------------------
================================================================================
@@ -739,17 +739,17 @@ For more information, see Period Analysis in the Timing Closure User Guide (UG61
1303 paths analyzed, 495 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is 8.849ns.
+ Minimum period is 12.221ns.
--------------------------------------------------------------------------------
Paths for end point cmp_tdc2_clks_rsts_mgment/pll_sdi_o (OLOGIC_X28Y1.D1), 209 paths
--------------------------------------------------------------------------------
-Slack (setup path): 41.151ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2_clks_rsts_mgment/dac_bit_index_1 (FF)
+Slack (setup path): 37.779ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2_clks_rsts_mgment/pll_byte_index_1 (FF)
Destination: cmp_tdc2_clks_rsts_mgment/pll_sdi_o (FF)
Requirement: 50.000ns
- Data Path Delay: 9.262ns (Levels of Logic = 4)
- Clock Path Skew: 0.448ns (1.172 - 0.724)
+ Data Path Delay: 12.595ns (Levels of Logic = 4)
+ Clock Path Skew: 0.409ns (0.656 - 0.247)
Source Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
Clock Uncertainty: 0.035ns
@@ -760,38 +760,40 @@ Slack (setup path): 41.151ns (requirement - (data path - clock path skew + u
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2_clks_rsts_mgment/dac_bit_index_1 to cmp_tdc2_clks_rsts_mgment/pll_sdi_o
+ Maximum Data Path at Slow Process Corner: cmp_tdc2_clks_rsts_mgment/pll_byte_index_1 to cmp_tdc2_clks_rsts_mgment/pll_sdi_o
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X73Y29.AMUX Tshcko 0.461 cmp_tdc2_clks_rsts_mgment/dac_bit_index<3>
- cmp_tdc2_clks_rsts_mgment/dac_bit_index_1
- SLICE_X67Y34.A4 net (fanout=11) 1.471 cmp_tdc2_clks_rsts_mgment/dac_bit_index<1>
- SLICE_X67Y34.A Tilo 0.259 cmp_tdc2_clks_rsts_mgment/dac_word<15>
- cmp_tdc2_clks_rsts_mgment/Mmux_dac_bit_being_sent_10
- SLICE_X71Y29.A3 net (fanout=1) 1.264 cmp_tdc2_clks_rsts_mgment/Mmux_dac_bit_being_sent_10
- SLICE_X71Y29.A Tilo 0.259 cmp_tdc2_clks_rsts_mgment/Mmux_dac_bit_being_sent_9
- cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent12
- SLICE_X88Y20.C1 net (fanout=1) 1.822 cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent11
- SLICE_X88Y20.C Tilo 0.205 cmp_tdc2_clks_rsts_mgment/bit_being_sent
- cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent15
- SLICE_X88Y20.D5 net (fanout=1) 0.204 cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent14
- SLICE_X88Y20.D Tilo 0.205 cmp_tdc2_clks_rsts_mgment/bit_being_sent
+ SLICE_X81Y9.DMUX Tshcko 0.461 cmp_tdc2_clks_rsts_mgment/pll_byte_index<3>
+ cmp_tdc2_clks_rsts_mgment/pll_byte_index_1
+ SLICE_X98Y6.D2 net (fanout=23) 3.088 cmp_tdc2_clks_rsts_mgment/pll_byte_index<1>
+ SLICE_X98Y6.CMUX Topdc 0.338 cmp_tdc2_clks_rsts_mgment/_n0515<6>
+ cmp_tdc2_clks_rsts_mgment_Mram__n0515111_F
+ cmp_tdc2_clks_rsts_mgment_Mram__n0515111
+ SLICE_X76Y6.D5 net (fanout=1) 2.567 cmp_tdc2_clks_rsts_mgment/_n0515<6>
+ SLICE_X76Y6.DMUX Tilo 0.261 cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent1
+ cmp_tdc2_clks_rsts_mgment/Mmux_pll_word_being_sent<1>11
+ SLICE_X76Y7.D2 net (fanout=1) 0.818 cmp_tdc2_clks_rsts_mgment/pll_word_being_sent<1>
+ SLICE_X76Y7.CMUX Topdc 0.368 cmp_tdc2_clks_rsts_mgment/pll_word_being_sent<4>
+ cmp_tdc2_clks_rsts_mgment/Mmux_pll_bit_being_sent_7
+ cmp_tdc2_clks_rsts_mgment/Mmux_pll_bit_being_sent_5_f7
+ SLICE_X77Y9.D3 net (fanout=1) 0.554 cmp_tdc2_clks_rsts_mgment/Mmux_pll_bit_being_sent_5_f7
+ SLICE_X77Y9.D Tilo 0.259 cmp_tdc2_clks_rsts_mgment/bit_being_sent
cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent16
- OLOGIC_X28Y1.D1 net (fanout=1) 2.309 cmp_tdc2_clks_rsts_mgment/bit_being_sent
+ OLOGIC_X28Y1.D1 net (fanout=1) 3.078 cmp_tdc2_clks_rsts_mgment/bit_being_sent
OLOGIC_X28Y1.CLK0 Todck 0.803 cmp_tdc2_clks_rsts_mgment/pll_sdi_o
cmp_tdc2_clks_rsts_mgment/pll_sdi_o
------------------------------------------------- ---------------------------
- Total 9.262ns (2.192ns logic, 7.070ns route)
- (23.7% logic, 76.3% route)
+ Total 12.595ns (2.490ns logic, 10.105ns route)
+ (19.8% logic, 80.2% route)
--------------------------------------------------------------------------------
-Slack (setup path): 41.168ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2_clks_rsts_mgment/dac_bit_index_0 (FF)
+Slack (setup path): 37.919ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2_clks_rsts_mgment/pll_byte_index_4 (FF)
Destination: cmp_tdc2_clks_rsts_mgment/pll_sdi_o (FF)
Requirement: 50.000ns
- Data Path Delay: 9.245ns (Levels of Logic = 4)
- Clock Path Skew: 0.448ns (1.172 - 0.724)
+ Data Path Delay: 12.455ns (Levels of Logic = 4)
+ Clock Path Skew: 0.409ns (0.656 - 0.247)
Source Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
Clock Uncertainty: 0.035ns
@@ -802,38 +804,40 @@ Slack (setup path): 41.168ns (requirement - (data path - clock path skew + u
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2_clks_rsts_mgment/dac_bit_index_0 to cmp_tdc2_clks_rsts_mgment/pll_sdi_o
+ Maximum Data Path at Slow Process Corner: cmp_tdc2_clks_rsts_mgment/pll_byte_index_4 to cmp_tdc2_clks_rsts_mgment/pll_sdi_o
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X73Y29.AQ Tcko 0.391 cmp_tdc2_clks_rsts_mgment/dac_bit_index<3>
- cmp_tdc2_clks_rsts_mgment/dac_bit_index_0
- SLICE_X67Y34.A1 net (fanout=11) 1.524 cmp_tdc2_clks_rsts_mgment/dac_bit_index<0>
- SLICE_X67Y34.A Tilo 0.259 cmp_tdc2_clks_rsts_mgment/dac_word<15>
- cmp_tdc2_clks_rsts_mgment/Mmux_dac_bit_being_sent_10
- SLICE_X71Y29.A3 net (fanout=1) 1.264 cmp_tdc2_clks_rsts_mgment/Mmux_dac_bit_being_sent_10
- SLICE_X71Y29.A Tilo 0.259 cmp_tdc2_clks_rsts_mgment/Mmux_dac_bit_being_sent_9
- cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent12
- SLICE_X88Y20.C1 net (fanout=1) 1.822 cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent11
- SLICE_X88Y20.C Tilo 0.205 cmp_tdc2_clks_rsts_mgment/bit_being_sent
- cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent15
- SLICE_X88Y20.D5 net (fanout=1) 0.204 cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent14
- SLICE_X88Y20.D Tilo 0.205 cmp_tdc2_clks_rsts_mgment/bit_being_sent
+ SLICE_X80Y9.BQ Tcko 0.447 cmp_tdc2_clks_rsts_mgment/pll_byte_index<6>
+ cmp_tdc2_clks_rsts_mgment/pll_byte_index_4
+ SLICE_X98Y6.D4 net (fanout=24) 2.962 cmp_tdc2_clks_rsts_mgment/pll_byte_index<4>
+ SLICE_X98Y6.CMUX Topdc 0.338 cmp_tdc2_clks_rsts_mgment/_n0515<6>
+ cmp_tdc2_clks_rsts_mgment_Mram__n0515111_F
+ cmp_tdc2_clks_rsts_mgment_Mram__n0515111
+ SLICE_X76Y6.D5 net (fanout=1) 2.567 cmp_tdc2_clks_rsts_mgment/_n0515<6>
+ SLICE_X76Y6.DMUX Tilo 0.261 cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent1
+ cmp_tdc2_clks_rsts_mgment/Mmux_pll_word_being_sent<1>11
+ SLICE_X76Y7.D2 net (fanout=1) 0.818 cmp_tdc2_clks_rsts_mgment/pll_word_being_sent<1>
+ SLICE_X76Y7.CMUX Topdc 0.368 cmp_tdc2_clks_rsts_mgment/pll_word_being_sent<4>
+ cmp_tdc2_clks_rsts_mgment/Mmux_pll_bit_being_sent_7
+ cmp_tdc2_clks_rsts_mgment/Mmux_pll_bit_being_sent_5_f7
+ SLICE_X77Y9.D3 net (fanout=1) 0.554 cmp_tdc2_clks_rsts_mgment/Mmux_pll_bit_being_sent_5_f7
+ SLICE_X77Y9.D Tilo 0.259 cmp_tdc2_clks_rsts_mgment/bit_being_sent
cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent16
- OLOGIC_X28Y1.D1 net (fanout=1) 2.309 cmp_tdc2_clks_rsts_mgment/bit_being_sent
+ OLOGIC_X28Y1.D1 net (fanout=1) 3.078 cmp_tdc2_clks_rsts_mgment/bit_being_sent
OLOGIC_X28Y1.CLK0 Todck 0.803 cmp_tdc2_clks_rsts_mgment/pll_sdi_o
cmp_tdc2_clks_rsts_mgment/pll_sdi_o
------------------------------------------------- ---------------------------
- Total 9.245ns (2.122ns logic, 7.123ns route)
- (23.0% logic, 77.0% route)
+ Total 12.455ns (2.476ns logic, 9.979ns route)
+ (19.9% logic, 80.1% route)
--------------------------------------------------------------------------------
-Slack (setup path): 41.481ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2_clks_rsts_mgment/dac_word_6 (FF)
+Slack (setup path): 38.031ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2_clks_rsts_mgment/pll_byte_index_1 (FF)
Destination: cmp_tdc2_clks_rsts_mgment/pll_sdi_o (FF)
Requirement: 50.000ns
- Data Path Delay: 8.835ns (Levels of Logic = 4)
- Clock Path Skew: 0.351ns (1.172 - 0.821)
+ Data Path Delay: 12.343ns (Levels of Logic = 4)
+ Clock Path Skew: 0.409ns (0.656 - 0.247)
Source Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
Clock Uncertainty: 0.035ns
@@ -844,40 +848,42 @@ Slack (setup path): 41.481ns (requirement - (data path - clock path skew + u
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2_clks_rsts_mgment/dac_word_6 to cmp_tdc2_clks_rsts_mgment/pll_sdi_o
+ Maximum Data Path at Slow Process Corner: cmp_tdc2_clks_rsts_mgment/pll_byte_index_1 to cmp_tdc2_clks_rsts_mgment/pll_sdi_o
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X61Y34.CMUX Tshcko 0.461 cmp_tdc2_clks_rsts_mgment/dac_word<11>
- cmp_tdc2_clks_rsts_mgment/dac_word_6
- SLICE_X67Y34.A2 net (fanout=1) 1.044 cmp_tdc2_clks_rsts_mgment/dac_word<6>
- SLICE_X67Y34.A Tilo 0.259 cmp_tdc2_clks_rsts_mgment/dac_word<15>
- cmp_tdc2_clks_rsts_mgment/Mmux_dac_bit_being_sent_10
- SLICE_X71Y29.A3 net (fanout=1) 1.264 cmp_tdc2_clks_rsts_mgment/Mmux_dac_bit_being_sent_10
- SLICE_X71Y29.A Tilo 0.259 cmp_tdc2_clks_rsts_mgment/Mmux_dac_bit_being_sent_9
- cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent12
- SLICE_X88Y20.C1 net (fanout=1) 1.822 cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent11
- SLICE_X88Y20.C Tilo 0.205 cmp_tdc2_clks_rsts_mgment/bit_being_sent
- cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent15
- SLICE_X88Y20.D5 net (fanout=1) 0.204 cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent14
- SLICE_X88Y20.D Tilo 0.205 cmp_tdc2_clks_rsts_mgment/bit_being_sent
+ SLICE_X81Y9.DMUX Tshcko 0.461 cmp_tdc2_clks_rsts_mgment/pll_byte_index<3>
+ cmp_tdc2_clks_rsts_mgment/pll_byte_index_1
+ SLICE_X98Y6.C5 net (fanout=23) 2.831 cmp_tdc2_clks_rsts_mgment/pll_byte_index<1>
+ SLICE_X98Y6.CMUX Tilo 0.343 cmp_tdc2_clks_rsts_mgment/_n0515<6>
+ cmp_tdc2_clks_rsts_mgment_Mram__n0515111_G
+ cmp_tdc2_clks_rsts_mgment_Mram__n0515111
+ SLICE_X76Y6.D5 net (fanout=1) 2.567 cmp_tdc2_clks_rsts_mgment/_n0515<6>
+ SLICE_X76Y6.DMUX Tilo 0.261 cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent1
+ cmp_tdc2_clks_rsts_mgment/Mmux_pll_word_being_sent<1>11
+ SLICE_X76Y7.D2 net (fanout=1) 0.818 cmp_tdc2_clks_rsts_mgment/pll_word_being_sent<1>
+ SLICE_X76Y7.CMUX Topdc 0.368 cmp_tdc2_clks_rsts_mgment/pll_word_being_sent<4>
+ cmp_tdc2_clks_rsts_mgment/Mmux_pll_bit_being_sent_7
+ cmp_tdc2_clks_rsts_mgment/Mmux_pll_bit_being_sent_5_f7
+ SLICE_X77Y9.D3 net (fanout=1) 0.554 cmp_tdc2_clks_rsts_mgment/Mmux_pll_bit_being_sent_5_f7
+ SLICE_X77Y9.D Tilo 0.259 cmp_tdc2_clks_rsts_mgment/bit_being_sent
cmp_tdc2_clks_rsts_mgment/Mmux_bit_being_sent16
- OLOGIC_X28Y1.D1 net (fanout=1) 2.309 cmp_tdc2_clks_rsts_mgment/bit_being_sent
+ OLOGIC_X28Y1.D1 net (fanout=1) 3.078 cmp_tdc2_clks_rsts_mgment/bit_being_sent
OLOGIC_X28Y1.CLK0 Todck 0.803 cmp_tdc2_clks_rsts_mgment/pll_sdi_o
cmp_tdc2_clks_rsts_mgment/pll_sdi_o
------------------------------------------------- ---------------------------
- Total 8.835ns (2.192ns logic, 6.643ns route)
- (24.8% logic, 75.2% route)
+ Total 12.343ns (2.495ns logic, 9.848ns route)
+ (20.2% logic, 79.8% route)
--------------------------------------------------------------------------------
Paths for end point cmp_tdc1_clks_rsts_mgment/pll_sdi_o (OLOGIC_X11Y175.D1), 213 paths
--------------------------------------------------------------------------------
-Slack (setup path): 41.402ns (requirement - (data path - clock path skew + uncertainty))
+Slack (setup path): 39.375ns (requirement - (data path - clock path skew + uncertainty))
Source: cmp_tdc1_clks_rsts_mgment/dac_bit_index_1 (FF)
Destination: cmp_tdc1_clks_rsts_mgment/pll_sdi_o (FF)
Requirement: 50.000ns
- Data Path Delay: 9.290ns (Levels of Logic = 4)
+ Data Path Delay: 11.317ns (Levels of Logic = 4)
Clock Path Skew: 0.727ns (1.358 - 0.631)
Source Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
@@ -893,34 +899,34 @@ Slack (setup path): 41.402ns (requirement - (data path - clock path skew + u
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X76Y152.AMUX Tshcko 0.488 cmp_tdc1_clks_rsts_mgment/dac_bit_index<3>
+ SLICE_X85Y151.AMUX Tshcko 0.461 cmp_tdc1_clks_rsts_mgment/dac_bit_index<3>
cmp_tdc1_clks_rsts_mgment/dac_bit_index_1
- SLICE_X85Y152.D5 net (fanout=11) 0.920 cmp_tdc1_clks_rsts_mgment/dac_bit_index<1>
- SLICE_X85Y152.D Tilo 0.259 cmp_tdc1_clks_rsts_mgment/Mmux_dac_bit_being_sent_10
+ SLICE_X87Y145.A3 net (fanout=11) 0.939 cmp_tdc1_clks_rsts_mgment/dac_bit_index<1>
+ SLICE_X87Y145.A Tilo 0.259 cmp_tdc1_clks_rsts_mgment/dac_word<7>
cmp_tdc1_clks_rsts_mgment/Mmux_dac_bit_being_sent_10
- SLICE_X80Y152.A3 net (fanout=1) 0.532 cmp_tdc1_clks_rsts_mgment/Mmux_dac_bit_being_sent_10
- SLICE_X80Y152.A Tilo 0.203 cmp_tdc1_clks_rsts_mgment/Mmux_dac_bit_being_sent_9
+ SLICE_X84Y151.C3 net (fanout=1) 1.101 cmp_tdc1_clks_rsts_mgment/Mmux_dac_bit_being_sent_10
+ SLICE_X84Y151.C Tilo 0.204 cmp_tdc1/tdc_core/data_formatting_block/acam_fine_timestamp<15>
cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent12
- SLICE_X49Y153.C3 net (fanout=1) 1.803 cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent11
- SLICE_X49Y153.C Tilo 0.259 cmp_tdc1_clks_rsts_mgment/bit_being_sent
+ SLICE_X67Y171.C3 net (fanout=1) 2.457 cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent11
+ SLICE_X67Y171.C Tilo 0.259 cmp_tdc1_clks_rsts_mgment/bit_being_sent
cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent15
- SLICE_X49Y153.D5 net (fanout=1) 0.209 cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent14
- SLICE_X49Y153.D Tilo 0.259 cmp_tdc1_clks_rsts_mgment/bit_being_sent
+ SLICE_X67Y171.D5 net (fanout=1) 0.209 cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent14
+ SLICE_X67Y171.D Tilo 0.259 cmp_tdc1_clks_rsts_mgment/bit_being_sent
cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent16
- OLOGIC_X11Y175.D1 net (fanout=1) 3.555 cmp_tdc1_clks_rsts_mgment/bit_being_sent
+ OLOGIC_X11Y175.D1 net (fanout=1) 4.366 cmp_tdc1_clks_rsts_mgment/bit_being_sent
OLOGIC_X11Y175.CLK0 Todck 0.803 cmp_tdc1_clks_rsts_mgment/pll_sdi_o
cmp_tdc1_clks_rsts_mgment/pll_sdi_o
------------------------------------------------- ---------------------------
- Total 9.290ns (2.271ns logic, 7.019ns route)
- (24.4% logic, 75.6% route)
+ Total 11.317ns (2.245ns logic, 9.072ns route)
+ (19.8% logic, 80.2% route)
--------------------------------------------------------------------------------
-Slack (setup path): 41.404ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1_clks_rsts_mgment/pll_byte_index_0 (FF)
+Slack (setup path): 39.573ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1_clks_rsts_mgment/dac_bit_index_0 (FF)
Destination: cmp_tdc1_clks_rsts_mgment/pll_sdi_o (FF)
Requirement: 50.000ns
- Data Path Delay: 9.109ns (Levels of Logic = 4)
- Clock Path Skew: 0.548ns (1.358 - 0.810)
+ Data Path Delay: 11.119ns (Levels of Logic = 4)
+ Clock Path Skew: 0.727ns (1.358 - 0.631)
Source Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
Clock Uncertainty: 0.035ns
@@ -931,40 +937,38 @@ Slack (setup path): 41.404ns (requirement - (data path - clock path skew + u
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_rsts_mgment/pll_byte_index_0 to cmp_tdc1_clks_rsts_mgment/pll_sdi_o
+ Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_rsts_mgment/dac_bit_index_0 to cmp_tdc1_clks_rsts_mgment/pll_sdi_o
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X46Y152.AQ Tcko 0.408 cmp_tdc1_clks_rsts_mgment/pll_byte_index<3>
- cmp_tdc1_clks_rsts_mgment/pll_byte_index_0
- SLICE_X42Y152.D2 net (fanout=20) 1.311 cmp_tdc1_clks_rsts_mgment/pll_byte_index<0>
- SLICE_X42Y152.CMUX Topdc 0.338 cmp_tdc1_clks_rsts_mgment/_n0515<6>
- cmp_tdc1_clks_rsts_mgment_Mram__n0515111_F
- cmp_tdc1_clks_rsts_mgment_Mram__n0515111
- SLICE_X45Y153.D3 net (fanout=1) 0.915 cmp_tdc1_clks_rsts_mgment/_n0515<6>
- SLICE_X45Y153.DMUX Tilo 0.313 cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent1
- cmp_tdc1_clks_rsts_mgment/Mmux_pll_word_being_sent<1>11
- SLICE_X44Y153.D4 net (fanout=1) 0.268 cmp_tdc1_clks_rsts_mgment/pll_word_being_sent<1>
- SLICE_X44Y153.CMUX Topdc 0.368 cmp_tdc1_clks_rsts_mgment/pll_word_being_sent<4>
- cmp_tdc1_clks_rsts_mgment/Mmux_pll_bit_being_sent_7
- cmp_tdc1_clks_rsts_mgment/Mmux_pll_bit_being_sent_5_f7
- SLICE_X49Y153.D3 net (fanout=1) 0.571 cmp_tdc1_clks_rsts_mgment/Mmux_pll_bit_being_sent_5_f7
- SLICE_X49Y153.D Tilo 0.259 cmp_tdc1_clks_rsts_mgment/bit_being_sent
+ SLICE_X85Y151.AQ Tcko 0.391 cmp_tdc1_clks_rsts_mgment/dac_bit_index<3>
+ cmp_tdc1_clks_rsts_mgment/dac_bit_index_0
+ SLICE_X87Y145.A5 net (fanout=11) 0.811 cmp_tdc1_clks_rsts_mgment/dac_bit_index<0>
+ SLICE_X87Y145.A Tilo 0.259 cmp_tdc1_clks_rsts_mgment/dac_word<7>
+ cmp_tdc1_clks_rsts_mgment/Mmux_dac_bit_being_sent_10
+ SLICE_X84Y151.C3 net (fanout=1) 1.101 cmp_tdc1_clks_rsts_mgment/Mmux_dac_bit_being_sent_10
+ SLICE_X84Y151.C Tilo 0.204 cmp_tdc1/tdc_core/data_formatting_block/acam_fine_timestamp<15>
+ cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent12
+ SLICE_X67Y171.C3 net (fanout=1) 2.457 cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent11
+ SLICE_X67Y171.C Tilo 0.259 cmp_tdc1_clks_rsts_mgment/bit_being_sent
+ cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent15
+ SLICE_X67Y171.D5 net (fanout=1) 0.209 cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent14
+ SLICE_X67Y171.D Tilo 0.259 cmp_tdc1_clks_rsts_mgment/bit_being_sent
cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent16
- OLOGIC_X11Y175.D1 net (fanout=1) 3.555 cmp_tdc1_clks_rsts_mgment/bit_being_sent
+ OLOGIC_X11Y175.D1 net (fanout=1) 4.366 cmp_tdc1_clks_rsts_mgment/bit_being_sent
OLOGIC_X11Y175.CLK0 Todck 0.803 cmp_tdc1_clks_rsts_mgment/pll_sdi_o
cmp_tdc1_clks_rsts_mgment/pll_sdi_o
------------------------------------------------- ---------------------------
- Total 9.109ns (2.489ns logic, 6.620ns route)
- (27.3% logic, 72.7% route)
+ Total 11.119ns (2.175ns logic, 8.944ns route)
+ (19.6% logic, 80.4% route)
--------------------------------------------------------------------------------
-Slack (setup path): 41.418ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1_clks_rsts_mgment/dac_bit_index_1 (FF)
+Slack (setup path): 39.768ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1_clks_rsts_mgment/dac_word_7 (FF)
Destination: cmp_tdc1_clks_rsts_mgment/pll_sdi_o (FF)
Requirement: 50.000ns
- Data Path Delay: 9.274ns (Levels of Logic = 4)
- Clock Path Skew: 0.727ns (1.358 - 0.631)
+ Data Path Delay: 10.913ns (Levels of Logic = 4)
+ Clock Path Skew: 0.716ns (1.358 - 0.642)
Source Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
Clock Uncertainty: 0.035ns
@@ -975,41 +979,41 @@ Slack (setup path): 41.418ns (requirement - (data path - clock path skew + u
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_rsts_mgment/dac_bit_index_1 to cmp_tdc1_clks_rsts_mgment/pll_sdi_o
+ Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_rsts_mgment/dac_word_7 to cmp_tdc1_clks_rsts_mgment/pll_sdi_o
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X76Y152.AMUX Tshcko 0.488 cmp_tdc1_clks_rsts_mgment/dac_bit_index<3>
- cmp_tdc1_clks_rsts_mgment/dac_bit_index_1
- SLICE_X80Y150.D2 net (fanout=11) 1.007 cmp_tdc1_clks_rsts_mgment/dac_bit_index<1>
- SLICE_X80Y150.D Tilo 0.203 cmp_tdc1_clks_rsts_mgment/send_dac_word_p_synch<2>
- cmp_tdc1_clks_rsts_mgment/Mmux_dac_bit_being_sent_11
- SLICE_X80Y152.A4 net (fanout=1) 0.485 cmp_tdc1_clks_rsts_mgment/Mmux_dac_bit_being_sent_11
- SLICE_X80Y152.A Tilo 0.203 cmp_tdc1_clks_rsts_mgment/Mmux_dac_bit_being_sent_9
+ SLICE_X87Y145.DQ Tcko 0.391 cmp_tdc1_clks_rsts_mgment/dac_word<7>
+ cmp_tdc1_clks_rsts_mgment/dac_word_7
+ SLICE_X87Y145.A2 net (fanout=1) 0.605 cmp_tdc1_clks_rsts_mgment/dac_word<7>
+ SLICE_X87Y145.A Tilo 0.259 cmp_tdc1_clks_rsts_mgment/dac_word<7>
+ cmp_tdc1_clks_rsts_mgment/Mmux_dac_bit_being_sent_10
+ SLICE_X84Y151.C3 net (fanout=1) 1.101 cmp_tdc1_clks_rsts_mgment/Mmux_dac_bit_being_sent_10
+ SLICE_X84Y151.C Tilo 0.204 cmp_tdc1/tdc_core/data_formatting_block/acam_fine_timestamp<15>
cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent12
- SLICE_X49Y153.C3 net (fanout=1) 1.803 cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent11
- SLICE_X49Y153.C Tilo 0.259 cmp_tdc1_clks_rsts_mgment/bit_being_sent
+ SLICE_X67Y171.C3 net (fanout=1) 2.457 cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent11
+ SLICE_X67Y171.C Tilo 0.259 cmp_tdc1_clks_rsts_mgment/bit_being_sent
cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent15
- SLICE_X49Y153.D5 net (fanout=1) 0.209 cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent14
- SLICE_X49Y153.D Tilo 0.259 cmp_tdc1_clks_rsts_mgment/bit_being_sent
+ SLICE_X67Y171.D5 net (fanout=1) 0.209 cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent14
+ SLICE_X67Y171.D Tilo 0.259 cmp_tdc1_clks_rsts_mgment/bit_being_sent
cmp_tdc1_clks_rsts_mgment/Mmux_bit_being_sent16
- OLOGIC_X11Y175.D1 net (fanout=1) 3.555 cmp_tdc1_clks_rsts_mgment/bit_being_sent
+ OLOGIC_X11Y175.D1 net (fanout=1) 4.366 cmp_tdc1_clks_rsts_mgment/bit_being_sent
OLOGIC_X11Y175.CLK0 Todck 0.803 cmp_tdc1_clks_rsts_mgment/pll_sdi_o
cmp_tdc1_clks_rsts_mgment/pll_sdi_o
------------------------------------------------- ---------------------------
- Total 9.274ns (2.215ns logic, 7.059ns route)
- (23.9% logic, 76.1% route)
+ Total 10.913ns (2.175ns logic, 8.738ns route)
+ (19.9% logic, 80.1% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2_clks_rsts_mgment/pll_status_synch_0 (ILOGIC_X34Y2.SR), 1 path
+Paths for end point cmp_tdc1_clks_rsts_mgment/pll_dac_sync_n_o (OLOGIC_X13Y174.SR), 1 path
--------------------------------------------------------------------------------
-Slack (setup path): 43.530ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2_clks_rsts_mgment/rst_in_synch_1 (FF)
- Destination: cmp_tdc2_clks_rsts_mgment/pll_status_synch_0 (FF)
+Slack (setup path): 42.953ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1_clks_rsts_mgment/rst_in_synch_1 (FF)
+ Destination: cmp_tdc1_clks_rsts_mgment/pll_dac_sync_n_o (FF)
Requirement: 50.000ns
- Data Path Delay: 6.989ns (Levels of Logic = 0)
- Clock Path Skew: 0.554ns (1.185 - 0.631)
+ Data Path Delay: 7.559ns (Levels of Logic = 0)
+ Clock Path Skew: 0.547ns (1.355 - 0.808)
Source Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
Clock Uncertainty: 0.035ns
@@ -1020,32 +1024,32 @@ Slack (setup path): 43.530ns (requirement - (data path - clock path skew + u
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2_clks_rsts_mgment/rst_in_synch_1 to cmp_tdc2_clks_rsts_mgment/pll_status_synch_0
+ Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_rsts_mgment/rst_in_synch_1 to cmp_tdc1_clks_rsts_mgment/pll_dac_sync_n_o
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X84Y39.BQ Tcko 0.447 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
- cmp_tdc2_clks_rsts_mgment/rst_in_synch_1
- ILOGIC_X34Y2.SR net (fanout=22) 5.808 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
- ILOGIC_X34Y2.CLK0 Tisrck 0.734 tdc2_pll_status_i_IBUF
- cmp_tdc2_clks_rsts_mgment/pll_status_synch_0
+ SLICE_X56Y138.BQ Tcko 0.447 cmp_tdc1_clks_rsts_mgment/rst_in_synch<1>
+ cmp_tdc1_clks_rsts_mgment/rst_in_synch_1
+ OLOGIC_X13Y174.SR net (fanout=22) 6.417 cmp_tdc1_clks_rsts_mgment/rst_in_synch<1>
+ OLOGIC_X13Y174.CLK0 Tosrck 0.695 cmp_tdc1_clks_rsts_mgment/pll_dac_sync_n_o
+ cmp_tdc1_clks_rsts_mgment/pll_dac_sync_n_o
------------------------------------------------- ---------------------------
- Total 6.989ns (1.181ns logic, 5.808ns route)
- (16.9% logic, 83.1% route)
+ Total 7.559ns (1.142ns logic, 6.417ns route)
+ (15.1% logic, 84.9% route)
--------------------------------------------------------------------------------
Hold Paths: TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_20m_vcxo_i" 50 ns HIGH 50%;
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2_clks_rsts_mgment/rst (SLICE_X87Y39.SR), 1 path
+Paths for end point cmp_tdc2_clks_rsts_mgment/rst (SLICE_X85Y41.SR), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.427ns (requirement - (clock path skew + uncertainty - data path))
+Slack (hold path): 0.391ns (requirement - (clock path skew + uncertainty - data path))
Source: cmp_tdc2_clks_rsts_mgment/rst_in_synch_1 (FF)
Destination: cmp_tdc2_clks_rsts_mgment/rst (FF)
Requirement: 0.000ns
- Data Path Delay: 0.431ns (Levels of Logic = 0)
- Clock Path Skew: 0.004ns (0.067 - 0.063)
+ Data Path Delay: 0.395ns (Levels of Logic = 0)
+ Clock Path Skew: 0.004ns (0.069 - 0.065)
Source Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
Clock Uncertainty: 0.000ns
@@ -1054,70 +1058,69 @@ Slack (hold path): 0.427ns (requirement - (clock path skew + uncertainty -
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X84Y39.BQ Tcko 0.234 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
+ SLICE_X82Y41.BQ Tcko 0.200 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
cmp_tdc2_clks_rsts_mgment/rst_in_synch_1
- SLICE_X87Y39.SR net (fanout=22) 0.148 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
- SLICE_X87Y39.CLK Tcksr (-Th) -0.049 cmp_tdc2_clks_rsts_mgment/rst
+ SLICE_X85Y41.SR net (fanout=22) 0.146 cmp_tdc2_clks_rsts_mgment/rst_in_synch<1>
+ SLICE_X85Y41.CLK Tcksr (-Th) -0.049 cmp_tdc2_clks_rsts_mgment/rst
cmp_tdc2_clks_rsts_mgment/rst
------------------------------------------------- ---------------------------
- Total 0.431ns (0.283ns logic, 0.148ns route)
- (65.7% logic, 34.3% route)
+ Total 0.395ns (0.249ns logic, 0.146ns route)
+ (63.0% logic, 37.0% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2_clks_rsts_mgment/config_st_FSM_FFd1 (SLICE_X86Y20.CX), 1 path
+Paths for end point cmp_tdc2_clks_rsts_mgment/sclk (SLICE_X98Y9.A6), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.433ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc2_clks_rsts_mgment/config_st_FSM_FFd1 (FF)
- Destination: cmp_tdc2_clks_rsts_mgment/config_st_FSM_FFd1 (FF)
+Slack (hold path): 0.424ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc2_clks_rsts_mgment/sclk (FF)
+ Destination: cmp_tdc2_clks_rsts_mgment/sclk (FF)
Requirement: 0.000ns
- Data Path Delay: 0.433ns (Levels of Logic = 1)
+ Data Path Delay: 0.424ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc2_clks_rsts_mgment/config_st_FSM_FFd1 to cmp_tdc2_clks_rsts_mgment/config_st_FSM_FFd1
+ Minimum Data Path at Fast Process Corner: cmp_tdc2_clks_rsts_mgment/sclk to cmp_tdc2_clks_rsts_mgment/sclk
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X86Y20.CQ Tcko 0.200 cmp_tdc2_clks_rsts_mgment/config_st_FSM_FFd1
- cmp_tdc2_clks_rsts_mgment/config_st_FSM_FFd1
- SLICE_X86Y20.CX net (fanout=20) 0.127 cmp_tdc2_clks_rsts_mgment/config_st_FSM_FFd1
- SLICE_X86Y20.CLK Tckdi (-Th) -0.106 cmp_tdc2_clks_rsts_mgment/config_st_FSM_FFd1
- cmp_tdc2_clks_rsts_mgment/config_st_FSM_FFd1-In3
- cmp_tdc2_clks_rsts_mgment/config_st_FSM_FFd1
+ SLICE_X98Y9.AQ Tcko 0.200 cmp_tdc2_clks_rsts_mgment/sclk
+ cmp_tdc2_clks_rsts_mgment/sclk
+ SLICE_X98Y9.A6 net (fanout=10) 0.034 cmp_tdc2_clks_rsts_mgment/sclk
+ SLICE_X98Y9.CLK Tah (-Th) -0.190 cmp_tdc2_clks_rsts_mgment/sclk
+ cmp_tdc2_clks_rsts_mgment/sclk_INV_31_o1_INV_0
+ cmp_tdc2_clks_rsts_mgment/sclk
------------------------------------------------- ---------------------------
- Total 0.433ns (0.306ns logic, 0.127ns route)
- (70.7% logic, 29.3% route)
+ Total 0.424ns (0.390ns logic, 0.034ns route)
+ (92.0% logic, 8.0% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_rsts_mgment/config_st_FSM_FFd1 (SLICE_X50Y153.A6), 1 path
+Paths for end point cmp_tdc1_clks_rsts_mgment/rst (SLICE_X55Y138.SR), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.438ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc1_clks_rsts_mgment/config_st_FSM_FFd1 (FF)
- Destination: cmp_tdc1_clks_rsts_mgment/config_st_FSM_FFd1 (FF)
+Slack (hold path): 0.425ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc1_clks_rsts_mgment/rst_in_synch_1 (FF)
+ Destination: cmp_tdc1_clks_rsts_mgment/rst (FF)
Requirement: 0.000ns
- Data Path Delay: 0.438ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
+ Data Path Delay: 0.429ns (Levels of Logic = 0)
+ Clock Path Skew: 0.004ns (0.071 - 0.067)
Source Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_rsts_mgment/config_st_FSM_FFd1 to cmp_tdc1_clks_rsts_mgment/config_st_FSM_FFd1
+ Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_rsts_mgment/rst_in_synch_1 to cmp_tdc1_clks_rsts_mgment/rst
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X50Y153.AQ Tcko 0.200 cmp_tdc1_clks_rsts_mgment/config_st_FSM_FFd2
- cmp_tdc1_clks_rsts_mgment/config_st_FSM_FFd1
- SLICE_X50Y153.A6 net (fanout=21) 0.048 cmp_tdc1_clks_rsts_mgment/config_st_FSM_FFd1
- SLICE_X50Y153.CLK Tah (-Th) -0.190 cmp_tdc1_clks_rsts_mgment/config_st_FSM_FFd2
- cmp_tdc1_clks_rsts_mgment/config_st_FSM_FFd1-In3
- cmp_tdc1_clks_rsts_mgment/config_st_FSM_FFd1
+ SLICE_X56Y138.BQ Tcko 0.234 cmp_tdc1_clks_rsts_mgment/rst_in_synch<1>
+ cmp_tdc1_clks_rsts_mgment/rst_in_synch_1
+ SLICE_X55Y138.SR net (fanout=22) 0.146 cmp_tdc1_clks_rsts_mgment/rst_in_synch<1>
+ SLICE_X55Y138.CLK Tcksr (-Th) -0.049 cmp_tdc1_clks_rsts_mgment/rst
+ cmp_tdc1_clks_rsts_mgment/rst
------------------------------------------------- ---------------------------
- Total 0.438ns (0.390ns logic, 0.048ns route)
- (89.0% logic, 11.0% route)
+ Total 0.429ns (0.283ns logic, 0.146ns route)
+ (66.0% logic, 34.0% route)
--------------------------------------------------------------------------------
@@ -1165,7 +1168,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
Logical resource: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X2Y78.CLKA
+ Location pin: RAMB16_X3Y78.CLKA
Clock network: tdc1_clk_125m
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
@@ -1173,7 +1176,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKB)
Physical resource: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
Logical resource: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
- Location pin: RAMB16_X2Y78.CLKB
+ Location pin: RAMB16_X3Y78.CLKB
Clock network: tdc1_clk_125m
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
@@ -1181,7 +1184,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
Logical resource: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X1Y78.CLKA
+ Location pin: RAMB16_X2Y78.CLKA
Clock network: tdc1_clk_125m
--------------------------------------------------------------------------------
@@ -1190,19 +1193,19 @@ Timing constraint: TS_tdc1_125m_clk_p_i = PERIOD TIMEGRP "tdc1_125m_clk_p_i" 8
ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
- 542428 paths analyzed, 8661 endpoints analyzed, 1 failing endpoint
- 1 timing error detected. (1 setup error, 0 hold errors, 0 component switching limit errors)
- Minimum period is 8.007ns.
+ 542428 paths analyzed, 8651 endpoints analyzed, 0 failing endpoints
+ 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
+ Minimum period is 7.749ns.
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAMB16_X1Y78.DIA15), 14898 paths
+Paths for end point cmp_tdc1/tdc_core/reg_control_block/tdc_config_wb_dat_o_3 (SLICE_X104Y159.B4), 608 paths
--------------------------------------------------------------------------------
-Slack (setup path): -0.007ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_0 (FF)
- Destination: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+Slack (setup path): 0.251ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1/tdc_core/reg_control_block/reg_adr_pipe0_1_1 (FF)
+ Destination: cmp_tdc1/tdc_core/reg_control_block/tdc_config_wb_dat_o_3 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.860ns (Levels of Logic = 8)
- Clock Path Skew: -0.112ns (0.796 - 0.908)
+ Data Path Delay: 7.706ns (Levels of Logic = 7)
+ Clock Path Skew: -0.008ns (0.249 - 0.257)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1213,54 +1216,45 @@ Slack (setup path): -0.007ns (requirement - (data path - clock path skew + u
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_0 to cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/reg_control_block/reg_adr_pipe0_1_1 to cmp_tdc1/tdc_core/reg_control_block/tdc_config_wb_dat_o_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X51Y170.BQ Tcko 0.391 cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset<5>
- cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_0
- SLICE_X49Y169.B5 net (fanout=2) 0.408 cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset<0>
- SLICE_X49Y169.B Tilo 0.259 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<5>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd
- SLICE_X48Y169.B4 net (fanout=2) 0.437 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd
- SLICE_X48Y169.DQ Tad_logic 0.980 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<3>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_lut<0>1
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_2
- cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<3>_rt
- SLICE_X50Y168.D5 net (fanout=1) 0.582 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<3>
- SLICE_X50Y168.COUT Topcyd 0.260 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<3>
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<3>_INV_0
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<3>
- SLICE_X50Y169.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<3>
- SLICE_X50Y169.AMUX Tcina 0.177 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<7>
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<7>
- SLICE_X52Y167.A4 net (fanout=2) 0.750 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<10>
- SLICE_X52Y167.COUT Topcya 0.379 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<10>_rt
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- SLICE_X52Y168.CIN net (fanout=1) 0.082 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- SLICE_X52Y168.COUT Tbyp 0.076 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- SLICE_X52Y169.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- SLICE_X52Y169.COUT Tbyp 0.076 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.DMUX Tcind 0.302 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- RAMB16_X1Y78.DIA15 net (fanout=1) 2.392 cmp_tdc1/tdc_core/circ_buff_class_data_wr<57>
- RAMB16_X1Y78.CLKA Trdck_DIA 0.300 cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X102Y156.AQ Tcko 0.408 cmp_tdc1/tdc_core/reg_control_block/reg_adr_pipe0_1_2
+ cmp_tdc1/tdc_core/reg_control_block/reg_adr_pipe0_1_1
+ SLICE_X102Y154.B4 net (fanout=1) 0.766 cmp_tdc1/tdc_core/reg_control_block/reg_adr_pipe0_1_1
+ SLICE_X102Y154.B Tilo 0.205 cmp_tdc1/tdc_core/reg_control_block/acam_config_10<11>
+ cmp_tdc1/tdc_core/reg_control_block/_n0589<7>_SW0
+ SLICE_X102Y154.A5 net (fanout=1) 0.169 N338
+ SLICE_X102Y154.A Tilo 0.205 cmp_tdc1/tdc_core/reg_control_block/acam_config_10<11>
+ cmp_tdc1/tdc_core/reg_control_block/_n0589<7>
+ SLICE_X109Y153.C3 net (fanout=35) 1.639 cmp_tdc1/tdc_core/reg_control_block/_n0589
+ SLICE_X109Y153.C Tilo 0.259 cmp_tdc1/tdc_core/reg_control_block/acam_config_5<10>
+ cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out1101241
+ SLICE_X105Y154.A6 net (fanout=32) 0.612 cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out110124
+ SLICE_X105Y154.A Tilo 0.259 cmp_tdc1/tdc_core/reg_control_block/acam_config_8<31>
+ cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28614
+ SLICE_X106Y158.A1 net (fanout=1) 1.551 cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28613
+ SLICE_X106Y158.A Tilo 0.205 cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out2869
+ cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28618
+ SLICE_X104Y159.C1 net (fanout=1) 0.666 cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28617
+ SLICE_X104Y159.C Tilo 0.204 cmp_tdc1/tdc_core/reg_control_block/tdc_config_wb_dat_o<3>
+ cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28619
+ SLICE_X104Y159.B4 net (fanout=1) 0.269 cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28618
+ SLICE_X104Y159.CLK Tas 0.289 cmp_tdc1/tdc_core/reg_control_block/tdc_config_wb_dat_o<3>
+ cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28620
+ cmp_tdc1/tdc_core/reg_control_block/tdc_config_wb_dat_o_3
------------------------------------------------- ---------------------------
- Total 7.860ns (3.200ns logic, 4.660ns route)
- (40.7% logic, 59.3% route)
+ Total 7.706ns (2.034ns logic, 5.672ns route)
+ (26.4% logic, 73.6% route)
--------------------------------------------------------------------------------
-Slack (setup path): -0.001ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6 (FF)
- Destination: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+Slack (setup path): 0.294ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1/tdc_core/reg_control_block/reg_adr_pipe0_2_2 (FF)
+ Destination: cmp_tdc1/tdc_core/reg_control_block/tdc_config_wb_dat_o_3 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.857ns (Levels of Logic = 7)
- Clock Path Skew: -0.109ns (0.796 - 0.905)
+ Data Path Delay: 7.664ns (Levels of Logic = 6)
+ Clock Path Skew: -0.007ns (0.249 - 0.256)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1271,50 +1265,42 @@ Slack (setup path): -0.001ns (requirement - (data path - clock path skew + u
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6 to cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/reg_control_block/reg_adr_pipe0_2_2 to cmp_tdc1/tdc_core/reg_control_block/tdc_config_wb_dat_o_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X49Y169.DMUX Tshcko 0.461 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<5>
- cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6
- SLICE_X48Y170.C1 net (fanout=6) 0.635 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<6>
- SLICE_X48Y170.CMUX Tilo 0.261 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd6
- SLICE_X48Y170.DX net (fanout=2) 0.585 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd6
- SLICE_X48Y170.COUT Tdxcy 0.087 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_6
- SLICE_X48Y171.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>7
- SLICE_X48Y171.AQ Tito_logic 0.611 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<11>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_10
- cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<8>_rt
- SLICE_X50Y170.A5 net (fanout=1) 0.547 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<8>
- SLICE_X50Y170.COUT Topcya 0.395 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<8>_INV_0
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- SLICE_X50Y171.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- SLICE_X50Y171.AMUX Tcina 0.177 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
- SLICE_X52Y169.A3 net (fanout=2) 0.716 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<18>
- SLICE_X52Y169.COUT Topcya 0.379 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<18>_rt
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.DMUX Tcind 0.302 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- RAMB16_X1Y78.DIA15 net (fanout=1) 2.392 cmp_tdc1/tdc_core/circ_buff_class_data_wr<57>
- RAMB16_X1Y78.CLKA Trdck_DIA 0.300 cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X101Y156.CQ Tcko 0.391 cmp_tdc1/tdc_core/reg_control_block/reg_adr_pipe0_2_2
+ cmp_tdc1/tdc_core/reg_control_block/reg_adr_pipe0_2_2
+ SLICE_X102Y154.A1 net (fanout=5) 1.115 cmp_tdc1/tdc_core/reg_control_block/reg_adr_pipe0_2_2
+ SLICE_X102Y154.A Tilo 0.205 cmp_tdc1/tdc_core/reg_control_block/acam_config_10<11>
+ cmp_tdc1/tdc_core/reg_control_block/_n0589<7>
+ SLICE_X109Y153.C3 net (fanout=35) 1.639 cmp_tdc1/tdc_core/reg_control_block/_n0589
+ SLICE_X109Y153.C Tilo 0.259 cmp_tdc1/tdc_core/reg_control_block/acam_config_5<10>
+ cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out1101241
+ SLICE_X105Y154.A6 net (fanout=32) 0.612 cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out110124
+ SLICE_X105Y154.A Tilo 0.259 cmp_tdc1/tdc_core/reg_control_block/acam_config_8<31>
+ cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28614
+ SLICE_X106Y158.A1 net (fanout=1) 1.551 cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28613
+ SLICE_X106Y158.A Tilo 0.205 cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out2869
+ cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28618
+ SLICE_X104Y159.C1 net (fanout=1) 0.666 cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28617
+ SLICE_X104Y159.C Tilo 0.204 cmp_tdc1/tdc_core/reg_control_block/tdc_config_wb_dat_o<3>
+ cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28619
+ SLICE_X104Y159.B4 net (fanout=1) 0.269 cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28618
+ SLICE_X104Y159.CLK Tas 0.289 cmp_tdc1/tdc_core/reg_control_block/tdc_config_wb_dat_o<3>
+ cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28620
+ cmp_tdc1/tdc_core/reg_control_block/tdc_config_wb_dat_o_3
------------------------------------------------- ---------------------------
- Total 7.857ns (2.973ns logic, 4.884ns route)
- (37.8% logic, 62.2% route)
+ Total 7.664ns (1.812ns logic, 5.852ns route)
+ (23.6% logic, 76.4% route)
--------------------------------------------------------------------------------
-Slack (setup path): -0.001ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6 (FF)
- Destination: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+Slack (setup path): 0.325ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1/tdc_core/reg_control_block/reg_adr_pipe0_1_1 (FF)
+ Destination: cmp_tdc1/tdc_core/reg_control_block/tdc_config_wb_dat_o_3 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.857ns (Levels of Logic = 7)
- Clock Path Skew: -0.109ns (0.796 - 0.905)
+ Data Path Delay: 7.632ns (Levels of Logic = 7)
+ Clock Path Skew: -0.008ns (0.249 - 0.257)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1325,53 +1311,48 @@ Slack (setup path): -0.001ns (requirement - (data path - clock path skew + u
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6 to cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/reg_control_block/reg_adr_pipe0_1_1 to cmp_tdc1/tdc_core/reg_control_block/tdc_config_wb_dat_o_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X49Y169.DMUX Tshcko 0.461 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<5>
- cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6
- SLICE_X48Y170.C1 net (fanout=6) 0.635 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<6>
- SLICE_X48Y170.CMUX Tilo 0.261 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd6
- SLICE_X48Y170.DX net (fanout=2) 0.585 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd6
- SLICE_X48Y170.COUT Tdxcy 0.087 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_6
- SLICE_X48Y171.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>7
- SLICE_X48Y171.DQ Tito_logic 0.711 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<11>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_10
- cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<11>_rt
- SLICE_X50Y170.D5 net (fanout=1) 0.582 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<11>
- SLICE_X50Y170.COUT Topcyd 0.260 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<11>_INV_0
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- SLICE_X50Y171.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- SLICE_X50Y171.AMUX Tcina 0.177 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
- SLICE_X52Y169.A3 net (fanout=2) 0.716 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<18>
- SLICE_X52Y169.COUT Topcya 0.379 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<18>_rt
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.DMUX Tcind 0.302 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- RAMB16_X1Y78.DIA15 net (fanout=1) 2.392 cmp_tdc1/tdc_core/circ_buff_class_data_wr<57>
- RAMB16_X1Y78.CLKA Trdck_DIA 0.300 cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X102Y156.AQ Tcko 0.408 cmp_tdc1/tdc_core/reg_control_block/reg_adr_pipe0_1_2
+ cmp_tdc1/tdc_core/reg_control_block/reg_adr_pipe0_1_1
+ SLICE_X102Y154.B4 net (fanout=1) 0.766 cmp_tdc1/tdc_core/reg_control_block/reg_adr_pipe0_1_1
+ SLICE_X102Y154.B Tilo 0.205 cmp_tdc1/tdc_core/reg_control_block/acam_config_10<11>
+ cmp_tdc1/tdc_core/reg_control_block/_n0589<7>_SW0
+ SLICE_X102Y154.A5 net (fanout=1) 0.169 N338
+ SLICE_X102Y154.A Tilo 0.205 cmp_tdc1/tdc_core/reg_control_block/acam_config_10<11>
+ cmp_tdc1/tdc_core/reg_control_block/_n0589<7>
+ SLICE_X106Y153.C6 net (fanout=35) 1.674 cmp_tdc1/tdc_core/reg_control_block/_n0589
+ SLICE_X106Y153.C Tilo 0.205 cmp_tdc1/tdc_core/reg_control_block/acam_config_6<15>
+ cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out1101221
+ SLICE_X105Y154.A4 net (fanout=32) 0.557 cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out110122
+ SLICE_X105Y154.A Tilo 0.259 cmp_tdc1/tdc_core/reg_control_block/acam_config_8<31>
+ cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28614
+ SLICE_X106Y158.A1 net (fanout=1) 1.551 cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28613
+ SLICE_X106Y158.A Tilo 0.205 cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out2869
+ cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28618
+ SLICE_X104Y159.C1 net (fanout=1) 0.666 cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28617
+ SLICE_X104Y159.C Tilo 0.204 cmp_tdc1/tdc_core/reg_control_block/tdc_config_wb_dat_o<3>
+ cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28619
+ SLICE_X104Y159.B4 net (fanout=1) 0.269 cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28618
+ SLICE_X104Y159.CLK Tas 0.289 cmp_tdc1/tdc_core/reg_control_block/tdc_config_wb_dat_o<3>
+ cmp_tdc1/tdc_core/reg_control_block/Mmux_dat_out28620
+ cmp_tdc1/tdc_core/reg_control_block/tdc_config_wb_dat_o_3
------------------------------------------------- ---------------------------
- Total 7.857ns (2.938ns logic, 4.919ns route)
- (37.4% logic, 62.6% route)
+ Total 7.632ns (1.980ns logic, 5.652ns route)
+ (25.9% logic, 74.1% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAMB16_X1Y78.DIA14), 12728 paths
+Paths for end point cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAMB16_X3Y78.DIA9), 22860 paths
--------------------------------------------------------------------------------
-Slack (setup path): 0.027ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_0 (FF)
- Destination: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+Slack (setup path): 0.282ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_13 (FF)
+ Destination: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
Requirement: 8.000ns
- Data Path Delay: 7.826ns (Levels of Logic = 8)
- Clock Path Skew: -0.112ns (0.796 - 0.908)
+ Data Path Delay: 7.384ns (Levels of Logic = 6)
+ Clock Path Skew: -0.299ns (0.617 - 0.916)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1382,54 +1363,48 @@ Slack (setup path): 0.027ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_0 to cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_13 to cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X51Y170.BQ Tcko 0.391 cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset<5>
- cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_0
- SLICE_X49Y169.B5 net (fanout=2) 0.408 cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset<0>
- SLICE_X49Y169.B Tilo 0.259 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<5>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd
- SLICE_X48Y169.B4 net (fanout=2) 0.437 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd
- SLICE_X48Y169.DQ Tad_logic 0.980 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<3>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_lut<0>1
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_2
- cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<3>_rt
- SLICE_X50Y168.D5 net (fanout=1) 0.582 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<3>
- SLICE_X50Y168.COUT Topcyd 0.260 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<3>
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<3>_INV_0
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<3>
- SLICE_X50Y169.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<3>
- SLICE_X50Y169.AMUX Tcina 0.177 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<7>
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<7>
- SLICE_X52Y167.A4 net (fanout=2) 0.750 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<10>
- SLICE_X52Y167.COUT Topcya 0.379 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<10>_rt
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- SLICE_X52Y168.CIN net (fanout=1) 0.082 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- SLICE_X52Y168.COUT Tbyp 0.076 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- SLICE_X52Y169.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- SLICE_X52Y169.COUT Tbyp 0.076 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.CMUX Tcinc 0.261 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X55Y160.BQ Tcko 0.391 cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset<15>
+ cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_13
+ SLICE_X56Y160.B5 net (fanout=1) 1.029 cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset<13>
+ SLICE_X56Y160.BMUX Tilo 0.261 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<15>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd13
+ SLICE_X56Y160.C5 net (fanout=2) 0.380 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd13
+ SLICE_X56Y160.CQ Tad_logic 0.822 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<15>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_lut<0>14
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_14
+ cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<14>_rt
+ SLICE_X58Y160.C4 net (fanout=1) 0.532 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<14>
+ SLICE_X58Y160.COUT Topcyc 0.295 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<14>_INV_0
+ cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X58Y161.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X58Y161.AMUX Tcina 0.177 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ SLICE_X62Y161.A4 net (fanout=2) 0.806 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<22>
+ SLICE_X62Y161.COUT Topcya 0.395 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<22>_rt
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- RAMB16_X1Y78.DIA14 net (fanout=1) 2.399 cmp_tdc1/tdc_core/circ_buff_class_data_wr<56>
- RAMB16_X1Y78.CLKA Trdck_DIA 0.300 cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X62Y162.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X62Y162.CMUX Tcinc 0.272 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ RAMB16_X3Y78.DIA9 net (fanout=1) 1.718 cmp_tdc1/tdc_core/circ_buff_class_data_wr<60>
+ RAMB16_X3Y78.CLKA Trdck_DIA 0.300 cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
------------------------------------------------- ---------------------------
- Total 7.826ns (3.159ns logic, 4.667ns route)
- (40.4% logic, 59.6% route)
+ Total 7.384ns (2.913ns logic, 4.471ns route)
+ (39.5% logic, 60.5% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.033ns (requirement - (data path - clock path skew + uncertainty))
+Slack (setup path): 0.286ns (requirement - (data path - clock path skew + uncertainty))
Source: cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6 (FF)
- Destination: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+ Destination: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
Requirement: 8.000ns
- Data Path Delay: 7.823ns (Levels of Logic = 7)
- Clock Path Skew: -0.109ns (0.796 - 0.905)
+ Data Path Delay: 7.473ns (Levels of Logic = 8)
+ Clock Path Skew: -0.206ns (0.617 - 0.823)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1440,50 +1415,53 @@ Slack (setup path): 0.033ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6 to cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6 to cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X49Y169.DMUX Tshcko 0.461 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<5>
+ SLICE_X59Y158.CQ Tcko 0.391 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<6>
cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6
- SLICE_X48Y170.C1 net (fanout=6) 0.635 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<6>
- SLICE_X48Y170.CMUX Tilo 0.261 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ SLICE_X56Y158.C2 net (fanout=6) 0.853 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<6>
+ SLICE_X56Y158.CMUX Tilo 0.261 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd6
- SLICE_X48Y170.DX net (fanout=2) 0.585 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd6
- SLICE_X48Y170.COUT Tdxcy 0.087 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ SLICE_X56Y158.DX net (fanout=2) 0.585 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd6
+ SLICE_X56Y158.COUT Tdxcy 0.087 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_6
- SLICE_X48Y171.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>7
- SLICE_X48Y171.AQ Tito_logic 0.611 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<11>
+ SLICE_X56Y159.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>7
+ SLICE_X56Y159.COUT Tbyp 0.076 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<11>
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_10
- cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<8>_rt
- SLICE_X50Y170.A5 net (fanout=1) 0.547 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<8>
- SLICE_X50Y170.COUT Topcya 0.395 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<8>_INV_0
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- SLICE_X50Y171.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- SLICE_X50Y171.AMUX Tcina 0.177 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X56Y160.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>11
+ SLICE_X56Y160.BQ Tito_logic 0.701 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<15>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_14
+ cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<13>_rt
+ SLICE_X58Y160.B4 net (fanout=1) 0.464 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<13>
+ SLICE_X58Y160.COUT Topcyb 0.375 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<13>_INV_0
cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
- SLICE_X52Y169.A3 net (fanout=2) 0.716 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<18>
- SLICE_X52Y169.COUT Topcya 0.379 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<18>_rt
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.CMUX Tcinc 0.261 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X58Y161.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X58Y161.AMUX Tcina 0.177 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ SLICE_X62Y161.A4 net (fanout=2) 0.806 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<22>
+ SLICE_X62Y161.COUT Topcya 0.395 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<22>_rt
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- RAMB16_X1Y78.DIA14 net (fanout=1) 2.399 cmp_tdc1/tdc_core/circ_buff_class_data_wr<56>
- RAMB16_X1Y78.CLKA Trdck_DIA 0.300 cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X62Y162.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X62Y162.CMUX Tcinc 0.272 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ RAMB16_X3Y78.DIA9 net (fanout=1) 1.718 cmp_tdc1/tdc_core/circ_buff_class_data_wr<60>
+ RAMB16_X3Y78.CLKA Trdck_DIA 0.300 cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
------------------------------------------------- ---------------------------
- Total 7.823ns (2.932ns logic, 4.891ns route)
- (37.5% logic, 62.5% route)
+ Total 7.473ns (3.035ns logic, 4.438ns route)
+ (40.6% logic, 59.4% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.033ns (requirement - (data path - clock path skew + uncertainty))
+Slack (setup path): 0.286ns (requirement - (data path - clock path skew + uncertainty))
Source: cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6 (FF)
- Destination: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+ Destination: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
Requirement: 8.000ns
- Data Path Delay: 7.823ns (Levels of Logic = 7)
- Clock Path Skew: -0.109ns (0.796 - 0.905)
+ Data Path Delay: 7.473ns (Levels of Logic = 8)
+ Clock Path Skew: -0.206ns (0.617 - 0.823)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1494,53 +1472,56 @@ Slack (setup path): 0.033ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6 to cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6 to cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X49Y169.DMUX Tshcko 0.461 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<5>
+ SLICE_X59Y158.CQ Tcko 0.391 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<6>
cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6
- SLICE_X48Y170.C1 net (fanout=6) 0.635 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<6>
- SLICE_X48Y170.CMUX Tilo 0.261 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ SLICE_X56Y158.C2 net (fanout=6) 0.853 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<6>
+ SLICE_X56Y158.CMUX Tilo 0.261 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd6
- SLICE_X48Y170.DX net (fanout=2) 0.585 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd6
- SLICE_X48Y170.COUT Tdxcy 0.087 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ SLICE_X56Y158.DX net (fanout=2) 0.585 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd6
+ SLICE_X56Y158.COUT Tdxcy 0.087 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_6
- SLICE_X48Y171.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>7
- SLICE_X48Y171.DQ Tito_logic 0.711 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<11>
+ SLICE_X56Y159.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>7
+ SLICE_X56Y159.BQ Tito_logic 0.701 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<11>
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_10
- cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<11>_rt
- SLICE_X50Y170.D5 net (fanout=1) 0.582 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<11>
- SLICE_X50Y170.COUT Topcyd 0.260 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<11>_INV_0
+ cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<9>_rt
+ SLICE_X58Y159.B4 net (fanout=1) 0.464 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<9>
+ SLICE_X58Y159.COUT Topcyb 0.375 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
+ cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<9>_INV_0
cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- SLICE_X50Y171.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- SLICE_X50Y171.AMUX Tcina 0.177 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X58Y160.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
+ SLICE_X58Y160.COUT Tbyp 0.076 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
- SLICE_X52Y169.A3 net (fanout=2) 0.716 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<18>
- SLICE_X52Y169.COUT Topcya 0.379 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<18>_rt
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.CMUX Tcinc 0.261 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X58Y161.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X58Y161.AMUX Tcina 0.177 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ SLICE_X62Y161.A4 net (fanout=2) 0.806 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<22>
+ SLICE_X62Y161.COUT Topcya 0.395 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<22>_rt
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- RAMB16_X1Y78.DIA14 net (fanout=1) 2.399 cmp_tdc1/tdc_core/circ_buff_class_data_wr<56>
- RAMB16_X1Y78.CLKA Trdck_DIA 0.300 cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X62Y162.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X62Y162.CMUX Tcinc 0.272 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ RAMB16_X3Y78.DIA9 net (fanout=1) 1.718 cmp_tdc1/tdc_core/circ_buff_class_data_wr<60>
+ RAMB16_X3Y78.CLKA Trdck_DIA 0.300 cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
------------------------------------------------- ---------------------------
- Total 7.823ns (2.897ns logic, 4.926ns route)
- (37.0% logic, 63.0% route)
+ Total 7.473ns (3.035ns logic, 4.438ns route)
+ (40.6% logic, 59.4% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAMB16_X1Y78.DIA13), 10780 paths
+Paths for end point cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAMB16_X3Y78.DIA12), 33252 paths
--------------------------------------------------------------------------------
-Slack (setup path): 0.124ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_0 (FF)
- Destination: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+Slack (setup path): 0.300ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_13 (FF)
+ Destination: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
Requirement: 8.000ns
- Data Path Delay: 7.729ns (Levels of Logic = 8)
- Clock Path Skew: -0.112ns (0.796 - 0.908)
+ Data Path Delay: 7.366ns (Levels of Logic = 7)
+ Clock Path Skew: -0.299ns (0.617 - 0.916)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1551,54 +1532,51 @@ Slack (setup path): 0.124ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_0 to cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_13 to cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X51Y170.BQ Tcko 0.391 cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset<5>
- cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_0
- SLICE_X49Y169.B5 net (fanout=2) 0.408 cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset<0>
- SLICE_X49Y169.B Tilo 0.259 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<5>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd
- SLICE_X48Y169.B4 net (fanout=2) 0.437 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd
- SLICE_X48Y169.DQ Tad_logic 0.980 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<3>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_lut<0>1
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_2
- cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<3>_rt
- SLICE_X50Y168.D5 net (fanout=1) 0.582 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<3>
- SLICE_X50Y168.COUT Topcyd 0.260 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<3>
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<3>_INV_0
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<3>
- SLICE_X50Y169.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<3>
- SLICE_X50Y169.AMUX Tcina 0.177 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<7>
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<7>
- SLICE_X52Y167.A4 net (fanout=2) 0.750 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<10>
- SLICE_X52Y167.COUT Topcya 0.379 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<10>_rt
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- SLICE_X52Y168.CIN net (fanout=1) 0.082 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- SLICE_X52Y168.COUT Tbyp 0.076 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- SLICE_X52Y169.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- SLICE_X52Y169.COUT Tbyp 0.076 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.BMUX Tcinb 0.292 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X55Y160.BQ Tcko 0.391 cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset<15>
+ cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_13
+ SLICE_X56Y160.B5 net (fanout=1) 1.029 cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset<13>
+ SLICE_X56Y160.BMUX Tilo 0.261 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<15>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd13
+ SLICE_X56Y160.C5 net (fanout=2) 0.380 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd13
+ SLICE_X56Y160.CQ Tad_logic 0.822 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<15>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_lut<0>14
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_14
+ cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<14>_rt
+ SLICE_X58Y160.C4 net (fanout=1) 0.532 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<14>
+ SLICE_X58Y160.COUT Topcyc 0.295 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<14>_INV_0
+ cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X58Y161.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X58Y161.AMUX Tcina 0.177 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ SLICE_X62Y161.A4 net (fanout=2) 0.806 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<22>
+ SLICE_X62Y161.COUT Topcya 0.395 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<22>_rt
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- RAMB16_X1Y78.DIA13 net (fanout=1) 2.271 cmp_tdc1/tdc_core/circ_buff_class_data_wr<55>
- RAMB16_X1Y78.CLKA Trdck_DIA 0.300 cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X62Y162.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X62Y162.COUT Tbyp 0.076 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ SLICE_X62Y163.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ SLICE_X62Y163.BMUX Tcinb 0.260 cmp_tdc1/tdc_core/circ_buff_class_data_wr<63>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_xor<31>
+ RAMB16_X3Y78.DIA12 net (fanout=1) 1.633 cmp_tdc1/tdc_core/circ_buff_class_data_wr<63>
+ RAMB16_X3Y78.CLKA Trdck_DIA 0.300 cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
------------------------------------------------- ---------------------------
- Total 7.729ns (3.190ns logic, 4.539ns route)
- (41.3% logic, 58.7% route)
+ Total 7.366ns (2.977ns logic, 4.389ns route)
+ (40.4% logic, 59.6% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.130ns (requirement - (data path - clock path skew + uncertainty))
+Slack (setup path): 0.304ns (requirement - (data path - clock path skew + uncertainty))
Source: cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6 (FF)
- Destination: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+ Destination: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
Requirement: 8.000ns
- Data Path Delay: 7.726ns (Levels of Logic = 7)
- Clock Path Skew: -0.109ns (0.796 - 0.905)
+ Data Path Delay: 7.455ns (Levels of Logic = 9)
+ Clock Path Skew: -0.206ns (0.617 - 0.823)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1609,50 +1587,56 @@ Slack (setup path): 0.130ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6 to cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6 to cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X49Y169.DMUX Tshcko 0.461 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<5>
+ SLICE_X59Y158.CQ Tcko 0.391 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<6>
cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6
- SLICE_X48Y170.C1 net (fanout=6) 0.635 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<6>
- SLICE_X48Y170.CMUX Tilo 0.261 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ SLICE_X56Y158.C2 net (fanout=6) 0.853 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<6>
+ SLICE_X56Y158.CMUX Tilo 0.261 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd6
- SLICE_X48Y170.DX net (fanout=2) 0.585 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd6
- SLICE_X48Y170.COUT Tdxcy 0.087 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ SLICE_X56Y158.DX net (fanout=2) 0.585 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd6
+ SLICE_X56Y158.COUT Tdxcy 0.087 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_6
- SLICE_X48Y171.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>7
- SLICE_X48Y171.AQ Tito_logic 0.611 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<11>
+ SLICE_X56Y159.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>7
+ SLICE_X56Y159.COUT Tbyp 0.076 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<11>
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_10
- cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<8>_rt
- SLICE_X50Y170.A5 net (fanout=1) 0.547 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<8>
- SLICE_X50Y170.COUT Topcya 0.395 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<8>_INV_0
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- SLICE_X50Y171.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- SLICE_X50Y171.AMUX Tcina 0.177 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X56Y160.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>11
+ SLICE_X56Y160.BQ Tito_logic 0.701 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<15>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_14
+ cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<13>_rt
+ SLICE_X58Y160.B4 net (fanout=1) 0.464 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<13>
+ SLICE_X58Y160.COUT Topcyb 0.375 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<13>_INV_0
cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
- SLICE_X52Y169.A3 net (fanout=2) 0.716 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<18>
- SLICE_X52Y169.COUT Topcya 0.379 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<18>_rt
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.BMUX Tcinb 0.292 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X58Y161.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X58Y161.AMUX Tcina 0.177 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ SLICE_X62Y161.A4 net (fanout=2) 0.806 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<22>
+ SLICE_X62Y161.COUT Topcya 0.395 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<22>_rt
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- RAMB16_X1Y78.DIA13 net (fanout=1) 2.271 cmp_tdc1/tdc_core/circ_buff_class_data_wr<55>
- RAMB16_X1Y78.CLKA Trdck_DIA 0.300 cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X62Y162.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X62Y162.COUT Tbyp 0.076 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ SLICE_X62Y163.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ SLICE_X62Y163.BMUX Tcinb 0.260 cmp_tdc1/tdc_core/circ_buff_class_data_wr<63>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_xor<31>
+ RAMB16_X3Y78.DIA12 net (fanout=1) 1.633 cmp_tdc1/tdc_core/circ_buff_class_data_wr<63>
+ RAMB16_X3Y78.CLKA Trdck_DIA 0.300 cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
------------------------------------------------- ---------------------------
- Total 7.726ns (2.963ns logic, 4.763ns route)
- (38.4% logic, 61.6% route)
+ Total 7.455ns (3.099ns logic, 4.356ns route)
+ (41.6% logic, 58.4% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.130ns (requirement - (data path - clock path skew + uncertainty))
+Slack (setup path): 0.304ns (requirement - (data path - clock path skew + uncertainty))
Source: cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6 (FF)
- Destination: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+ Destination: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
Requirement: 8.000ns
- Data Path Delay: 7.726ns (Levels of Logic = 7)
- Clock Path Skew: -0.109ns (0.796 - 0.905)
+ Data Path Delay: 7.455ns (Levels of Logic = 9)
+ Clock Path Skew: -0.206ns (0.617 - 0.823)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1663,126 +1647,134 @@ Slack (setup path): 0.130ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6 to cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6 to cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X49Y169.DMUX Tshcko 0.461 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<5>
+ SLICE_X59Y158.CQ Tcko 0.391 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<6>
cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb_6
- SLICE_X48Y170.C1 net (fanout=6) 0.635 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<6>
- SLICE_X48Y170.CMUX Tilo 0.261 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ SLICE_X56Y158.C2 net (fanout=6) 0.853 cmp_tdc1/tdc_core/data_formatting_block/acam_start_nb<6>
+ SLICE_X56Y158.CMUX Tilo 0.261 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd6
- SLICE_X48Y170.DX net (fanout=2) 0.585 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd6
- SLICE_X48Y170.COUT Tdxcy 0.087 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ SLICE_X56Y158.DX net (fanout=2) 0.585 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd6
+ SLICE_X56Y158.COUT Tdxcy 0.087 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<7>
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_6
- SLICE_X48Y171.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>7
- SLICE_X48Y171.DQ Tito_logic 0.711 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<11>
+ SLICE_X56Y159.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>7
+ SLICE_X56Y159.BQ Tito_logic 0.701 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<11>
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_10
- cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<11>_rt
- SLICE_X50Y170.D5 net (fanout=1) 0.582 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<11>
- SLICE_X50Y170.COUT Topcyd 0.260 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<11>_INV_0
+ cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<9>_rt
+ SLICE_X58Y159.B4 net (fanout=1) 0.464 cmp_tdc1/tdc_core/data_formatting_block/un_nb_of_retrig<9>
+ SLICE_X58Y159.COUT Topcyb 0.375 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
+ cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<9>_INV_0
cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- SLICE_X50Y171.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- SLICE_X50Y171.AMUX Tcina 0.177 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X58Y160.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
+ SLICE_X58Y160.COUT Tbyp 0.076 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
- SLICE_X52Y169.A3 net (fanout=2) 0.716 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<18>
- SLICE_X52Y169.COUT Topcya 0.379 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<18>_rt
- cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X52Y170.BMUX Tcinb 0.292 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X58Y161.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X58Y161.AMUX Tcina 0.177 cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ cmp_tdc1/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ SLICE_X62Y161.A4 net (fanout=2) 0.806 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<22>
+ SLICE_X62Y161.COUT Topcya 0.395 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<22>_rt
cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- RAMB16_X1Y78.DIA13 net (fanout=1) 2.271 cmp_tdc1/tdc_core/circ_buff_class_data_wr<55>
- RAMB16_X1Y78.CLKA Trdck_DIA 0.300 cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X62Y162.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X62Y162.COUT Tbyp 0.076 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ SLICE_X62Y163.CIN net (fanout=1) 0.003 cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ SLICE_X62Y163.BMUX Tcinb 0.260 cmp_tdc1/tdc_core/circ_buff_class_data_wr<63>
+ cmp_tdc1/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_xor<31>
+ RAMB16_X3Y78.DIA12 net (fanout=1) 1.633 cmp_tdc1/tdc_core/circ_buff_class_data_wr<63>
+ RAMB16_X3Y78.CLKA Trdck_DIA 0.300 cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
------------------------------------------------- ---------------------------
- Total 7.726ns (2.928ns logic, 4.798ns route)
- (37.9% logic, 62.1% route)
+ Total 7.455ns (3.099ns logic, 4.356ns route)
+ (41.6% logic, 58.4% route)
--------------------------------------------------------------------------------
Hold Paths: TS_tdc1_125m_clk_p_i = PERIOD TIMEGRP "tdc1_125m_clk_p_i" 8 ns HIGH 50%;
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAMB16_X3Y82.DIA25), 1 path
+Paths for end point cmp_tdc1/tdc_core/acam_data_block/ACAM_data_st_FSM_FFd4 (SLICE_X99Y176.AX), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.332ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc1/tdc_core/data_formatting_block/acam_channel_1 (FF)
- Destination: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+Slack (hold path): 0.398ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc1/tdc_core/acam_data_block/ACAM_data_st_FSM_FFd6 (FF)
+ Destination: cmp_tdc1/tdc_core/acam_data_block/ACAM_data_st_FSM_FFd4 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.338ns (Levels of Logic = 0)
- Clock Path Skew: 0.006ns (0.071 - 0.065)
+ Data Path Delay: 0.400ns (Levels of Logic = 0)
+ Clock Path Skew: 0.002ns (0.044 - 0.042)
Source Clock: tdc1_clk_125m rising at 8.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc1/tdc_core/data_formatting_block/acam_channel_1 to cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Minimum Data Path at Fast Process Corner: cmp_tdc1/tdc_core/acam_data_block/ACAM_data_st_FSM_FFd6 to cmp_tdc1/tdc_core/acam_data_block/ACAM_data_st_FSM_FFd4
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X84Y166.BQ Tcko 0.234 cmp_tdc1/tdc_core/data_formatting_block/acam_channel<2>
- cmp_tdc1/tdc_core/data_formatting_block/acam_channel_1
- RAMB16_X3Y82.DIA25 net (fanout=1) 0.157 cmp_tdc1/tdc_core/data_formatting_block/acam_channel<1>
- RAMB16_X3Y82.CLKA Trckd_DIA (-Th) 0.053 cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X98Y176.AQ Tcko 0.200 cmp_tdc1/tdc_core/acam_data_block/ACAM_data_st_FSM_FFd4-In
+ cmp_tdc1/tdc_core/acam_data_block/ACAM_data_st_FSM_FFd6
+ SLICE_X99Y176.AX net (fanout=2) 0.141 cmp_tdc1/tdc_core/acam_data_block/ACAM_data_st_FSM_FFd4-In
+ SLICE_X99Y176.CLK Tckdi (-Th) -0.059 cmp_tdc1/tdc_core/acam_data_block/ACAM_data_st_FSM_FFd3-In
+ cmp_tdc1/tdc_core/acam_data_block/ACAM_data_st_FSM_FFd4
------------------------------------------------- ---------------------------
- Total 0.338ns (0.181ns logic, 0.157ns route)
- (53.6% logic, 46.4% route)
+ Total 0.400ns (0.259ns logic, 0.141ns route)
+ (64.8% logic, 35.3% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAMB16_X3Y82.DIA7), 1 path
+Paths for end point cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_24 (SLICE_X50Y157.B6), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.379ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc1/tdc_core/data_formatting_block/acam_fine_timestamp_7 (FF)
- Destination: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+Slack (hold path): 0.403ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc1/tdc_core/data_formatting_block/un_previous_retrig_nb_offset_24 (FF)
+ Destination: cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_24 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.380ns (Levels of Logic = 0)
- Clock Path Skew: 0.001ns (0.071 - 0.070)
+ Data Path Delay: 0.405ns (Levels of Logic = 1)
+ Clock Path Skew: 0.002ns (0.042 - 0.040)
Source Clock: tdc1_clk_125m rising at 8.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc1/tdc_core/data_formatting_block/acam_fine_timestamp_7 to cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Minimum Data Path at Fast Process Corner: cmp_tdc1/tdc_core/data_formatting_block/un_previous_retrig_nb_offset_24 to cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_24
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X85Y164.DQ Tcko 0.198 cmp_tdc1/tdc_core/data_formatting_block/acam_fine_timestamp<7>
- cmp_tdc1/tdc_core/data_formatting_block/acam_fine_timestamp_7
- RAMB16_X3Y82.DIA7 net (fanout=2) 0.235 cmp_tdc1/tdc_core/data_formatting_block/acam_fine_timestamp<7>
- RAMB16_X3Y82.CLKA Trckd_DIA (-Th) 0.053 cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X51Y157.AQ Tcko 0.198 cmp_tdc1/tdc_core/data_formatting_block/un_previous_retrig_nb_offset<25>
+ cmp_tdc1/tdc_core/data_formatting_block/un_previous_retrig_nb_offset_24
+ SLICE_X50Y157.B6 net (fanout=1) 0.017 cmp_tdc1/tdc_core/data_formatting_block/un_previous_retrig_nb_offset<24>
+ SLICE_X50Y157.CLK Tah (-Th) -0.190 cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset<25>
+ cmp_tdc1/tdc_core/data_formatting_block/Mmux_retrig_nb_offset_i[31]_un_previous_retrig_nb_offset[31]_mux_62_OUT171
+ cmp_tdc1/tdc_core/data_formatting_block/un_retrig_nb_offset_24
------------------------------------------------- ---------------------------
- Total 0.380ns (0.145ns logic, 0.235ns route)
- (38.2% logic, 61.8% route)
+ Total 0.405ns (0.388ns logic, 0.017ns route)
+ (95.8% logic, 4.2% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1/tdc_core/data_formatting_block/local_utc_20 (SLICE_X63Y168.SR), 1 path
+Paths for end point cmp_tdc1/tdc_core/reg_control_block/Pulse_stretcher/counter_0 (SLICE_X89Y149.C5), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.384ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc1_clks_rsts_mgment/internal_rst_synch_1 (FF)
- Destination: cmp_tdc1/tdc_core/data_formatting_block/local_utc_20 (FF)
+Slack (hold path): 0.410ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc1/tdc_core/reg_control_block/Pulse_stretcher/counter_1 (FF)
+ Destination: cmp_tdc1/tdc_core/reg_control_block/Pulse_stretcher/counter_0 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.388ns (Levels of Logic = 0)
- Clock Path Skew: 0.004ns (0.065 - 0.061)
+ Data Path Delay: 0.410ns (Levels of Logic = 1)
+ Clock Path Skew: 0.000ns
Source Clock: tdc1_clk_125m rising at 8.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_rsts_mgment/internal_rst_synch_1 to cmp_tdc1/tdc_core/data_formatting_block/local_utc_20
+ Minimum Data Path at Fast Process Corner: cmp_tdc1/tdc_core/reg_control_block/Pulse_stretcher/counter_1 to cmp_tdc1/tdc_core/reg_control_block/Pulse_stretcher/counter_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X60Y167.DQ Tcko 0.234 cmp_tdc1_clks_rsts_mgment/internal_rst_synch<1>
- cmp_tdc1_clks_rsts_mgment/internal_rst_synch_1
- SLICE_X63Y168.SR net (fanout=648) 0.285 cmp_tdc1_clks_rsts_mgment/internal_rst_synch<1>
- SLICE_X63Y168.CLK Tcksr (-Th) 0.131 cmp_tdc1/tdc_core/data_formatting_block/local_utc<23>
- cmp_tdc1/tdc_core/data_formatting_block/local_utc_20
+ SLICE_X89Y149.CQ Tcko 0.198 cmp_tdc1/tdc_core/reg_control_block/Pulse_stretcher/counter<1>
+ cmp_tdc1/tdc_core/reg_control_block/Pulse_stretcher/counter_1
+ SLICE_X89Y149.C5 net (fanout=2) 0.057 cmp_tdc1/tdc_core/reg_control_block/Pulse_stretcher/counter<1>
+ SLICE_X89Y149.CLK Tah (-Th) -0.155 cmp_tdc1/tdc_core/reg_control_block/Pulse_stretcher/counter<1>
+ cmp_tdc1/tdc_core/reg_control_block/Pulse_stretcher/counter_0_glue_set
+ cmp_tdc1/tdc_core/reg_control_block/Pulse_stretcher/counter_0
------------------------------------------------- ---------------------------
- Total 0.388ns (0.103ns logic, 0.285ns route)
- (26.5% logic, 73.5% route)
+ Total 0.410ns (0.353ns logic, 0.057ns route)
+ (86.1% logic, 13.9% route)
--------------------------------------------------------------------------------
@@ -1793,7 +1785,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
Logical resource: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X2Y78.CLKA
+ Location pin: RAMB16_X3Y78.CLKA
Clock network: tdc1_clk_125m
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
@@ -1801,7 +1793,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKB)
Physical resource: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
Logical resource: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
- Location pin: RAMB16_X2Y78.CLKB
+ Location pin: RAMB16_X3Y78.CLKB
Clock network: tdc1_clk_125m
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
@@ -1809,7 +1801,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
Logical resource: cmp_tdc1/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X1Y78.CLKA
+ Location pin: RAMB16_X2Y78.CLKA
Clock network: tdc1_clk_125m
--------------------------------------------------------------------------------
@@ -1830,7 +1822,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
Logical resource: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X4Y18.CLKA
+ Location pin: RAMB16_X3Y14.CLKA
Clock network: tdc2_clk_125m
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
@@ -1838,7 +1830,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKB)
Physical resource: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
Logical resource: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
- Location pin: RAMB16_X4Y18.CLKB
+ Location pin: RAMB16_X3Y14.CLKB
Clock network: tdc2_clk_125m
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
@@ -1855,19 +1847,19 @@ Timing constraint: TS_tdc2_tdc_125m_clk_n_i = PERIOD TIMEGRP
"tdc2_125m_clk_n_i" 8 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
- 542446 paths analyzed, 8647 endpoints analyzed, 0 failing endpoints
+ 542446 paths analyzed, 8641 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is 7.742ns.
+ Minimum period is 7.764ns.
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_13 (SLICE_X53Y28.C6), 608 paths
+Paths for end point cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAMB16_X3Y16.DIA15), 14898 paths
--------------------------------------------------------------------------------
-Slack (setup path): 0.258ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_0_1 (FF)
- Destination: cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_13 (FF)
+Slack (setup path): 0.236ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5 (FF)
+ Destination: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
Requirement: 8.000ns
- Data Path Delay: 7.691ns (Levels of Logic = 8)
- Clock Path Skew: -0.016ns (0.243 - 0.259)
+ Data Path Delay: 7.630ns (Levels of Logic = 7)
+ Clock Path Skew: -0.099ns (0.617 - 0.716)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1878,48 +1870,50 @@ Slack (setup path): 0.258ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_0_1 to cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_13
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5 to cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X38Y30.AMUX Tshcko 0.455 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_2_1
- cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_0_1
- SLICE_X39Y30.B6 net (fanout=3) 0.576 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_0_1
- SLICE_X39Y30.B Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0<2>
- cmp_tdc2/tdc_core/reg_control_block/_n0533<7>11
- SLICE_X40Y33.A6 net (fanout=14) 0.575 cmp_tdc2/tdc_core/reg_control_block/_n0533<7>1
- SLICE_X40Y33.A Tilo 0.203 cmp_tdc2/tdc_core/reg_control_block/acam_config_1<3>
- cmp_tdc2/tdc_core/reg_control_block/_n0533<7>1
- SLICE_X40Y33.B5 net (fanout=34) 0.883 cmp_tdc2/tdc_core/reg_control_block/_n0533
- SLICE_X40Y33.B Tilo 0.203 cmp_tdc2/tdc_core/reg_control_block/acam_config_1<3>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out1101111
- SLICE_X44Y28.D5 net (fanout=4) 1.174 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out110111
- SLICE_X44Y28.D Tilo 0.203 cmp_tdc2/tdc_core/data_engine_block/acam_config_rdbk_2<31>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out11011
- SLICE_X45Y29.B6 net (fanout=12) 0.379 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out11011
- SLICE_X45Y29.B Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/acam_config_2<23>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5510
- SLICE_X45Y29.A6 net (fanout=1) 0.452 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out559
- SLICE_X45Y29.A Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/acam_config_2<23>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5518
- SLICE_X53Y28.D2 net (fanout=1) 1.112 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5517
- SLICE_X53Y28.D Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o<13>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5519
- SLICE_X53Y28.C6 net (fanout=1) 0.118 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5518
- SLICE_X53Y28.CLK Tas 0.322 cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o<13>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5520
- cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_13
+ SLICE_X82Y22.CQ Tcko 0.408 cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset<6>
+ cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5
+ SLICE_X80Y22.B3 net (fanout=1) 1.107 cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset<5>
+ SLICE_X80Y22.BMUX Tilo 0.261 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd5
+ SLICE_X80Y22.CX net (fanout=2) 1.079 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd5
+ SLICE_X80Y22.COUT Tcxcy 0.093 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_6
+ SLICE_X80Y23.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>7
+ SLICE_X80Y23.COUT Tbyp 0.076 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<11>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_10
+ SLICE_X80Y24.CIN net (fanout=1) 0.082 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>11
+ SLICE_X80Y24.BQ Tito_logic 0.701 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<15>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_14
+ cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<13>_rt
+ SLICE_X76Y25.B5 net (fanout=1) 0.617 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<13>
+ SLICE_X76Y25.COUT Topcyb 0.380 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<13>_INV_0
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X76Y26.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X76Y26.BMUX Tcinb 0.292 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ SLICE_X78Y27.B6 net (fanout=2) 0.690 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<23>
+ SLICE_X78Y27.DMUX Topbd 0.537 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<23>_rt
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ RAMB16_X3Y16.DIA15 net (fanout=1) 1.001 cmp_tdc2/tdc_core/circ_buff_class_data_wr<57>
+ RAMB16_X3Y16.CLKA Trdck_DIA 0.300 cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
------------------------------------------------- ---------------------------
- Total 7.691ns (2.422ns logic, 5.269ns route)
- (31.5% logic, 68.5% route)
+ Total 7.630ns (3.048ns logic, 4.582ns route)
+ (39.9% logic, 60.1% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.273ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_5 (FF)
- Destination: cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_13 (FF)
+Slack (setup path): 0.243ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5 (FF)
+ Destination: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
Requirement: 8.000ns
- Data Path Delay: 7.678ns (Levels of Logic = 8)
- Clock Path Skew: -0.014ns (0.243 - 0.257)
+ Data Path Delay: 7.623ns (Levels of Logic = 7)
+ Clock Path Skew: -0.099ns (0.617 - 0.716)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1930,48 +1924,50 @@ Slack (setup path): 0.273ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_5 to cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_13
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5 to cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X39Y29.AQ Tcko 0.391 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_3_1
- cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_5
- SLICE_X39Y30.B1 net (fanout=10) 0.627 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0<5>
- SLICE_X39Y30.B Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0<2>
- cmp_tdc2/tdc_core/reg_control_block/_n0533<7>11
- SLICE_X40Y33.A6 net (fanout=14) 0.575 cmp_tdc2/tdc_core/reg_control_block/_n0533<7>1
- SLICE_X40Y33.A Tilo 0.203 cmp_tdc2/tdc_core/reg_control_block/acam_config_1<3>
- cmp_tdc2/tdc_core/reg_control_block/_n0533<7>1
- SLICE_X40Y33.B5 net (fanout=34) 0.883 cmp_tdc2/tdc_core/reg_control_block/_n0533
- SLICE_X40Y33.B Tilo 0.203 cmp_tdc2/tdc_core/reg_control_block/acam_config_1<3>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out1101111
- SLICE_X44Y28.D5 net (fanout=4) 1.174 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out110111
- SLICE_X44Y28.D Tilo 0.203 cmp_tdc2/tdc_core/data_engine_block/acam_config_rdbk_2<31>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out11011
- SLICE_X45Y29.B6 net (fanout=12) 0.379 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out11011
- SLICE_X45Y29.B Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/acam_config_2<23>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5510
- SLICE_X45Y29.A6 net (fanout=1) 0.452 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out559
- SLICE_X45Y29.A Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/acam_config_2<23>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5518
- SLICE_X53Y28.D2 net (fanout=1) 1.112 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5517
- SLICE_X53Y28.D Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o<13>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5519
- SLICE_X53Y28.C6 net (fanout=1) 0.118 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5518
- SLICE_X53Y28.CLK Tas 0.322 cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o<13>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5520
- cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_13
+ SLICE_X82Y22.CQ Tcko 0.408 cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset<6>
+ cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5
+ SLICE_X80Y22.B3 net (fanout=1) 1.107 cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset<5>
+ SLICE_X80Y22.BMUX Tilo 0.261 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd5
+ SLICE_X80Y22.CX net (fanout=2) 1.079 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd5
+ SLICE_X80Y22.COUT Tcxcy 0.093 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_6
+ SLICE_X80Y23.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>7
+ SLICE_X80Y23.COUT Tbyp 0.076 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<11>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_10
+ SLICE_X80Y24.CIN net (fanout=1) 0.082 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>11
+ SLICE_X80Y24.AQ Tito_logic 0.611 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<15>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_14
+ cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<12>_rt
+ SLICE_X76Y25.A3 net (fanout=1) 0.701 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<12>
+ SLICE_X76Y25.COUT Topcya 0.379 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<12>_INV_0
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X76Y26.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X76Y26.BMUX Tcinb 0.292 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ SLICE_X78Y27.B6 net (fanout=2) 0.690 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<23>
+ SLICE_X78Y27.DMUX Topbd 0.537 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<23>_rt
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ RAMB16_X3Y16.DIA15 net (fanout=1) 1.001 cmp_tdc2/tdc_core/circ_buff_class_data_wr<57>
+ RAMB16_X3Y16.CLKA Trdck_DIA 0.300 cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
------------------------------------------------- ---------------------------
- Total 7.678ns (2.358ns logic, 5.320ns route)
- (30.7% logic, 69.3% route)
+ Total 7.623ns (2.957ns logic, 4.666ns route)
+ (38.8% logic, 61.2% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.303ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_7 (FF)
- Destination: cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_13 (FF)
+Slack (setup path): 0.254ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5 (FF)
+ Destination: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
Requirement: 8.000ns
- Data Path Delay: 7.647ns (Levels of Logic = 8)
- Clock Path Skew: -0.015ns (0.243 - 0.258)
+ Data Path Delay: 7.612ns (Levels of Logic = 7)
+ Clock Path Skew: -0.099ns (0.617 - 0.716)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1982,51 +1978,53 @@ Slack (setup path): 0.303ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_7 to cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_13
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5 to cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X43Y30.CQ Tcko 0.391 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0<6>
- cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_7
- SLICE_X39Y30.B4 net (fanout=10) 0.596 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0<7>
- SLICE_X39Y30.B Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0<2>
- cmp_tdc2/tdc_core/reg_control_block/_n0533<7>11
- SLICE_X40Y33.A6 net (fanout=14) 0.575 cmp_tdc2/tdc_core/reg_control_block/_n0533<7>1
- SLICE_X40Y33.A Tilo 0.203 cmp_tdc2/tdc_core/reg_control_block/acam_config_1<3>
- cmp_tdc2/tdc_core/reg_control_block/_n0533<7>1
- SLICE_X40Y33.B5 net (fanout=34) 0.883 cmp_tdc2/tdc_core/reg_control_block/_n0533
- SLICE_X40Y33.B Tilo 0.203 cmp_tdc2/tdc_core/reg_control_block/acam_config_1<3>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out1101111
- SLICE_X44Y28.D5 net (fanout=4) 1.174 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out110111
- SLICE_X44Y28.D Tilo 0.203 cmp_tdc2/tdc_core/data_engine_block/acam_config_rdbk_2<31>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out11011
- SLICE_X45Y29.B6 net (fanout=12) 0.379 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out11011
- SLICE_X45Y29.B Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/acam_config_2<23>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5510
- SLICE_X45Y29.A6 net (fanout=1) 0.452 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out559
- SLICE_X45Y29.A Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/acam_config_2<23>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5518
- SLICE_X53Y28.D2 net (fanout=1) 1.112 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5517
- SLICE_X53Y28.D Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o<13>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5519
- SLICE_X53Y28.C6 net (fanout=1) 0.118 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5518
- SLICE_X53Y28.CLK Tas 0.322 cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o<13>
- cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out5520
- cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_13
+ SLICE_X82Y22.CQ Tcko 0.408 cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset<6>
+ cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5
+ SLICE_X80Y22.B3 net (fanout=1) 1.107 cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset<5>
+ SLICE_X80Y22.BMUX Tilo 0.261 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd5
+ SLICE_X80Y22.CX net (fanout=2) 1.079 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd5
+ SLICE_X80Y22.COUT Tcxcy 0.093 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_6
+ SLICE_X80Y23.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>7
+ SLICE_X80Y23.BQ Tito_logic 0.701 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<11>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_10
+ cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<9>_rt
+ SLICE_X76Y24.B5 net (fanout=1) 0.644 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<9>
+ SLICE_X76Y24.COUT Topcyb 0.380 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<9>_INV_0
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
+ SLICE_X76Y25.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
+ SLICE_X76Y25.BMUX Tcinb 0.292 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X78Y26.B6 net (fanout=2) 0.690 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<19>
+ SLICE_X78Y26.COUT Topcyb 0.375 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<19>_rt
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
+ SLICE_X78Y27.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
+ SLICE_X78Y27.DMUX Tcind 0.272 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ RAMB16_X3Y16.DIA15 net (fanout=1) 1.001 cmp_tdc2/tdc_core/circ_buff_class_data_wr<57>
+ RAMB16_X3Y16.CLKA Trdck_DIA 0.300 cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
------------------------------------------------- ---------------------------
- Total 7.647ns (2.358ns logic, 5.289ns route)
- (30.8% logic, 69.2% route)
+ Total 7.612ns (3.082ns logic, 4.530ns route)
+ (40.5% logic, 59.5% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAMB16_X3Y18.DIA14), 1748 paths
+Paths for end point cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_19 (SLICE_X44Y18.C6), 608 paths
--------------------------------------------------------------------------------
-Slack (setup path): 0.260ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_2 (FF)
- Destination: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+Slack (setup path): 0.254ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_6 (FF)
+ Destination: cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_19 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.686ns (Levels of Logic = 6)
- Clock Path Skew: -0.019ns (0.238 - 0.257)
+ Data Path Delay: 7.706ns (Levels of Logic = 7)
+ Clock Path Skew: -0.005ns (0.245 - 0.250)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -2037,47 +2035,45 @@ Slack (setup path): 0.260ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_2 to cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_6 to cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_19
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X105Y35.DQ Tcko 0.391 cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset<2>
- cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_2
- SLICE_X104Y32.C3 net (fanout=1) 0.657 cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset<2>
- SLICE_X104Y32.CMUX Tilo 0.261 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<3>
- cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd2
- SLICE_X104Y32.DX net (fanout=2) 0.967 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd2
- SLICE_X104Y32.COUT Tdxcy 0.087 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<3>
- cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_2
- SLICE_X104Y33.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>3
- SLICE_X104Y33.AQ Tito_logic 0.611 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>
- cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_6
- cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<4>_rt
- SLICE_X108Y31.A5 net (fanout=1) 0.822 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<4>
- SLICE_X108Y31.CMUX Topac 0.537 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<7>
- cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<4>_INV_0
- cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<7>
- SLICE_X106Y30.C6 net (fanout=2) 0.667 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<12>
- SLICE_X106Y30.COUT Topcyc 0.295 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<12>_rt
- cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- SLICE_X106Y31.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- SLICE_X106Y31.BMUX Tcinb 0.260 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- RAMB16_X3Y18.DIA14 net (fanout=1) 1.825 cmp_tdc2/tdc_core/circ_buff_class_data_wr<47>
- RAMB16_X3Y18.CLKA Trdck_DIA 0.300 cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X39Y26.CQ Tcko 0.391 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0<6>
+ cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_6
+ SLICE_X39Y26.B2 net (fanout=10) 0.742 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0<6>
+ SLICE_X39Y26.B Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0<6>
+ cmp_tdc2/tdc_core/reg_control_block/_n0524<7>11
+ SLICE_X40Y24.A6 net (fanout=33) 1.023 cmp_tdc2/tdc_core/reg_control_block/_n0524<7>1
+ SLICE_X40Y24.A Tilo 0.203 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out18714
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out11011_SW0
+ SLICE_X39Y22.A1 net (fanout=2) 1.430 N328
+ SLICE_X39Y22.A Tilo 0.259 cmp_tdc2/tdc_core/data_engine_block/acam_config_rdbk_3<31>
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out11011_1
+ SLICE_X38Y20.B5 net (fanout=10) 0.549 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out110112
+ SLICE_X38Y20.B Tilo 0.205 cmp_tdc2/tdc_core/data_engine_block/acam_config_rdbk_3<7>
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12110
+ SLICE_X38Y20.A6 net (fanout=1) 0.553 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out1219
+ SLICE_X38Y20.A Tilo 0.205 cmp_tdc2/tdc_core/data_engine_block/acam_config_rdbk_3<7>
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12118
+ SLICE_X44Y18.D4 net (fanout=1) 1.277 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12117
+ SLICE_X44Y18.D Tilo 0.203 cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o<19>
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12119
+ SLICE_X44Y18.C6 net (fanout=1) 0.118 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12118
+ SLICE_X44Y18.CLK Tas 0.289 cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o<19>
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12120
+ cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_19
------------------------------------------------- ---------------------------
- Total 7.686ns (2.742ns logic, 4.944ns route)
- (35.7% logic, 64.3% route)
+ Total 7.706ns (2.014ns logic, 5.692ns route)
+ (26.1% logic, 73.9% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.282ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2/tdc_core/data_formatting_block/acam_start_nb_2 (FF)
- Destination: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+Slack (setup path): 0.281ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_2_1 (FF)
+ Destination: cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_19 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.661ns (Levels of Logic = 6)
- Clock Path Skew: -0.022ns (0.238 - 0.260)
+ Data Path Delay: 7.676ns (Levels of Logic = 7)
+ Clock Path Skew: -0.008ns (0.245 - 0.253)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -2088,47 +2084,45 @@ Slack (setup path): 0.282ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2/tdc_core/data_formatting_block/acam_start_nb_2 to cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_2_1 to cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_19
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X105Y32.CQ Tcko 0.391 cmp_tdc2/tdc_core/data_formatting_block/acam_start_nb<3>
- cmp_tdc2/tdc_core/data_formatting_block/acam_start_nb_2
- SLICE_X104Y32.C1 net (fanout=5) 0.632 cmp_tdc2/tdc_core/data_formatting_block/acam_start_nb<2>
- SLICE_X104Y32.CMUX Tilo 0.261 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<3>
- cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd2
- SLICE_X104Y32.DX net (fanout=2) 0.967 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd2
- SLICE_X104Y32.COUT Tdxcy 0.087 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<3>
- cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_2
- SLICE_X104Y33.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>3
- SLICE_X104Y33.AQ Tito_logic 0.611 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>
- cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_6
- cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<4>_rt
- SLICE_X108Y31.A5 net (fanout=1) 0.822 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<4>
- SLICE_X108Y31.CMUX Topac 0.537 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<7>
- cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<4>_INV_0
- cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<7>
- SLICE_X106Y30.C6 net (fanout=2) 0.667 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<12>
- SLICE_X106Y30.COUT Topcyc 0.295 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<12>_rt
- cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- SLICE_X106Y31.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- SLICE_X106Y31.BMUX Tcinb 0.260 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- RAMB16_X3Y18.DIA14 net (fanout=1) 1.825 cmp_tdc2/tdc_core/circ_buff_class_data_wr<47>
- RAMB16_X3Y18.CLKA Trdck_DIA 0.300 cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X39Y27.AQ Tcko 0.391 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_2_1
+ cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_2_1
+ SLICE_X39Y26.B6 net (fanout=3) 0.712 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_2_1
+ SLICE_X39Y26.B Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0<6>
+ cmp_tdc2/tdc_core/reg_control_block/_n0524<7>11
+ SLICE_X40Y24.A6 net (fanout=33) 1.023 cmp_tdc2/tdc_core/reg_control_block/_n0524<7>1
+ SLICE_X40Y24.A Tilo 0.203 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out18714
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out11011_SW0
+ SLICE_X39Y22.A1 net (fanout=2) 1.430 N328
+ SLICE_X39Y22.A Tilo 0.259 cmp_tdc2/tdc_core/data_engine_block/acam_config_rdbk_3<31>
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out11011_1
+ SLICE_X38Y20.B5 net (fanout=10) 0.549 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out110112
+ SLICE_X38Y20.B Tilo 0.205 cmp_tdc2/tdc_core/data_engine_block/acam_config_rdbk_3<7>
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12110
+ SLICE_X38Y20.A6 net (fanout=1) 0.553 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out1219
+ SLICE_X38Y20.A Tilo 0.205 cmp_tdc2/tdc_core/data_engine_block/acam_config_rdbk_3<7>
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12118
+ SLICE_X44Y18.D4 net (fanout=1) 1.277 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12117
+ SLICE_X44Y18.D Tilo 0.203 cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o<19>
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12119
+ SLICE_X44Y18.C6 net (fanout=1) 0.118 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12118
+ SLICE_X44Y18.CLK Tas 0.289 cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o<19>
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12120
+ cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_19
------------------------------------------------- ---------------------------
- Total 7.661ns (2.742ns logic, 4.919ns route)
- (35.8% logic, 64.2% route)
+ Total 7.676ns (2.014ns logic, 5.662ns route)
+ (26.2% logic, 73.8% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.356ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2/tdc_core/data_formatting_block/acam_start_nb_5 (FF)
- Destination: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+Slack (setup path): 0.282ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_4 (FF)
+ Destination: cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_19 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.587ns (Levels of Logic = 5)
- Clock Path Skew: -0.022ns (0.238 - 0.260)
+ Data Path Delay: 7.678ns (Levels of Logic = 7)
+ Clock Path Skew: -0.005ns (0.245 - 0.250)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -2139,48 +2133,48 @@ Slack (setup path): 0.356ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2/tdc_core/data_formatting_block/acam_start_nb_5 to cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_4 to cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_19
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X105Y33.BQ Tcko 0.391 cmp_tdc2/tdc_core/data_formatting_block/acam_start_nb<7>
- cmp_tdc2/tdc_core/data_formatting_block/acam_start_nb_5
- SLICE_X104Y33.B1 net (fanout=5) 0.639 cmp_tdc2/tdc_core/data_formatting_block/acam_start_nb<5>
- SLICE_X104Y33.BMUX Tilo 0.261 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>
- cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd5
- SLICE_X104Y33.C5 net (fanout=2) 1.021 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd5
- SLICE_X104Y33.DQ Tad_logic 0.844 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>
- cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_lut<0>6
- cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_6
- cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>_rt
- SLICE_X108Y31.D5 net (fanout=1) 0.814 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>
- SLICE_X108Y31.COUT Topcyd 0.261 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<7>
- cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<7>_INV_0
- cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<7>
- SLICE_X108Y32.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<7>
- SLICE_X108Y32.BMUX Tcinb 0.292 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<11>
- SLICE_X106Y31.B3 net (fanout=2) 0.568 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<15>
- SLICE_X106Y31.BMUX Topbb 0.368 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<15>_rt
- cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- RAMB16_X3Y18.DIA14 net (fanout=1) 1.825 cmp_tdc2/tdc_core/circ_buff_class_data_wr<47>
- RAMB16_X3Y18.CLKA Trdck_DIA 0.300 cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X38Y26.AQ Tcko 0.408 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_2_2
+ cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0_4
+ SLICE_X41Y26.A3 net (fanout=48) 1.817 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0<4>
+ SLICE_X41Y26.A Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/acam_config_1<7>
+ cmp_tdc2/tdc_core/reg_control_block/_n0533<7>21
+ SLICE_X41Y26.D3 net (fanout=1) 0.316 cmp_tdc2/tdc_core/reg_control_block/_n0533<7>2
+ SLICE_X41Y26.D Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/acam_config_1<7>
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out1101231
+ SLICE_X39Y22.A4 net (fanout=34) 0.961 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out110123
+ SLICE_X39Y22.A Tilo 0.259 cmp_tdc2/tdc_core/data_engine_block/acam_config_rdbk_3<31>
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out11011_1
+ SLICE_X38Y20.B5 net (fanout=10) 0.549 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out110112
+ SLICE_X38Y20.B Tilo 0.205 cmp_tdc2/tdc_core/data_engine_block/acam_config_rdbk_3<7>
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12110
+ SLICE_X38Y20.A6 net (fanout=1) 0.553 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out1219
+ SLICE_X38Y20.A Tilo 0.205 cmp_tdc2/tdc_core/data_engine_block/acam_config_rdbk_3<7>
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12118
+ SLICE_X44Y18.D4 net (fanout=1) 1.277 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12117
+ SLICE_X44Y18.D Tilo 0.203 cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o<19>
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12119
+ SLICE_X44Y18.C6 net (fanout=1) 0.118 cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12118
+ SLICE_X44Y18.CLK Tas 0.289 cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o<19>
+ cmp_tdc2/tdc_core/reg_control_block/Mmux_dat_out12120
+ cmp_tdc2/tdc_core/reg_control_block/tdc_config_wb_dat_o_19
------------------------------------------------- ---------------------------
- Total 7.587ns (2.717ns logic, 4.870ns route)
- (35.8% logic, 64.2% route)
+ Total 7.678ns (2.087ns logic, 5.591ns route)
+ (27.2% logic, 72.8% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2/tdc_core/reg_control_block/acam_config_7_16 (SLICE_X34Y33.CE), 22 paths
+Paths for end point cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAMB16_X3Y16.DIPA1), 17302 paths
--------------------------------------------------------------------------------
-Slack (setup path): 0.267ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2_clks_crossing/mfifo/ram/Mram_ram1 (RAM)
- Destination: cmp_tdc2/tdc_core/reg_control_block/acam_config_7_16 (FF)
+Slack (setup path): 0.262ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5 (FF)
+ Destination: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
Requirement: 8.000ns
- Data Path Delay: 7.693ns (Levels of Logic = 3)
- Clock Path Skew: -0.005ns (0.242 - 0.247)
+ Data Path Delay: 7.604ns (Levels of Logic = 8)
+ Clock Path Skew: -0.099ns (0.617 - 0.716)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -2191,35 +2185,53 @@ Slack (setup path): 0.267ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2_clks_crossing/mfifo/ram/Mram_ram1 to cmp_tdc2/tdc_core/reg_control_block/acam_config_7_16
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5 to cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- RAMB8_X2Y20.DOADO1 Trcko_DOA 1.850 cmp_tdc2_clks_crossing/mfifo/ram/Mram_ram1
- cmp_tdc2_clks_crossing/mfifo/ram/Mram_ram1
- SLICE_X48Y35.C1 net (fanout=30) 1.674 tdc2_slave_in_we
- SLICE_X48Y35.C Tilo 0.204 cmp_tdc2/cnx_master_out[0]_we
- cmp_tdc2/cmp_sdb_crossbar/crossbar/master_oe[0]_we1
- SLICE_X49Y35.A2 net (fanout=1) 0.690 cmp_tdc2/cnx_master_out[0]_we
- SLICE_X49Y35.A Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/_n0477_inv
- cmp_tdc2/tdc_core/reg_control_block/_n0429_inv11
- SLICE_X39Y36.D6 net (fanout=18) 1.409 cmp_tdc2/tdc_core/reg_control_block/_n0429_inv1
- SLICE_X39Y36.D Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/acam_config_7<11>
- cmp_tdc2/tdc_core/reg_control_block/_n0457_inv1
- SLICE_X34Y33.CE net (fanout=7) 1.013 cmp_tdc2/tdc_core/reg_control_block/_n0457_inv
- SLICE_X34Y33.CLK Tceck 0.335 cmp_tdc2/tdc_core/reg_control_block/acam_config_7<19>
- cmp_tdc2/tdc_core/reg_control_block/acam_config_7_16
+ SLICE_X82Y22.CQ Tcko 0.408 cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset<6>
+ cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5
+ SLICE_X80Y22.B3 net (fanout=1) 1.107 cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset<5>
+ SLICE_X80Y22.BMUX Tilo 0.261 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd5
+ SLICE_X80Y22.CX net (fanout=2) 1.079 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd5
+ SLICE_X80Y22.COUT Tcxcy 0.093 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_6
+ SLICE_X80Y23.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>7
+ SLICE_X80Y23.COUT Tbyp 0.076 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<11>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_10
+ SLICE_X80Y24.CIN net (fanout=1) 0.082 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>11
+ SLICE_X80Y24.BQ Tito_logic 0.701 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<15>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_14
+ cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<13>_rt
+ SLICE_X76Y25.B5 net (fanout=1) 0.617 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<13>
+ SLICE_X76Y25.COUT Topcyb 0.380 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<13>_INV_0
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X76Y26.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X76Y26.BMUX Tcinb 0.292 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ SLICE_X78Y27.B6 net (fanout=2) 0.690 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<23>
+ SLICE_X78Y27.COUT Topcyb 0.375 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<23>_rt
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X78Y28.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X78Y28.AMUX Tcina 0.177 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ RAMB16_X3Y16.DIPA1 net (fanout=1) 0.957 cmp_tdc2/tdc_core/circ_buff_class_data_wr<58>
+ RAMB16_X3Y16.CLKA Trdck_DIPA 0.300 cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
------------------------------------------------- ---------------------------
- Total 7.693ns (2.907ns logic, 4.786ns route)
- (37.8% logic, 62.2% route)
+ Total 7.604ns (3.063ns logic, 4.541ns route)
+ (40.3% logic, 59.7% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.337ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2_clks_crossing/mfifo/ram/Mram_ram1 (RAM)
- Destination: cmp_tdc2/tdc_core/reg_control_block/acam_config_7_16 (FF)
+Slack (setup path): 0.269ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5 (FF)
+ Destination: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
Requirement: 8.000ns
- Data Path Delay: 7.623ns (Levels of Logic = 3)
- Clock Path Skew: -0.005ns (0.242 - 0.247)
+ Data Path Delay: 7.597ns (Levels of Logic = 8)
+ Clock Path Skew: -0.099ns (0.617 - 0.716)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -2230,35 +2242,53 @@ Slack (setup path): 0.337ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2_clks_crossing/mfifo/ram/Mram_ram1 to cmp_tdc2/tdc_core/reg_control_block/acam_config_7_16
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5 to cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- RAMB8_X2Y20.DOADO11 Trcko_DOA 1.850 cmp_tdc2_clks_crossing/mfifo/ram/Mram_ram1
- cmp_tdc2_clks_crossing/mfifo/ram/Mram_ram1
- SLICE_X43Y30.D5 net (fanout=8) 1.340 tdc2_slave_in_adr<9>
- SLICE_X43Y30.DMUX Tilo 0.313 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0<6>
- cmp_tdc2/cmp_sdb_crossbar/crossbar/master_oe[0]_adr<9>1
- SLICE_X49Y35.A6 net (fanout=2) 0.845 cmp_tdc2/cnx_master_out[0]_adr<9>
- SLICE_X49Y35.A Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/_n0477_inv
- cmp_tdc2/tdc_core/reg_control_block/_n0429_inv11
- SLICE_X39Y36.D6 net (fanout=18) 1.409 cmp_tdc2/tdc_core/reg_control_block/_n0429_inv1
- SLICE_X39Y36.D Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/acam_config_7<11>
- cmp_tdc2/tdc_core/reg_control_block/_n0457_inv1
- SLICE_X34Y33.CE net (fanout=7) 1.013 cmp_tdc2/tdc_core/reg_control_block/_n0457_inv
- SLICE_X34Y33.CLK Tceck 0.335 cmp_tdc2/tdc_core/reg_control_block/acam_config_7<19>
- cmp_tdc2/tdc_core/reg_control_block/acam_config_7_16
+ SLICE_X82Y22.CQ Tcko 0.408 cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset<6>
+ cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5
+ SLICE_X80Y22.B3 net (fanout=1) 1.107 cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset<5>
+ SLICE_X80Y22.BMUX Tilo 0.261 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd5
+ SLICE_X80Y22.CX net (fanout=2) 1.079 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd5
+ SLICE_X80Y22.COUT Tcxcy 0.093 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_6
+ SLICE_X80Y23.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>7
+ SLICE_X80Y23.COUT Tbyp 0.076 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<11>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_10
+ SLICE_X80Y24.CIN net (fanout=1) 0.082 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>11
+ SLICE_X80Y24.AQ Tito_logic 0.611 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<15>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_14
+ cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<12>_rt
+ SLICE_X76Y25.A3 net (fanout=1) 0.701 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<12>
+ SLICE_X76Y25.COUT Topcya 0.379 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<12>_INV_0
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X76Y26.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X76Y26.BMUX Tcinb 0.292 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ SLICE_X78Y27.B6 net (fanout=2) 0.690 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<23>
+ SLICE_X78Y27.COUT Topcyb 0.375 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<23>_rt
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X78Y28.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X78Y28.AMUX Tcina 0.177 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ RAMB16_X3Y16.DIPA1 net (fanout=1) 0.957 cmp_tdc2/tdc_core/circ_buff_class_data_wr<58>
+ RAMB16_X3Y16.CLKA Trdck_DIPA 0.300 cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
------------------------------------------------- ---------------------------
- Total 7.623ns (3.016ns logic, 4.607ns route)
- (39.6% logic, 60.4% route)
+ Total 7.597ns (2.972ns logic, 4.625ns route)
+ (39.1% logic, 60.9% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.350ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2_clks_crossing/mfifo/ram/Mram_ram1 (RAM)
- Destination: cmp_tdc2/tdc_core/reg_control_block/acam_config_7_16 (FF)
+Slack (setup path): 0.311ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5 (FF)
+ Destination: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
Requirement: 8.000ns
- Data Path Delay: 7.610ns (Levels of Logic = 3)
- Clock Path Skew: -0.005ns (0.242 - 0.247)
+ Data Path Delay: 7.555ns (Levels of Logic = 8)
+ Clock Path Skew: -0.099ns (0.617 - 0.716)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -2269,113 +2299,129 @@ Slack (setup path): 0.350ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2_clks_crossing/mfifo/ram/Mram_ram1 to cmp_tdc2/tdc_core/reg_control_block/acam_config_7_16
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5 to cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- RAMB8_X2Y20.DOADO10 Trcko_DOA 1.850 cmp_tdc2_clks_crossing/mfifo/ram/Mram_ram1
- cmp_tdc2_clks_crossing/mfifo/ram/Mram_ram1
- SLICE_X43Y30.D4 net (fanout=8) 1.235 tdc2_slave_in_adr<8>
- SLICE_X43Y30.D Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/reg_adr_pipe0<6>
- cmp_tdc2/cmp_sdb_crossbar/crossbar/master_oe[0]_adr<8>1
- SLICE_X49Y35.A4 net (fanout=1) 0.991 cmp_tdc2/cnx_master_out[0]_adr<8>
- SLICE_X49Y35.A Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/_n0477_inv
- cmp_tdc2/tdc_core/reg_control_block/_n0429_inv11
- SLICE_X39Y36.D6 net (fanout=18) 1.409 cmp_tdc2/tdc_core/reg_control_block/_n0429_inv1
- SLICE_X39Y36.D Tilo 0.259 cmp_tdc2/tdc_core/reg_control_block/acam_config_7<11>
- cmp_tdc2/tdc_core/reg_control_block/_n0457_inv1
- SLICE_X34Y33.CE net (fanout=7) 1.013 cmp_tdc2/tdc_core/reg_control_block/_n0457_inv
- SLICE_X34Y33.CLK Tceck 0.335 cmp_tdc2/tdc_core/reg_control_block/acam_config_7<19>
- cmp_tdc2/tdc_core/reg_control_block/acam_config_7_16
+ SLICE_X82Y22.CQ Tcko 0.408 cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset<6>
+ cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset_5
+ SLICE_X80Y22.B3 net (fanout=1) 1.107 cmp_tdc2/tdc_core/data_formatting_block/un_retrig_nb_offset<5>
+ SLICE_X80Y22.BMUX Tilo 0.261 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd5
+ SLICE_X80Y22.CX net (fanout=2) 1.079 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd5
+ SLICE_X80Y22.COUT Tcxcy 0.093 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<7>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_6
+ SLICE_X80Y23.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>7
+ SLICE_X80Y23.COUT Tbyp 0.076 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<11>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_10
+ SLICE_X80Y24.CIN net (fanout=1) 0.082 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>11
+ SLICE_X80Y24.BQ Tito_logic 0.701 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<15>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_14
+ cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<13>_rt
+ SLICE_X76Y25.B5 net (fanout=1) 0.617 cmp_tdc2/tdc_core/data_formatting_block/un_nb_of_retrig<13>
+ SLICE_X76Y25.COUT Topcyb 0.380 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_lut<13>_INV_0
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X76Y26.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<15>
+ SLICE_X76Y26.AMUX Tcina 0.202 cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ cmp_tdc2/tdc_core/data_formatting_block/Msub_GND_313_o_GND_313_o_sub_76_OUT<25:0>_cy<19>
+ SLICE_X78Y27.A5 net (fanout=2) 0.711 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<22>
+ SLICE_X78Y27.COUT Topcya 0.395 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<22>_rt
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X78Y28.CIN net (fanout=1) 0.003 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
+ SLICE_X78Y28.AMUX Tcina 0.177 cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ cmp_tdc2/tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
+ RAMB16_X3Y16.DIPA1 net (fanout=1) 0.957 cmp_tdc2/tdc_core/circ_buff_class_data_wr<58>
+ RAMB16_X3Y16.CLKA Trdck_DIPA 0.300 cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
------------------------------------------------- ---------------------------
- Total 7.610ns (2.962ns logic, 4.648ns route)
- (38.9% logic, 61.1% route)
+ Total 7.555ns (2.993ns logic, 4.562ns route)
+ (39.6% logic, 60.4% route)
--------------------------------------------------------------------------------
Hold Paths: TS_tdc2_tdc_125m_clk_n_i = PERIOD TIMEGRP "tdc2_125m_clk_n_i" 8 ns HIGH 50%;
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAMB16_X4Y16.DIPA0), 1 path
+Paths for end point cmp_tdc2/tdc_core/reg_control_block/Pulse_stretcher/counter_2 (SLICE_X59Y24.SR), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.376ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc2/tdc_core/data_formatting_block/acam_fine_timestamp_8 (FF)
- Destination: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+Slack (hold path): 0.325ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc2/tdc_core/reg_control_block/ctrl_reg_11 (FF)
+ Destination: cmp_tdc2/tdc_core/reg_control_block/Pulse_stretcher/counter_2 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.380ns (Levels of Logic = 0)
- Clock Path Skew: 0.004ns (0.077 - 0.073)
+ Data Path Delay: 0.329ns (Levels of Logic = 0)
+ Clock Path Skew: 0.004ns (0.067 - 0.063)
Source Clock: tdc2_clk_125m rising at 8.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc2/tdc_core/data_formatting_block/acam_fine_timestamp_8 to cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Minimum Data Path at Fast Process Corner: cmp_tdc2/tdc_core/reg_control_block/ctrl_reg_11 to cmp_tdc2/tdc_core/reg_control_block/Pulse_stretcher/counter_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X101Y32.AQ Tcko 0.198 cmp_tdc2/tdc_core/data_formatting_block/acam_fine_timestamp<11>
- cmp_tdc2/tdc_core/data_formatting_block/acam_fine_timestamp_8
- RAMB16_X4Y16.DIPA0 net (fanout=2) 0.235 cmp_tdc2/tdc_core/data_formatting_block/acam_fine_timestamp<8>
- RAMB16_X4Y16.CLKA Trckd_DIPA (-Th) 0.053 cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X57Y24.DQ Tcko 0.198 cmp_tdc2/tdc_core/reg_control_block/ctrl_reg<11>
+ cmp_tdc2/tdc_core/reg_control_block/ctrl_reg_11
+ SLICE_X59Y24.SR net (fanout=1) 0.270 cmp_tdc2/tdc_core/reg_control_block/ctrl_reg<11>
+ SLICE_X59Y24.CLK Tcksr (-Th) 0.139 cmp_tdc2/tdc_core/reg_control_block/Pulse_stretcher/counter<1>
+ cmp_tdc2/tdc_core/reg_control_block/Pulse_stretcher/counter_2
------------------------------------------------- ---------------------------
- Total 0.380ns (0.145ns logic, 0.235ns route)
- (38.2% logic, 61.8% route)
+ Total 0.329ns (0.059ns logic, 0.270ns route)
+ (17.9% logic, 82.1% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA_1 (SLICE_X110Y78.C5), 1 path
+Paths for end point cmp_tdc2/tdc_core/reg_control_block/Pulse_stretcher/counter_0 (SLICE_X59Y24.SR), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.381ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc2/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA_0 (FF)
- Destination: cmp_tdc2/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA_1 (FF)
+Slack (hold path): 0.326ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc2/tdc_core/reg_control_block/ctrl_reg_11 (FF)
+ Destination: cmp_tdc2/tdc_core/reg_control_block/Pulse_stretcher/counter_0 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.381ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
+ Data Path Delay: 0.330ns (Levels of Logic = 0)
+ Clock Path Skew: 0.004ns (0.067 - 0.063)
Source Clock: tdc2_clk_125m rising at 8.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc2/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA_0 to cmp_tdc2/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA_1
+ Minimum Data Path at Fast Process Corner: cmp_tdc2/tdc_core/reg_control_block/ctrl_reg_11 to cmp_tdc2/tdc_core/reg_control_block/Pulse_stretcher/counter_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X110Y78.CQ Tcko 0.200 cmp_tdc2/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA<0>
- cmp_tdc2/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA_0
- SLICE_X110Y78.C5 net (fanout=1) 0.060 cmp_tdc2/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA<0>
- SLICE_X110Y78.CLK Tah (-Th) -0.121 cmp_tdc2/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA<0>
- cmp_tdc2/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/Mmux_bus_status_ctrl.cSDA[0]_GND_362_o_mux_6_OUT21
- cmp_tdc2/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA_1
+ SLICE_X57Y24.DQ Tcko 0.198 cmp_tdc2/tdc_core/reg_control_block/ctrl_reg<11>
+ cmp_tdc2/tdc_core/reg_control_block/ctrl_reg_11
+ SLICE_X59Y24.SR net (fanout=1) 0.270 cmp_tdc2/tdc_core/reg_control_block/ctrl_reg<11>
+ SLICE_X59Y24.CLK Tcksr (-Th) 0.138 cmp_tdc2/tdc_core/reg_control_block/Pulse_stretcher/counter<1>
+ cmp_tdc2/tdc_core/reg_control_block/Pulse_stretcher/counter_0
------------------------------------------------- ---------------------------
- Total 0.381ns (0.321ns logic, 0.060ns route)
- (84.3% logic, 15.7% route)
+ Total 0.330ns (0.060ns logic, 0.270ns route)
+ (18.2% logic, 81.8% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2/tdc_core/data_formatting_block/un_previous_clk_i_cycles_offset_2 (SLICE_X96Y33.C5), 1 path
+Paths for end point cmp_tdc2/tdc_core/reg_control_block/Pulse_stretcher/counter_1 (SLICE_X59Y24.SR), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.387ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc2/tdc_core/start_retrigger_block/clk_i_cycles_offset_2 (FF)
- Destination: cmp_tdc2/tdc_core/data_formatting_block/un_previous_clk_i_cycles_offset_2 (FF)
+Slack (hold path): 0.333ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc2/tdc_core/reg_control_block/ctrl_reg_11 (FF)
+ Destination: cmp_tdc2/tdc_core/reg_control_block/Pulse_stretcher/counter_1 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.387ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
+ Data Path Delay: 0.337ns (Levels of Logic = 0)
+ Clock Path Skew: 0.004ns (0.067 - 0.063)
Source Clock: tdc2_clk_125m rising at 8.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc2/tdc_core/start_retrigger_block/clk_i_cycles_offset_2 to cmp_tdc2/tdc_core/data_formatting_block/un_previous_clk_i_cycles_offset_2
+ Minimum Data Path at Fast Process Corner: cmp_tdc2/tdc_core/reg_control_block/ctrl_reg_11 to cmp_tdc2/tdc_core/reg_control_block/Pulse_stretcher/counter_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X96Y33.CQ Tcko 0.200 cmp_tdc2/tdc_core/start_retrigger_block/clk_i_cycles_offset<3>
- cmp_tdc2/tdc_core/start_retrigger_block/clk_i_cycles_offset_2
- SLICE_X96Y33.C5 net (fanout=2) 0.066 cmp_tdc2/tdc_core/start_retrigger_block/clk_i_cycles_offset<2>
- SLICE_X96Y33.CLK Tah (-Th) -0.121 cmp_tdc2/tdc_core/start_retrigger_block/clk_i_cycles_offset<3>
- cmp_tdc2/tdc_core/start_retrigger_block/clk_i_cycles_offset<2>_rt
- cmp_tdc2/tdc_core/data_formatting_block/un_previous_clk_i_cycles_offset_2
+ SLICE_X57Y24.DQ Tcko 0.198 cmp_tdc2/tdc_core/reg_control_block/ctrl_reg<11>
+ cmp_tdc2/tdc_core/reg_control_block/ctrl_reg_11
+ SLICE_X59Y24.SR net (fanout=1) 0.270 cmp_tdc2/tdc_core/reg_control_block/ctrl_reg<11>
+ SLICE_X59Y24.CLK Tcksr (-Th) 0.131 cmp_tdc2/tdc_core/reg_control_block/Pulse_stretcher/counter<1>
+ cmp_tdc2/tdc_core/reg_control_block/Pulse_stretcher/counter_1
------------------------------------------------- ---------------------------
- Total 0.387ns (0.321ns logic, 0.066ns route)
- (82.9% logic, 17.1% route)
+ Total 0.337ns (0.067ns logic, 0.270ns route)
+ (19.9% logic, 80.1% route)
--------------------------------------------------------------------------------
@@ -2386,7 +2432,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
Logical resource: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X4Y18.CLKA
+ Location pin: RAMB16_X3Y14.CLKA
Clock network: tdc2_clk_125m
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
@@ -2394,7 +2440,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKB)
Physical resource: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
Logical resource: cmp_tdc2/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
- Location pin: RAMB16_X4Y18.CLKB
+ Location pin: RAMB16_X3Y14.CLKB
Clock network: tdc2_clk_125m
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
@@ -2407,7 +2453,7 @@ Slack: 4.876ns (period - min period limit)
--------------------------------------------------------------------------------
-1 constraint not met.
+All constraints were met.
Data Sheet report:
@@ -2419,9 +2465,9 @@ Clock to Setup on destination clock clk_20m_vcxo_i
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
-clk_20m_vcxo_i | 8.849| | | |
-tdc1_125m_clk_n_i| 4.804| | | |
-tdc1_125m_clk_p_i| 4.804| | | |
+clk_20m_vcxo_i | 12.221| | | |
+tdc1_125m_clk_n_i| 6.225| | | |
+tdc1_125m_clk_p_i| 6.225| | | |
-----------------+---------+---------+---------+---------+
Clock to Setup on destination clock tdc1_125m_clk_n_i
@@ -2429,9 +2475,9 @@ Clock to Setup on destination clock tdc1_125m_clk_n_i
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
-clk_20m_vcxo_i | 1.191| | | |
-tdc1_125m_clk_n_i| 8.007| | | |
-tdc1_125m_clk_p_i| 8.007| | | |
+clk_20m_vcxo_i | 1.218| | | |
+tdc1_125m_clk_n_i| 7.749| | | |
+tdc1_125m_clk_p_i| 7.749| | | |
-----------------+---------+---------+---------+---------+
Clock to Setup on destination clock tdc1_125m_clk_p_i
@@ -2439,9 +2485,9 @@ Clock to Setup on destination clock tdc1_125m_clk_p_i
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
-clk_20m_vcxo_i | 1.191| | | |
-tdc1_125m_clk_n_i| 8.007| | | |
-tdc1_125m_clk_p_i| 8.007| | | |
+clk_20m_vcxo_i | 1.218| | | |
+tdc1_125m_clk_n_i| 7.749| | | |
+tdc1_125m_clk_p_i| 7.749| | | |
-----------------+---------+---------+---------+---------+
Clock to Setup on destination clock tdc2_125m_clk_n_i
@@ -2449,8 +2495,8 @@ Clock to Setup on destination clock tdc2_125m_clk_n_i
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
-tdc2_125m_clk_n_i| 7.742| | | |
-tdc2_125m_clk_p_i| 7.742| | | |
+tdc2_125m_clk_n_i| 7.764| | | |
+tdc2_125m_clk_p_i| 7.764| | | |
-----------------+---------+---------+---------+---------+
Clock to Setup on destination clock tdc2_125m_clk_p_i
@@ -2458,27 +2504,27 @@ Clock to Setup on destination clock tdc2_125m_clk_p_i
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
-tdc2_125m_clk_n_i| 7.742| | | |
-tdc2_125m_clk_p_i| 7.742| | | |
+tdc2_125m_clk_n_i| 7.764| | | |
+tdc2_125m_clk_p_i| 7.764| | | |
-----------------+---------+---------+---------+---------+
Timing summary:
---------------
-Timing errors: 1 Score: 7 (Setup/Max: 7, Hold: 0)
+Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
-Constraints cover 1086201 paths, 0 nets, and 24071 connections
+Constraints cover 1086201 paths, 0 nets, and 24079 connections
Design statistics:
- Minimum period: 8.849ns{1} (Maximum frequency: 113.007MHz)
- Maximum path delay from/to any node: 6.134ns
+ Minimum period: 12.221ns{1} (Maximum frequency: 81.826MHz)
+ Maximum path delay from/to any node: 7.445ns
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
-Analysis completed Fri Nov 22 14:58:25 2013
+Analysis completed Thu Nov 28 15:41:43 2013
--------------------------------------------------------------------------------
Trace Settings:
diff --git a/hdl/syn/svec/top_tdc_summary.html b/hdl/syn/svec/top_tdc_summary.html
index 96c3f449ff971a5793bdad0933e71cba5753b41f..2ef8f2aba1d60f9a43514287b0776e8eae9a4976 100644
--- a/hdl/syn/svec/top_tdc_summary.html
+++ b/hdl/syn/svec/top_tdc_summary.html
@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>top_tdc Project Status (11/22/2013 - 14:59:27)</B></TD></TR>
+<TD ALIGN=CENTER COLSPAN='4'><B>top_tdc Project Status (11/28/2013 - 15:42:49)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>svec-tdc-fmc.xise</TD>
@@ -25,7 +25,7 @@ No Errors</TD>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
-<TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/*.xmsgs?&DataKey=Warning'>3330 Warnings (3317 new)</A></TD>
+<TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/*.xmsgs?&DataKey=Warning'>3325 Warnings (3303 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
@@ -39,8 +39,7 @@ No Errors</TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>
-<font color="red"; face="Arial"><b>X </b></font>
-<A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.ptwx?&DataKey=ConstraintsData'>1 Failing Constraint</A></TD>
+<A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
@@ -49,7 +48,7 @@ No Errors</TD>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
-<TD>7 <A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
+<TD>0 <A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
</TR>
</TABLE>
@@ -61,13 +60,13 @@ System Settings</A>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
-<TD ALIGN=RIGHT>6,532</TD>
+<TD ALIGN=RIGHT>6,526</TD>
<TD ALIGN=RIGHT>184,304</TD>
<TD ALIGN=RIGHT>3%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD>
-<TD ALIGN=RIGHT>6,486</TD>
+<TD ALIGN=RIGHT>6,480</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
@@ -91,31 +90,31 @@ System Settings</A>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
-<TD ALIGN=RIGHT>9,239</TD>
+<TD ALIGN=RIGHT>9,248</TD>
<TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>10%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD>
-<TD ALIGN=RIGHT>8,951</TD>
+<TD ALIGN=RIGHT>8,960</TD>
<TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>9%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
-<TD ALIGN=RIGHT>5,945</TD>
+<TD ALIGN=RIGHT>5,957</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
-<TD ALIGN=RIGHT>387</TD>
+<TD ALIGN=RIGHT>409</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
-<TD ALIGN=RIGHT>2,619</TD>
+<TD ALIGN=RIGHT>2,594</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
@@ -175,13 +174,13 @@ System Settings</A>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice register load</TD>
-<TD ALIGN=RIGHT>177</TD>
+<TD ALIGN=RIGHT>176</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice carry load</TD>
-<TD ALIGN=RIGHT>74</TD>
+<TD ALIGN=RIGHT>75</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
@@ -193,7 +192,7 @@ System Settings</A>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
-<TD ALIGN=RIGHT>3,678</TD>
+<TD ALIGN=RIGHT>3,647</TD>
<TD ALIGN=RIGHT>23,038</TD>
<TD ALIGN=RIGHT>15%</TD>
<TD COLSPAN='2'> </TD>
@@ -205,37 +204,37 @@ System Settings</A>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
-<TD ALIGN=RIGHT>10,525</TD>
+<TD ALIGN=RIGHT>10,494</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD>
-<TD ALIGN=RIGHT>4,788</TD>
-<TD ALIGN=RIGHT>10,525</TD>
+<TD ALIGN=RIGHT>4,755</TD>
+<TD ALIGN=RIGHT>10,494</TD>
<TD ALIGN=RIGHT>45%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD>
-<TD ALIGN=RIGHT>1,286</TD>
-<TD ALIGN=RIGHT>10,525</TD>
-<TD ALIGN=RIGHT>12%</TD>
+<TD ALIGN=RIGHT>1,246</TD>
+<TD ALIGN=RIGHT>10,494</TD>
+<TD ALIGN=RIGHT>11%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD>
-<TD ALIGN=RIGHT>4,451</TD>
-<TD ALIGN=RIGHT>10,525</TD>
+<TD ALIGN=RIGHT>4,493</TD>
+<TD ALIGN=RIGHT>10,494</TD>
<TD ALIGN=RIGHT>42%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD>
-<TD ALIGN=RIGHT>207</TD>
+<TD ALIGN=RIGHT>208</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of slice register sites lost<BR> to control set restrictions</TD>
-<TD ALIGN=RIGHT>363</TD>
+<TD ALIGN=RIGHT>369</TD>
<TD ALIGN=RIGHT>184,304</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'> </TD>
@@ -446,7 +445,7 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
-<TD>7 (Setup: 7, Hold: 0, Component Switching Limit: 0)</TD>
+<TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD>
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
</TR>
@@ -459,8 +458,7 @@ System Settings</A>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
<TD>
-<font color="red"; face="Arial"><b>X </b></font>
-<A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.ptwx?&DataKey=ConstraintsData'>1 Failing Constraint</A></TD>
+<A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD BGCOLOR='#FFFF99'><B> </B></TD>
<TD COLSPAN='2'> </TD>
</TABLE>
@@ -471,21 +469,21 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Nov 22 14:50:53 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/xst.xmsgs?&DataKey=Warning'>3318 Warnings (3317 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/xst.xmsgs?&DataKey=Info'>135 Infos (135 new)</A></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Nov 22 14:51:09 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri Nov 22 14:54:42 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/map.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/map.xmsgs?&DataKey=Info'>279 Infos (0 new)</A></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri Nov 22 14:58:03 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/par.xmsgs?&DataKey=Warning'>7 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/par.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Thu Nov 28 15:35:36 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/xst.xmsgs?&DataKey=Warning'>3314 Warnings (3303 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/xst.xmsgs?&DataKey=Info'>131 Infos (131 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Nov 28 15:35:53 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu Nov 28 15:39:22 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/map.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/map.xmsgs?&DataKey=Info'>279 Infos (0 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Thu Nov 28 15:41:21 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/par.xmsgs?&DataKey=Warning'>6 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/par.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Fri Nov 22 14:58:25 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/trce.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Fri Nov 22 14:59:18 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/bitgen.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Thu Nov 28 15:41:43 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/trce.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Thu Nov 28 15:42:40 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/bitgen.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
</TABLE>
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri Nov 22 14:59:19 2013</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri Nov 22 14:59:26 2013</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Nov 28 15:42:40 2013</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Nov 28 15:42:48 2013</TD></TR>
</TABLE>
-<br><center><b>Date Generated:</b> 11/22/2013 - 14:59:27</center>
+<br><center><b>Date Generated:</b> 11/28/2013 - 15:42:49</center>
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