From 9990db8c0d0ce9f7bec0123c4cabfc17b746d0f4 Mon Sep 17 00:00:00 2001
From: egousiou <egousiou@85dfdc96-de2c-444c-878d-45b388be74a9>
Date: Thu, 5 Jun 2014 17:05:39 +0000
Subject: [PATCH] white rabbit svec working! (code needs revamping though)
git-svn-id: http://svn.ohwr.org/fmc-tdc@169 85dfdc96-de2c-444c-878d-45b388be74a9
---
.../hdl/syn/svec/svec_top_fmc_tdc.twr | 1936 +++++++++--------
.../hdl/syn/svec/svec_top_fmc_tdc.xise | 2 +-
.../hdl/syn/svec/svec_top_fmc_tdc_map.mrp | 1532 +------------
hdl/wrabbit_tdc/hdl/top/svec/svec_tdc.ucf | 25 +
.../hdl/top/svec/svec_top_fmc_tdc.vhd | 4 +-
5 files changed, 1194 insertions(+), 2305 deletions(-)
diff --git a/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc.twr b/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc.twr
index 18e2782..c522b32 100644
--- a/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc.twr
+++ b/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc.twr
@@ -42,170 +42,171 @@ Timing constraint: ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP "tdc1_clk_125m" TO
TIMEGRP "clk_62m5_sys" 20 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).
- 38 paths analyzed, 36 endpoints analyzed, 0 failing endpoints
+ 40 paths analyzed, 38 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is 6.270ns.
+ Maximum delay is 5.678ns.
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_2 (SLICE_X36Y75.CX), 1 path
+Paths for end point cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_3 (SLICE_X40Y74.BX), 1 path
--------------------------------------------------------------------------------
-Slack (setup paths): 13.730ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_2 (FF)
- Destination: cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_2 (FF)
+Slack (setup paths): 14.322ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_3 (FF)
+ Destination: cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_3 (FF)
Requirement: 20.000ns
- Data Path Delay: 6.270ns (Levels of Logic = 0)
+ Data Path Delay: 5.678ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: clk_62m5_sys rising
Clock Uncertainty: 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_2 to cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_2
+ Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_3 to cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X95Y128.BQ Tcko 0.391 cmp_tdc1_clks_crossing/sfifo/w_idx_gray<2>
- cmp_tdc1_clks_crossing/sfifo/w_idx_gray_2
- SLICE_X36Y75.CX net (fanout=1) 5.924 cmp_tdc1_clks_crossing/sfifo/w_idx_gray<2>
- SLICE_X36Y75.CLK Tds -0.045 cmp_tdc2_clks_crossing/mfifo/r_idx_shift_w_3<1>
- cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_2
+ SLICE_X88Y127.BMUX Tshcko 0.455 cmp_tdc1_clks_crossing/sfifo/w_idx_bnry<2>
+ cmp_tdc1_clks_crossing/sfifo/w_idx_gray_3
+ SLICE_X40Y74.BX net (fanout=1) 5.303 cmp_tdc1_clks_crossing/sfifo/w_idx_gray<3>
+ SLICE_X40Y74.CLK Tds -0.080 cmp_tdc2_clks_crossing/mfifo/r_idx_shift_w_3<2>
+ cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_3
------------------------------------------------- ---------------------------
- Total 6.270ns (0.346ns logic, 5.924ns route)
- (5.5% logic, 94.5% route)
+ Total 5.678ns (0.375ns logic, 5.303ns route)
+ (6.6% logic, 93.4% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_3 (SLICE_X36Y75.BX), 1 path
+Paths for end point cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_2 (SLICE_X40Y74.CX), 1 path
--------------------------------------------------------------------------------
-Slack (setup paths): 13.807ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_3 (FF)
- Destination: cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_3 (FF)
+Slack (setup paths): 14.361ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_2 (FF)
+ Destination: cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_2 (FF)
Requirement: 20.000ns
- Data Path Delay: 6.193ns (Levels of Logic = 0)
+ Data Path Delay: 5.639ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: clk_62m5_sys rising
Clock Uncertainty: 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_3 to cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_3
+ Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_2 to cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X94Y128.BMUX Tshcko 0.488 cmp_tdc1_clks_crossing/sfifo/w_idx_bnry<2>
- cmp_tdc1_clks_crossing/sfifo/w_idx_gray_3
- SLICE_X36Y75.BX net (fanout=1) 5.785 cmp_tdc1_clks_crossing/sfifo/w_idx_gray<3>
- SLICE_X36Y75.CLK Tds -0.080 cmp_tdc2_clks_crossing/mfifo/r_idx_shift_w_3<1>
- cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_3
+ SLICE_X87Y127.BQ Tcko 0.391 cmp_tdc1_clks_crossing/sfifo/w_idx_bnry<3>
+ cmp_tdc1_clks_crossing/sfifo/w_idx_gray_2
+ SLICE_X40Y74.CX net (fanout=1) 5.293 cmp_tdc1_clks_crossing/sfifo/w_idx_gray<2>
+ SLICE_X40Y74.CLK Tds -0.045 cmp_tdc2_clks_crossing/mfifo/r_idx_shift_w_3<2>
+ cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_2
------------------------------------------------- ---------------------------
- Total 6.193ns (0.408ns logic, 5.785ns route)
- (6.6% logic, 93.4% route)
+ Total 5.639ns (0.346ns logic, 5.293ns route)
+ (6.1% logic, 93.9% route)
--------------------------------------------------------------------------------
-Paths for end point tdc1_irq_synch_0 (SLICE_X87Y117.AX), 1 path
+Paths for end point cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_1 (SLICE_X40Y74.DX), 1 path
--------------------------------------------------------------------------------
-Slack (setup paths): 16.767ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1/cmp_tdc_eic/eic_irq_controller_inst/wb_irq_o (FF)
- Destination: tdc1_irq_synch_0 (FF)
+Slack (setup paths): 14.685ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_1 (FF)
+ Destination: cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_1 (FF)
Requirement: 20.000ns
- Data Path Delay: 3.233ns (Levels of Logic = 0)
+ Data Path Delay: 5.315ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: clk_62m5_sys rising
Clock Uncertainty: 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_eic/eic_irq_controller_inst/wb_irq_o to tdc1_irq_synch_0
+ Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_1 to cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X99Y147.DQ Tcko 0.391 cmp_tdc1/cmp_tdc_eic/eic_irq_controller_inst/wb_irq_o
- cmp_tdc1/cmp_tdc_eic/eic_irq_controller_inst/wb_irq_o
- SLICE_X87Y117.AX net (fanout=1) 2.779 cmp_tdc1/cmp_tdc_eic/eic_irq_controller_inst/wb_irq_o
- SLICE_X87Y117.CLK Tdick 0.063 tdc1_irq_synch<1>
- tdc1_irq_synch_0
+ SLICE_X87Y127.AQ Tcko 0.391 cmp_tdc1_clks_crossing/sfifo/w_idx_bnry<3>
+ cmp_tdc1_clks_crossing/sfifo/w_idx_gray_1
+ SLICE_X40Y74.DX net (fanout=1) 5.024 cmp_tdc1_clks_crossing/sfifo/w_idx_gray<1>
+ SLICE_X40Y74.CLK Tds -0.100 cmp_tdc2_clks_crossing/mfifo/r_idx_shift_w_3<2>
+ cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_1
------------------------------------------------- ---------------------------
- Total 3.233ns (0.454ns logic, 2.779ns route)
- (14.0% logic, 86.0% route)
+ Total 5.315ns (0.291ns logic, 5.024ns route)
+ (5.5% logic, 94.5% route)
--------------------------------------------------------------------------------
Hold Paths: ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP "tdc1_clk_125m" TO TIMEGRP "clk_62m5_sys" 20 ns DATAPATHONLY;
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_4 (SLICE_X64Y121.DI), 1 path
+Paths for end point cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_4 (SLICE_X100Y122.AX), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.868ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc1_clks_crossing/mfifo/r_idx_bnry_4 (FF)
- Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_4 (FF)
+Slack (hold path): 0.842ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc1_clks_crossing/sfifo/w_idx_bnry_4 (FF)
+ Destination: cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_4 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.868ns (Levels of Logic = 0)
+ Data Path Delay: 0.842ns (Levels of Logic = 0)
Positive Clock Path Skew: 0.000ns
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: clk_62m5_sys rising
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/mfifo/r_idx_bnry_4 to cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_4
+ Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/sfifo/w_idx_bnry_4 to cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_4
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X69Y130.DQ Tcko 0.198 cmp_tdc1_clks_crossing/mfifo/r_idx_bnry<4>
- cmp_tdc1_clks_crossing/mfifo/r_idx_bnry_4
- SLICE_X64Y121.DI net (fanout=3) 0.637 cmp_tdc1_clks_crossing/mfifo/r_idx_bnry<4>
- SLICE_X64Y121.CLK Tdh (-Th) -0.033 cmp_tdc1_clks_crossing/mfifo/r_idx_shift_w_3<4>
- cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_4
+ SLICE_X88Y127.BQ Tcko 0.200 cmp_tdc1_clks_crossing/sfifo/w_idx_bnry<2>
+ cmp_tdc1_clks_crossing/sfifo/w_idx_bnry_4
+ SLICE_X100Y122.AX net (fanout=2) 0.712 cmp_tdc1_clks_crossing/sfifo/w_idx_bnry<4>
+ SLICE_X100Y122.CLK Tdh (-Th) 0.070 cmp_tdc1_clks_crossing/sfifo/r_idx_shift_a_3<3>
+ cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_4
------------------------------------------------- ---------------------------
- Total 0.868ns (0.231ns logic, 0.637ns route)
- (26.6% logic, 73.4% route)
+ Total 0.842ns (0.130ns logic, 0.712ns route)
+ (15.4% logic, 84.6% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_0 (SLICE_X64Y121.DX), 1 path
+Paths for end point cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_0 (SLICE_X100Y122.DX), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.885ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc1_clks_crossing/mfifo/r_idx_gray_0 (FF)
- Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_0 (FF)
+Slack (hold path): 0.910ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_0 (FF)
+ Destination: cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_0 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.885ns (Levels of Logic = 0)
+ Data Path Delay: 0.910ns (Levels of Logic = 0)
Positive Clock Path Skew: 0.000ns
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: clk_62m5_sys rising
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/mfifo/r_idx_gray_0 to cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_0
+ Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/sfifo/w_idx_gray_0 to cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X68Y129.CMUX Tshcko 0.266 cmp_tdc1_clks_crossing/mfifo/r_idx_bnry<3>
- cmp_tdc1_clks_crossing/mfifo/r_idx_gray_0
- SLICE_X64Y121.DX net (fanout=2) 0.719 cmp_tdc1_clks_crossing/mfifo/r_idx_gray<0>
- SLICE_X64Y121.CLK Tdh (-Th) 0.100 cmp_tdc1_clks_crossing/mfifo/r_idx_shift_w_3<4>
- cmp_tdc1_clks_crossing/mfifo/Mshreg_r_idx_shift_w_3_0
+ SLICE_X88Y127.CMUX Tshcko 0.238 cmp_tdc1_clks_crossing/sfifo/w_idx_bnry<2>
+ cmp_tdc1_clks_crossing/sfifo/w_idx_gray_0
+ SLICE_X100Y122.DX net (fanout=1) 0.772 cmp_tdc1_clks_crossing/sfifo/w_idx_gray<0>
+ SLICE_X100Y122.CLK Tdh (-Th) 0.100 cmp_tdc1_clks_crossing/sfifo/r_idx_shift_a_3<3>
+ cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_0
------------------------------------------------- ---------------------------
- Total 0.885ns (0.166ns logic, 0.719ns route)
- (18.8% logic, 81.2% route)
+ Total 0.910ns (0.138ns logic, 0.772ns route)
+ (15.2% logic, 84.8% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_4 (SLICE_X94Y113.BX), 1 path
+Paths for end point cmp_tdc1_clks_rsts_mgment/dac_word_22 (SLICE_X91Y141.D5), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.885ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc1_clks_crossing/sfifo/w_idx_bnry_4 (FF)
- Destination: cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_4 (FF)
+Slack (hold path): 0.932ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc1/cmp_tdc_core/reg_control_block/dac_word_22 (FF)
+ Destination: cmp_tdc1_clks_rsts_mgment/dac_word_22 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.885ns (Levels of Logic = 0)
+ Data Path Delay: 0.932ns (Levels of Logic = 1)
Positive Clock Path Skew: 0.000ns
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: clk_62m5_sys rising
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/sfifo/w_idx_bnry_4 to cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_4
+ Minimum Data Path at Fast Process Corner: cmp_tdc1/cmp_tdc_core/reg_control_block/dac_word_22 to cmp_tdc1_clks_rsts_mgment/dac_word_22
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X94Y128.BQ Tcko 0.234 cmp_tdc1_clks_crossing/sfifo/w_idx_bnry<2>
- cmp_tdc1_clks_crossing/sfifo/w_idx_bnry_4
- SLICE_X94Y113.BX net (fanout=2) 0.731 cmp_tdc1_clks_crossing/sfifo/w_idx_bnry<4>
- SLICE_X94Y113.CLK Tdh (-Th) 0.080 cmp_tdc1_clks_crossing/sfifo/r_idx_shift_a_3<1>
- cmp_tdc1_clks_crossing/sfifo/Mshreg_w_idx_shift_r_3_4
+ SLICE_X96Y150.CQ Tcko 0.200 cmp_tdc1/cmp_tdc_core/reg_control_block/dac_word<23>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/dac_word_22
+ SLICE_X91Y141.D5 net (fanout=2) 0.577 cmp_tdc1/cmp_tdc_core/reg_control_block/dac_word<22>
+ SLICE_X91Y141.CLK Tah (-Th) -0.155 cmp_tdc1_clks_rsts_mgment/dac_word<23>
+ cmp_tdc1_clks_rsts_mgment/Mmux_dac_word[23]_dac_word_i[23]_mux_15_OUT151
+ cmp_tdc1_clks_rsts_mgment/dac_word_22
------------------------------------------------- ---------------------------
- Total 0.885ns (0.154ns logic, 0.731ns route)
- (17.4% logic, 82.6% route)
+ Total 0.932ns (0.355ns logic, 0.577ns route)
+ (38.1% logic, 61.9% route)
--------------------------------------------------------------------------------
================================================================================
@@ -213,170 +214,203 @@ Timing constraint: ts_ignore_xclock3 = MAXDELAY FROM TIMEGRP "clk_62m5_sys" TO
TIMEGRP "tdc1_clk_125m" 20 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).
- 6 paths analyzed, 6 endpoints analyzed, 0 failing endpoints
+ 20 paths analyzed, 19 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is 3.855ns.
+ Maximum delay is 7.299ns.
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_rsts_mgment/Mshreg_internal_rst_synch_1 (SLICE_X60Y172.DI), 1 path
+Paths for end point cmp_tdc1/wrabbit_utc_p (SLICE_X93Y104.AX), 1 path
--------------------------------------------------------------------------------
-Slack (setup paths): 16.145ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1_clks_rsts_mgment/rst (FF)
- Destination: cmp_tdc1_clks_rsts_mgment/Mshreg_internal_rst_synch_1 (FF)
+Slack (setup paths): 12.701ns (requirement - (data path - clock path skew + uncertainty))
+ Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int_1 (FF)
+ Destination: cmp_tdc1/wrabbit_utc_p (FF)
Requirement: 20.000ns
- Data Path Delay: 3.855ns (Levels of Logic = 0)
+ Data Path Delay: 7.299ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: tdc1_clk_125m rising at 0.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_rsts_mgment/rst to cmp_tdc1_clks_rsts_mgment/Mshreg_internal_rst_synch_1
+ Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int_1 to cmp_tdc1/wrabbit_utc_p
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X23Y172.BQ Tcko 0.391 cmp_tdc1_clks_rsts_mgment/rst
- cmp_tdc1_clks_rsts_mgment/rst
- SLICE_X60Y172.DI net (fanout=1) 3.436 cmp_tdc1_clks_rsts_mgment/rst
- SLICE_X60Y172.CLK Tds 0.028 cmp_tdc1_clks_rsts_mgment/internal_rst_synch<1>
- cmp_tdc1_clks_rsts_mgment/Mshreg_internal_rst_synch_1
+ SLICE_X54Y105.BQ Tcko 0.408 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int<3>
+ U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int_1
+ SLICE_X69Y70.D2 net (fanout=6) 3.262 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int<1>
+ SLICE_X69Y70.DMUX Tilo 0.313 cmp_tdc2/wrabbit_utc_p
+ cmp_tdc1/wrabbit_utc_p_rstpot
+ SLICE_X93Y104.AX net (fanout=1) 3.253 cmp_tdc1/wrabbit_utc_p_rstpot
+ SLICE_X93Y104.CLK Tdick 0.063 cmp_tdc1/wrabbit_utc_p
+ cmp_tdc1/wrabbit_utc_p
------------------------------------------------- ---------------------------
- Total 3.855ns (0.419ns logic, 3.436ns route)
- (10.9% logic, 89.1% route)
+ Total 7.299ns (0.784ns logic, 6.515ns route)
+ (10.7% logic, 89.3% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_0 (SLICE_X64Y130.AX), 1 path
+Paths for end point cmp_tdc1/cmp_wrabbit_synch/link_up_0 (SLICE_X96Y153.AX), 2 paths
--------------------------------------------------------------------------------
-Slack (setup paths): 18.716ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_0 (FF)
- Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_0 (FF)
+Slack (setup paths): 13.980ns (requirement - (data path - clock path skew + uncertainty))
+ Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_los/sync2 (FF)
+ Destination: cmp_tdc1/cmp_wrabbit_synch/link_up_0 (FF)
Requirement: 20.000ns
- Data Path Delay: 1.284ns (Levels of Logic = 0)
+ Data Path Delay: 6.020ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: tdc1_clk_125m rising at 0.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_0 to cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_0
+ Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_los/sync2 to cmp_tdc1/cmp_wrabbit_synch/link_up_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X64Y124.DMUX Tshcko 0.488 cmp_tdc1_clks_crossing/mfifo/w_idx_bnry<1>
- cmp_tdc1_clks_crossing/mfifo/w_idx_gray_0
- SLICE_X64Y130.AX net (fanout=2) 0.856 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<0>
- SLICE_X64Y130.CLK Tds -0.060 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
- cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_0
+ SLICE_X54Y107.AQ Tcko 0.408 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_los/sync2
+ U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_los/sync2
+ SLICE_X55Y120.A3 net (fanout=5) 1.178 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_los/sync2
+ SLICE_X55Y120.A Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/link_ok
+ U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/link_ok_o1
+ SLICE_X96Y153.AX net (fanout=8) 4.039 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/link_ok
+ SLICE_X96Y153.CLK Tdick 0.136 cmp_tdc1/cmp_wrabbit_synch/link_up<1>
+ cmp_tdc1/cmp_wrabbit_synch/link_up_0
------------------------------------------------- ---------------------------
- Total 1.284ns (0.428ns logic, 0.856ns route)
- (33.3% logic, 66.7% route)
+ Total 6.020ns (0.803ns logic, 5.217ns route)
+ (13.3% logic, 86.7% route)
--------------------------------------------------------------------------------
+Slack (setup paths): 14.533ns (requirement - (data path - clock path skew + uncertainty))
+ Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/pcs_link_ok_o (FF)
+ Destination: cmp_tdc1/cmp_wrabbit_synch/link_up_0 (FF)
+ Requirement: 20.000ns
+ Data Path Delay: 5.467ns (Levels of Logic = 1)
+ Clock Path Skew: 0.000ns
+ Source Clock: clk_62m5_sys rising
+ Destination Clock: tdc1_clk_125m rising at 0.000ns
+ Clock Uncertainty: 0.000ns
-Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_3 (SLICE_X64Y130.BI), 1 path
+ Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/pcs_link_ok_o to cmp_tdc1/cmp_wrabbit_synch/link_up_0
+ Location Delay type Delay(ns) Physical Resource
+ Logical Resource(s)
+ ------------------------------------------------- -------------------
+ SLICE_X65Y120.DQ Tcko 0.391 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/pcs_link_ok_o
+ U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/pcs_link_ok_o
+ SLICE_X55Y120.A5 net (fanout=4) 0.642 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/pcs_link_ok_o
+ SLICE_X55Y120.A Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/link_ok
+ U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/link_ok_o1
+ SLICE_X96Y153.AX net (fanout=8) 4.039 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/link_ok
+ SLICE_X96Y153.CLK Tdick 0.136 cmp_tdc1/cmp_wrabbit_synch/link_up<1>
+ cmp_tdc1/cmp_wrabbit_synch/link_up_0
+ ------------------------------------------------- ---------------------------
+ Total 5.467ns (0.786ns logic, 4.681ns route)
+ (14.4% logic, 85.6% route)
+
+--------------------------------------------------------------------------------
+
+Paths for end point cmp_tdc1/cmp_wrabbit_synch/clk_aux_locked_0 (SLICE_X97Y151.AX), 1 path
--------------------------------------------------------------------------------
-Slack (setup paths): 18.774ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_3 (FF)
- Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_3 (FF)
+Slack (setup paths): 14.899ns (requirement - (data path - clock path skew + uncertainty))
+ Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int_1 (FF)
+ Destination: cmp_tdc1/cmp_wrabbit_synch/clk_aux_locked_0 (FF)
Requirement: 20.000ns
- Data Path Delay: 1.226ns (Levels of Logic = 0)
+ Data Path Delay: 5.101ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: tdc1_clk_125m rising at 0.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_3 to cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_3
+ Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int_1 to cmp_tdc1/cmp_wrabbit_synch/clk_aux_locked_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X64Y124.BMUX Tshcko 0.488 cmp_tdc1_clks_crossing/mfifo/w_idx_bnry<1>
- cmp_tdc1_clks_crossing/mfifo/w_idx_gray_3
- SLICE_X64Y130.BI net (fanout=2) 0.708 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<3>
- SLICE_X64Y130.CLK Tds 0.030 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
- cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_3
+ SLICE_X54Y105.BQ Tcko 0.408 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int<3>
+ U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int_1
+ SLICE_X97Y151.AX net (fanout=6) 4.630 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int<1>
+ SLICE_X97Y151.CLK Tdick 0.063 cmp_tdc1/cmp_wrabbit_synch/clk_aux_locked<1>
+ cmp_tdc1/cmp_wrabbit_synch/clk_aux_locked_0
------------------------------------------------- ---------------------------
- Total 1.226ns (0.518ns logic, 0.708ns route)
- (42.3% logic, 57.7% route)
+ Total 5.101ns (0.471ns logic, 4.630ns route)
+ (9.2% logic, 90.8% route)
--------------------------------------------------------------------------------
Hold Paths: ts_ignore_xclock3 = MAXDELAY FROM TIMEGRP "clk_62m5_sys" TO TIMEGRP "tdc1_clk_125m" 20 ns DATAPATHONLY;
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_2 (SLICE_X64Y130.CI), 1 path
+Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_1 (SLICE_X90Y147.DI), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.605ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_2 (FF)
- Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_2 (FF)
+Slack (hold path): 0.656ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_1 (FF)
+ Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_1 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.605ns (Levels of Logic = 0)
+ Data Path Delay: 0.656ns (Levels of Logic = 0)
Positive Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: tdc1_clk_125m rising at 0.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_2 to cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_2
+ Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_1 to cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X64Y125.BQ Tcko 0.234 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<2>
- cmp_tdc1_clks_crossing/mfifo/w_idx_gray_2
- SLICE_X64Y130.CI net (fanout=2) 0.321 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<2>
- SLICE_X64Y130.CLK Tdh (-Th) -0.050 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
- cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_2
+ SLICE_X98Y145.CQ Tcko 0.200 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<2>
+ cmp_tdc1_clks_crossing/mfifo/w_idx_gray_1
+ SLICE_X90Y147.DI net (fanout=2) 0.423 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<1>
+ SLICE_X90Y147.CLK Tdh (-Th) -0.033 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
+ cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_1
------------------------------------------------- ---------------------------
- Total 0.605ns (0.284ns logic, 0.321ns route)
- (46.9% logic, 53.1% route)
+ Total 0.656ns (0.233ns logic, 0.423ns route)
+ (35.5% logic, 64.5% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_4 (SLICE_X64Y130.AI), 1 path
+Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_2 (SLICE_X90Y147.AI), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.616ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc1_clks_crossing/mfifo/w_idx_bnry_4 (FF)
- Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_4 (FF)
+Slack (hold path): 0.686ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_2 (FF)
+ Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_2 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.616ns (Levels of Logic = 0)
+ Data Path Delay: 0.686ns (Levels of Logic = 0)
Positive Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: tdc1_clk_125m rising at 0.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/mfifo/w_idx_bnry_4 to cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_4
+ Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_2 to cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X64Y124.BQ Tcko 0.234 cmp_tdc1_clks_crossing/mfifo/w_idx_bnry<1>
- cmp_tdc1_clks_crossing/mfifo/w_idx_bnry_4
- SLICE_X64Y130.AI net (fanout=3) 0.352 cmp_tdc1_clks_crossing/mfifo/w_idx_bnry<4>
- SLICE_X64Y130.CLK Tdh (-Th) -0.030 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
- cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_4
+ SLICE_X98Y145.DQ Tcko 0.200 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<2>
+ cmp_tdc1_clks_crossing/mfifo/w_idx_gray_2
+ SLICE_X90Y147.AI net (fanout=2) 0.456 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<2>
+ SLICE_X90Y147.CLK Tdh (-Th) -0.030 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
+ cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_2
------------------------------------------------- ---------------------------
- Total 0.616ns (0.264ns logic, 0.352ns route)
- (42.9% logic, 57.1% route)
+ Total 0.686ns (0.230ns logic, 0.456ns route)
+ (33.5% logic, 66.5% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_1 (SLICE_X64Y130.DI), 1 path
+Paths for end point cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_0 (SLICE_X90Y147.AX), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.616ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_1 (FF)
- Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_1 (FF)
+Slack (hold path): 0.717ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_0 (FF)
+ Destination: cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_0 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.616ns (Levels of Logic = 0)
+ Data Path Delay: 0.717ns (Levels of Logic = 0)
Positive Clock Path Skew: 0.000ns
Source Clock: clk_62m5_sys rising
Destination Clock: tdc1_clk_125m rising at 0.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_1 to cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_1
+ Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_crossing/mfifo/w_idx_gray_0 to cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X64Y125.AQ Tcko 0.234 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<2>
- cmp_tdc1_clks_crossing/mfifo/w_idx_gray_1
- SLICE_X64Y130.DI net (fanout=2) 0.349 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<1>
- SLICE_X64Y130.CLK Tdh (-Th) -0.033 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
- cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_1
+ SLICE_X99Y145.DMUX Tshcko 0.244 cmp_tdc1_clks_crossing/mfifo/w_idx_bnry<1>
+ cmp_tdc1_clks_crossing/mfifo/w_idx_gray_0
+ SLICE_X90Y147.AX net (fanout=2) 0.543 cmp_tdc1_clks_crossing/mfifo/w_idx_gray<0>
+ SLICE_X90Y147.CLK Tdh (-Th) 0.070 cmp_tdc1_clks_crossing/mfifo/w_idx_shift_r_3<1>
+ cmp_tdc1_clks_crossing/mfifo/Mshreg_w_idx_shift_r_3_0
------------------------------------------------- ---------------------------
- Total 0.616ns (0.267ns logic, 0.349ns route)
- (43.3% logic, 56.7% route)
+ Total 0.717ns (0.174ns logic, 0.543ns route)
+ (24.3% logic, 75.7% route)
--------------------------------------------------------------------------------
================================================================================
@@ -396,7 +430,7 @@ Slack: 1.750ns (period - min period limit)
Min period limit: 6.250ns (160.000MHz) (Tgtpcper_TXUSRCLK)
Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK20
Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK20
- Location pin: GTPA1_DUAL_X0Y0.TXUSRCLK20
+ Location pin: GTPA1_DUAL_X1Y1.TXUSRCLK20
Clock network: clk_125m_pllref_BUFG
--------------------------------------------------------------------------------
Slack: 1.750ns (period - min period limit)
@@ -404,7 +438,7 @@ Slack: 1.750ns (period - min period limit)
Min period limit: 6.250ns (160.000MHz) (Tgtpcper_TXUSRCLK)
Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK21
Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK21
- Location pin: GTPA1_DUAL_X0Y0.TXUSRCLK21
+ Location pin: GTPA1_DUAL_X1Y1.TXUSRCLK21
Clock network: clk_125m_pllref_BUFG
--------------------------------------------------------------------------------
Slack: 4.875ns (period - min period limit)
@@ -412,7 +446,7 @@ Slack: 4.875ns (period - min period limit)
Min period limit: 3.125ns (320.000MHz) (Tgtpcper_TXUSRCLK)
Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK0
Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK0
- Location pin: GTPA1_DUAL_X0Y0.TXUSRCLK0
+ Location pin: GTPA1_DUAL_X1Y1.TXUSRCLK0
Clock network: clk_125m_pllref_BUFG
--------------------------------------------------------------------------------
@@ -421,9 +455,201 @@ Timing constraint: TS_clk_125m_pllref_p_i = PERIOD TIMEGRP
"clk_125m_pllref_p_i" 8 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 6.250ns.
+ 9020 paths analyzed, 1721 endpoints analyzed, 0 failing endpoints
+ 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
+ Minimum period is 6.812ns.
+--------------------------------------------------------------------------------
+
+Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_f_1 (SLICE_X68Y125.SR), 1 path
+--------------------------------------------------------------------------------
+Slack (setup path): 0.594ns (requirement - (data path - clock path skew + uncertainty))
+ Source: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2 (FF)
+ Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_f_1 (FF)
+ Requirement: 4.000ns
+ Data Path Delay: 3.368ns (Levels of Logic = 1)
+ Clock Path Skew: -0.003ns (0.244 - 0.247)
+ Source Clock: clk_125m_pllref_BUFG rising at 0.000ns
+ Destination Clock: clk_125m_pllref_BUFG falling at 4.000ns
+ Clock Uncertainty: 0.035ns
+
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.070ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_f_1
+ Location Delay type Delay(ns) Physical Resource
+ Logical Resource(s)
+ ------------------------------------------------- -------------------
+ SLICE_X72Y120.AQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_sync_tx_en/sync2
+ U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2
+ SLICE_X74Y114.A6 net (fanout=7) 0.766 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2
+ SLICE_X74Y114.A Tilo 0.205 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv
+ U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv1_INV_0
+ SLICE_X68Y125.SR net (fanout=25) 1.508 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv
+ SLICE_X68Y125.CLK Tsrck 0.442 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_f<3>
+ U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_f_1
+ ------------------------------------------------- ---------------------------
+ Total 3.368ns (1.094ns logic, 2.274ns route)
+ (32.5% logic, 67.5% route)
+
+--------------------------------------------------------------------------------
+
+Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_f_3 (SLICE_X68Y125.SR), 1 path
+--------------------------------------------------------------------------------
+Slack (setup path): 0.597ns (requirement - (data path - clock path skew + uncertainty))
+ Source: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2 (FF)
+ Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_f_3 (FF)
+ Requirement: 4.000ns
+ Data Path Delay: 3.365ns (Levels of Logic = 1)
+ Clock Path Skew: -0.003ns (0.244 - 0.247)
+ Source Clock: clk_125m_pllref_BUFG rising at 0.000ns
+ Destination Clock: clk_125m_pllref_BUFG falling at 4.000ns
+ Clock Uncertainty: 0.035ns
+
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.070ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_f_3
+ Location Delay type Delay(ns) Physical Resource
+ Logical Resource(s)
+ ------------------------------------------------- -------------------
+ SLICE_X72Y120.AQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_sync_tx_en/sync2
+ U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2
+ SLICE_X74Y114.A6 net (fanout=7) 0.766 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2
+ SLICE_X74Y114.A Tilo 0.205 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv
+ U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv1_INV_0
+ SLICE_X68Y125.SR net (fanout=25) 1.508 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv
+ SLICE_X68Y125.CLK Tsrck 0.439 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_f<3>
+ U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_f_3
+ ------------------------------------------------- ---------------------------
+ Total 3.365ns (1.091ns logic, 2.274ns route)
+ (32.4% logic, 67.6% route)
+
+--------------------------------------------------------------------------------
+
+Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_f_2 (SLICE_X68Y125.SR), 1 path
+--------------------------------------------------------------------------------
+Slack (setup path): 0.605ns (requirement - (data path - clock path skew + uncertainty))
+ Source: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2 (FF)
+ Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_f_2 (FF)
+ Requirement: 4.000ns
+ Data Path Delay: 3.357ns (Levels of Logic = 1)
+ Clock Path Skew: -0.003ns (0.244 - 0.247)
+ Source Clock: clk_125m_pllref_BUFG rising at 0.000ns
+ Destination Clock: clk_125m_pllref_BUFG falling at 4.000ns
+ Clock Uncertainty: 0.035ns
+
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.070ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_f_2
+ Location Delay type Delay(ns) Physical Resource
+ Logical Resource(s)
+ ------------------------------------------------- -------------------
+ SLICE_X72Y120.AQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_sync_tx_en/sync2
+ U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2
+ SLICE_X74Y114.A6 net (fanout=7) 0.766 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2
+ SLICE_X74Y114.A Tilo 0.205 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv
+ U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv1_INV_0
+ SLICE_X68Y125.SR net (fanout=25) 1.508 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv
+ SLICE_X68Y125.CLK Tsrck 0.431 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_f<3>
+ U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_f_2
+ ------------------------------------------------- ---------------------------
+ Total 3.357ns (1.083ns logic, 2.274ns route)
+ (32.3% logic, 67.7% route)
+
+--------------------------------------------------------------------------------
+
+Hold Paths: TS_clk_125m_pllref_p_i = PERIOD TIMEGRP "clk_125m_pllref_p_i" 8 ns HIGH 50%;
+--------------------------------------------------------------------------------
+
+Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_r_7 (SLICE_X60Y127.CE), 1 path
+--------------------------------------------------------------------------------
+Slack (hold path): 0.325ns (requirement - (clock path skew + uncertainty - data path))
+ Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/ppulse_o (FF)
+ Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_r_7 (FF)
+ Requirement: 0.000ns
+ Data Path Delay: 0.329ns (Levels of Logic = 0)
+ Clock Path Skew: 0.004ns (0.079 - 0.075)
+ Source Clock: clk_125m_pllref_BUFG rising at 8.000ns
+ Destination Clock: clk_125m_pllref_BUFG rising at 8.000ns
+ Clock Uncertainty: 0.000ns
+
+ Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/ppulse_o to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_r_7
+ Location Delay type Delay(ns) Physical Resource
+ Logical Resource(s)
+ ------------------------------------------------- -------------------
+ SLICE_X63Y126.DQ Tcko 0.198 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/ppulse_o
+ U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/ppulse_o
+ SLICE_X60Y127.CE net (fanout=10) 0.239 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/ppulse_o
+ SLICE_X60Y127.CLK Tckce (-Th) 0.108 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_r<7>
+ U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_r_7
+ ------------------------------------------------- ---------------------------
+ Total 0.329ns (0.090ns logic, 0.239ns route)
+ (27.4% logic, 72.6% route)
+
+--------------------------------------------------------------------------------
+
+Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_r_6 (SLICE_X60Y127.CE), 1 path
+--------------------------------------------------------------------------------
+Slack (hold path): 0.329ns (requirement - (clock path skew + uncertainty - data path))
+ Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/ppulse_o (FF)
+ Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_r_6 (FF)
+ Requirement: 0.000ns
+ Data Path Delay: 0.333ns (Levels of Logic = 0)
+ Clock Path Skew: 0.004ns (0.079 - 0.075)
+ Source Clock: clk_125m_pllref_BUFG rising at 8.000ns
+ Destination Clock: clk_125m_pllref_BUFG rising at 8.000ns
+ Clock Uncertainty: 0.000ns
+
+ Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/ppulse_o to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_r_6
+ Location Delay type Delay(ns) Physical Resource
+ Logical Resource(s)
+ ------------------------------------------------- -------------------
+ SLICE_X63Y126.DQ Tcko 0.198 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/ppulse_o
+ U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/ppulse_o
+ SLICE_X60Y127.CE net (fanout=10) 0.239 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/ppulse_o
+ SLICE_X60Y127.CLK Tckce (-Th) 0.104 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_r<7>
+ U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_r_6
+ ------------------------------------------------- ---------------------------
+ Total 0.333ns (0.094ns logic, 0.239ns route)
+ (28.2% logic, 71.8% route)
+
+--------------------------------------------------------------------------------
+
+Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_r_5 (SLICE_X60Y127.CE), 1 path
+--------------------------------------------------------------------------------
+Slack (hold path): 0.331ns (requirement - (clock path skew + uncertainty - data path))
+ Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/ppulse_o (FF)
+ Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_r_5 (FF)
+ Requirement: 0.000ns
+ Data Path Delay: 0.335ns (Levels of Logic = 0)
+ Clock Path Skew: 0.004ns (0.079 - 0.075)
+ Source Clock: clk_125m_pllref_BUFG rising at 8.000ns
+ Destination Clock: clk_125m_pllref_BUFG rising at 8.000ns
+ Clock Uncertainty: 0.000ns
+
+ Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/ppulse_o to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_r_5
+ Location Delay type Delay(ns) Physical Resource
+ Logical Resource(s)
+ ------------------------------------------------- -------------------
+ SLICE_X63Y126.DQ Tcko 0.198 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/ppulse_o
+ U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/ppulse_o
+ SLICE_X60Y127.CE net (fanout=10) 0.239 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/ppulse_o
+ SLICE_X60Y127.CLK Tckce (-Th) 0.102 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_r<7>
+ U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_rx_r_5
+ ------------------------------------------------- ---------------------------
+ Total 0.335ns (0.096ns logic, 0.239ns route)
+ (28.7% logic, 71.3% route)
+
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_clk_125m_pllref_p_i = PERIOD TIMEGRP "clk_125m_pllref_p_i" 8 ns HIGH 50%;
@@ -433,7 +659,7 @@ Slack: 1.750ns (period - min period limit)
Min period limit: 6.250ns (160.000MHz) (Tgtpcper_TXUSRCLK)
Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK20
Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK20
- Location pin: GTPA1_DUAL_X0Y0.TXUSRCLK20
+ Location pin: GTPA1_DUAL_X1Y1.TXUSRCLK20
Clock network: clk_125m_pllref_BUFG
--------------------------------------------------------------------------------
Slack: 1.750ns (period - min period limit)
@@ -441,7 +667,7 @@ Slack: 1.750ns (period - min period limit)
Min period limit: 6.250ns (160.000MHz) (Tgtpcper_TXUSRCLK)
Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK21
Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK21
- Location pin: GTPA1_DUAL_X0Y0.TXUSRCLK21
+ Location pin: GTPA1_DUAL_X1Y1.TXUSRCLK21
Clock network: clk_125m_pllref_BUFG
--------------------------------------------------------------------------------
Slack: 4.875ns (period - min period limit)
@@ -449,7 +675,7 @@ Slack: 4.875ns (period - min period limit)
Min period limit: 3.125ns (320.000MHz) (Tgtpcper_TXUSRCLK)
Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK0
Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK0
- Location pin: GTPA1_DUAL_X0Y0.TXUSRCLK0
+ Location pin: GTPA1_DUAL_X1Y1.TXUSRCLK0
Clock network: clk_125m_pllref_BUFG
--------------------------------------------------------------------------------
@@ -470,7 +696,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
Logical resource: cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X4Y84.CLKA
+ Location pin: RAMB16_X3Y78.CLKA
Clock network: tdc1_clk_125m
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
@@ -478,7 +704,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKB)
Physical resource: cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
Logical resource: cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
- Location pin: RAMB16_X4Y84.CLKB
+ Location pin: RAMB16_X3Y78.CLKB
Clock network: tdc1_clk_125m
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
@@ -486,7 +712,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
Logical resource: cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X4Y80.CLKA
+ Location pin: RAMB16_X4Y76.CLKA
Clock network: tdc1_clk_125m
--------------------------------------------------------------------------------
@@ -495,19 +721,19 @@ Timing constraint: TS_tdc1_125m_clk_p_i = PERIOD TIMEGRP "tdc1_125m_clk_p_i" 8
ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
- 474722 paths analyzed, 9733 endpoints analyzed, 0 failing endpoints
+ 454503 paths analyzed, 9943 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is 7.731ns.
+ Minimum period is 7.729ns.
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAMB16_X4Y84.DIA8), 2650 paths
+Paths for end point cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_9 (SLICE_X95Y162.C6), 541 paths
--------------------------------------------------------------------------------
-Slack (setup path): 0.269ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1/cmp_tdc_core/data_formatting_block/acam_start_nb_2 (FF)
- Destination: cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+Slack (setup path): 0.271ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_3 (FF)
+ Destination: cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_9 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.671ns (Levels of Logic = 8)
- Clock Path Skew: -0.025ns (0.233 - 0.258)
+ Data Path Delay: 7.679ns (Levels of Logic = 7)
+ Clock Path Skew: -0.015ns (0.244 - 0.259)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -518,53 +744,45 @@ Slack (setup path): 0.269ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/data_formatting_block/acam_start_nb_2 to cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_3 to cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X71Y162.DQ Tcko 0.391 cmp_tdc1/cmp_tdc_core/data_formatting_block/acam_start_nb<2>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/acam_start_nb_2
- SLICE_X70Y162.C4 net (fanout=6) 1.833 cmp_tdc1/cmp_tdc_core/data_formatting_block/acam_start_nb<2>
- SLICE_X70Y162.CMUX Tilo 0.251 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<9>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd2
- SLICE_X70Y162.D3 net (fanout=2) 0.311 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd2
- SLICE_X70Y162.DQ Tad_logic 0.778 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<9>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_lut<0>3
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_2
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<9>_rt
- SLICE_X68Y161.D5 net (fanout=2) 0.717 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<9>
- SLICE_X68Y161.COUT Topcyd 0.261 cmp_tdc1/cmp_tdc_core/data_formatting_block/un_previous_retrig_nb_offset<3>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<9>_rt
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<9>
- SLICE_X68Y162.CIN net (fanout=1) 0.003 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<9>
- SLICE_X68Y162.COUT Tbyp 0.076 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- SLICE_X68Y163.CIN net (fanout=1) 0.003 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- SLICE_X68Y163.COUT Tbyp 0.076 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- SLICE_X68Y164.CIN net (fanout=1) 0.003 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- SLICE_X68Y164.COUT Tbyp 0.076 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X68Y165.CIN net (fanout=1) 0.003 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X68Y165.COUT Tbyp 0.076 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- SLICE_X68Y166.CIN net (fanout=1) 0.003 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- SLICE_X68Y166.BMUX Tcinb 0.292 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
- RAMB16_X4Y84.DIA8 net (fanout=1) 2.218 cmp_tdc1/cmp_tdc_core/circ_buff_class_data_wr<59>
- RAMB16_X4Y84.CLKA Trdck_DIA 0.300 cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X101Y161.DQ Tcko 0.391 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<3>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_3
+ SLICE_X103Y161.A6 net (fanout=47) 1.576 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<3>
+ SLICE_X103Y161.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_3<23>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out10921
+ SLICE_X100Y163.B3 net (fanout=32) 2.298 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out1092
+ SLICE_X100Y163.B Tilo 0.203 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_1<11>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38413
+ SLICE_X100Y163.A5 net (fanout=1) 0.222 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38412
+ SLICE_X100Y163.A Tilo 0.203 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_1<11>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38414
+ SLICE_X94Y163.C6 net (fanout=1) 0.765 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38413
+ SLICE_X94Y163.C Tilo 0.204 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_1<16>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38415
+ SLICE_X94Y163.B4 net (fanout=1) 0.269 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38414
+ SLICE_X94Y163.B Tilo 0.203 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_1<16>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38416
+ SLICE_X95Y162.D6 net (fanout=1) 0.387 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38415
+ SLICE_X95Y162.D Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<9>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38418_SW0
+ SLICE_X95Y162.C6 net (fanout=1) 0.118 N2733
+ SLICE_X95Y162.CLK Tas 0.322 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<9>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38418
+ cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_9
------------------------------------------------- ---------------------------
- Total 7.671ns (2.577ns logic, 5.094ns route)
- (33.6% logic, 66.4% route)
+ Total 7.679ns (2.044ns logic, 5.635ns route)
+ (26.6% logic, 73.4% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.317ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1/cmp_tdc_core/data_formatting_block/acam_start_nb_2 (FF)
- Destination: cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+Slack (setup path): 0.460ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0 (FF)
+ Destination: cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_9 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.623ns (Levels of Logic = 8)
- Clock Path Skew: -0.025ns (0.233 - 0.258)
+ Data Path Delay: 7.490ns (Levels of Logic = 8)
+ Clock Path Skew: -0.015ns (0.244 - 0.259)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -575,52 +793,48 @@ Slack (setup path): 0.317ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/data_formatting_block/acam_start_nb_2 to cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0 to cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X71Y162.DQ Tcko 0.391 cmp_tdc1/cmp_tdc_core/data_formatting_block/acam_start_nb<2>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/acam_start_nb_2
- SLICE_X70Y162.C4 net (fanout=6) 1.833 cmp_tdc1/cmp_tdc_core/data_formatting_block/acam_start_nb<2>
- SLICE_X70Y162.CMUX Tilo 0.251 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<9>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd2
- SLICE_X70Y162.DX net (fanout=2) 0.551 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd2
- SLICE_X70Y162.COUT Tdxcy 0.097 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<9>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_2
- SLICE_X70Y163.CIN net (fanout=1) 0.003 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>3
- SLICE_X70Y163.COUT Tbyp 0.076 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<13>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_6
- SLICE_X70Y164.CIN net (fanout=1) 0.003 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>7
- SLICE_X70Y164.BQ Tito_logic 0.664 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<17>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_10
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<15>_rt
- SLICE_X68Y163.B5 net (fanout=2) 0.403 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<15>
- SLICE_X68Y163.COUT Topcyb 0.380 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<15>_rt.1
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- SLICE_X68Y164.CIN net (fanout=1) 0.003 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- SLICE_X68Y164.COUT Tbyp 0.076 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X68Y165.CIN net (fanout=1) 0.003 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X68Y165.COUT Tbyp 0.076 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- SLICE_X68Y166.CIN net (fanout=1) 0.003 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- SLICE_X68Y166.BMUX Tcinb 0.292 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
- RAMB16_X4Y84.DIA8 net (fanout=1) 2.218 cmp_tdc1/cmp_tdc_core/circ_buff_class_data_wr<59>
- RAMB16_X4Y84.CLKA Trdck_DIA 0.300 cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X100Y161.AQ Tcko 0.447 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<1>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0
+ SLICE_X101Y161.A6 net (fanout=34) 0.664 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<0>
+ SLICE_X101Y161.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<3>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/_n0576<7>11
+ SLICE_X103Y161.A5 net (fanout=15) 0.408 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0576<7>1
+ SLICE_X103Y161.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_3<23>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out10921
+ SLICE_X100Y163.B3 net (fanout=32) 2.298 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out1092
+ SLICE_X100Y163.B Tilo 0.203 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_1<11>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38413
+ SLICE_X100Y163.A5 net (fanout=1) 0.222 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38412
+ SLICE_X100Y163.A Tilo 0.203 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_1<11>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38414
+ SLICE_X94Y163.C6 net (fanout=1) 0.765 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38413
+ SLICE_X94Y163.C Tilo 0.204 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_1<16>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38415
+ SLICE_X94Y163.B4 net (fanout=1) 0.269 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38414
+ SLICE_X94Y163.B Tilo 0.203 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_1<16>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38416
+ SLICE_X95Y162.D6 net (fanout=1) 0.387 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38415
+ SLICE_X95Y162.D Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<9>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38418_SW0
+ SLICE_X95Y162.C6 net (fanout=1) 0.118 N2733
+ SLICE_X95Y162.CLK Tas 0.322 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<9>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38418
+ cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_9
------------------------------------------------- ---------------------------
- Total 7.623ns (2.603ns logic, 5.020ns route)
- (34.1% logic, 65.9% route)
+ Total 7.490ns (2.359ns logic, 5.131ns route)
+ (31.5% logic, 68.5% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.317ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1/cmp_tdc_core/data_formatting_block/acam_start_nb_2 (FF)
- Destination: cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
+Slack (setup path): 0.655ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5 (FF)
+ Destination: cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_9 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.623ns (Levels of Logic = 8)
- Clock Path Skew: -0.025ns (0.233 - 0.258)
+ Data Path Delay: 7.295ns (Levels of Logic = 8)
+ Clock Path Skew: -0.015ns (0.244 - 0.259)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -631,55 +845,51 @@ Slack (setup path): 0.317ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/data_formatting_block/acam_start_nb_2 to cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5 to cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X71Y162.DQ Tcko 0.391 cmp_tdc1/cmp_tdc_core/data_formatting_block/acam_start_nb<2>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/acam_start_nb_2
- SLICE_X70Y162.C4 net (fanout=6) 1.833 cmp_tdc1/cmp_tdc_core/data_formatting_block/acam_start_nb<2>
- SLICE_X70Y162.CMUX Tilo 0.251 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<9>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd2
- SLICE_X70Y162.DX net (fanout=2) 0.551 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd2
- SLICE_X70Y162.COUT Tdxcy 0.097 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<9>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_2
- SLICE_X70Y163.CIN net (fanout=1) 0.003 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>3
- SLICE_X70Y163.BQ Tito_logic 0.664 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<13>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd_cy<0>_6
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<11>_rt
- SLICE_X68Y162.B5 net (fanout=2) 0.403 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<11>
- SLICE_X68Y162.COUT Topcyb 0.380 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_lut<11>_rt.1
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- SLICE_X68Y163.CIN net (fanout=1) 0.003 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<13>
- SLICE_X68Y163.COUT Tbyp 0.076 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- SLICE_X68Y164.CIN net (fanout=1) 0.003 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<17>
- SLICE_X68Y164.COUT Tbyp 0.076 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X68Y165.CIN net (fanout=1) 0.003 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<21>
- SLICE_X68Y165.COUT Tbyp 0.076 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- SLICE_X68Y166.CIN net (fanout=1) 0.003 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<25>
- SLICE_X68Y166.BMUX Tcinb 0.292 cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
- cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_cycles_cy<29>
- RAMB16_X4Y84.DIA8 net (fanout=1) 2.218 cmp_tdc1/cmp_tdc_core/circ_buff_class_data_wr<59>
- RAMB16_X4Y84.CLKA Trdck_DIA 0.300 cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
- cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ SLICE_X100Y161.CQ Tcko 0.447 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<1>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5
+ SLICE_X101Y161.A2 net (fanout=9) 0.469 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<5>
+ SLICE_X101Y161.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<3>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/_n0576<7>11
+ SLICE_X103Y161.A5 net (fanout=15) 0.408 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0576<7>1
+ SLICE_X103Y161.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_3<23>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out10921
+ SLICE_X100Y163.B3 net (fanout=32) 2.298 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out1092
+ SLICE_X100Y163.B Tilo 0.203 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_1<11>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38413
+ SLICE_X100Y163.A5 net (fanout=1) 0.222 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38412
+ SLICE_X100Y163.A Tilo 0.203 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_1<11>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38414
+ SLICE_X94Y163.C6 net (fanout=1) 0.765 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38413
+ SLICE_X94Y163.C Tilo 0.204 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_1<16>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38415
+ SLICE_X94Y163.B4 net (fanout=1) 0.269 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38414
+ SLICE_X94Y163.B Tilo 0.203 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_1<16>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38416
+ SLICE_X95Y162.D6 net (fanout=1) 0.387 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38415
+ SLICE_X95Y162.D Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<9>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38418_SW0
+ SLICE_X95Y162.C6 net (fanout=1) 0.118 N2733
+ SLICE_X95Y162.CLK Tas 0.322 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<9>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out38418
+ cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_9
------------------------------------------------- ---------------------------
- Total 7.623ns (2.603ns logic, 5.020ns route)
- (34.1% logic, 65.9% route)
+ Total 7.295ns (2.359ns logic, 4.936ns route)
+ (32.3% logic, 67.7% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_28 (SLICE_X103Y167.A5), 343 paths
+Paths for end point cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_13 (SLICE_X107Y158.C6), 541 paths
--------------------------------------------------------------------------------
-Slack (setup path): 0.313ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1 (FF)
- Destination: cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_28 (FF)
+Slack (setup path): 0.297ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0 (FF)
+ Destination: cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_13 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.627ns (Levels of Logic = 7)
- Clock Path Skew: -0.025ns (0.231 - 0.256)
+ Data Path Delay: 7.563ns (Levels of Logic = 6)
+ Clock Path Skew: -0.105ns (0.621 - 0.726)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -690,45 +900,42 @@ Slack (setup path): 0.313ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1 to cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_28
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0 to cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_13
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X105Y171.AQ Tcko 0.391 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- SLICE_X104Y172.A3 net (fanout=3) 1.121 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- SLICE_X104Y172.A Tilo 0.203 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5_1
- cmp_tdc1/cmp_tdc_core/reg_control_block/_n0585<7>11
- SLICE_X111Y174.A3 net (fanout=38) 0.768 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0585<7>1
- SLICE_X111Y174.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_0<3>
- cmp_tdc1/cmp_tdc_core/reg_control_block/_n0634<7>1
- SLICE_X112Y170.A6 net (fanout=32) 1.227 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0634
- SLICE_X112Y170.A Tilo 0.203 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_0<11>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2525
- SLICE_X105Y171.B6 net (fanout=1) 0.652 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2524
- SLICE_X105Y171.B Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2529
- SLICE_X105Y171.A6 net (fanout=1) 0.340 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2528
- SLICE_X105Y171.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out25211
- SLICE_X103Y167.B1 net (fanout=1) 1.177 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out25210
- SLICE_X103Y167.B Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<28>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out25212
- SLICE_X103Y167.A5 net (fanout=1) 0.187 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out25211
- SLICE_X103Y167.CLK Tas 0.322 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<28>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out25213
- cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_28
+ SLICE_X100Y161.AQ Tcko 0.447 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<1>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0
+ SLICE_X101Y161.A6 net (fanout=34) 0.664 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<0>
+ SLICE_X101Y161.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<3>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/_n0576<7>11
+ SLICE_X96Y167.B5 net (fanout=15) 1.473 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0576<7>1
+ SLICE_X96Y167.BMUX Tilo 0.251 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_9<27>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/_n0728<7>1
+ SLICE_X103Y170.A4 net (fanout=31) 1.032 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0728
+ SLICE_X103Y170.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_8<15>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out606
+ SLICE_X107Y163.C5 net (fanout=1) 1.708 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out605
+ SLICE_X107Y163.C Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_0<15>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out6016
+ SLICE_X107Y158.D6 net (fanout=1) 0.512 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out6015
+ SLICE_X107Y158.D Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<13>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out6018_SW0
+ SLICE_X107Y158.C6 net (fanout=1) 0.118 N2731
+ SLICE_X107Y158.CLK Tas 0.322 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<13>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out6018
+ cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_13
------------------------------------------------- ---------------------------
- Total 7.627ns (2.155ns logic, 5.472ns route)
- (28.3% logic, 71.7% route)
+ Total 7.563ns (2.056ns logic, 5.507ns route)
+ (27.2% logic, 72.8% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.602ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1 (FF)
- Destination: cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_28 (FF)
+Slack (setup path): 0.434ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0 (FF)
+ Destination: cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_13 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.338ns (Levels of Logic = 7)
- Clock Path Skew: -0.025ns (0.231 - 0.256)
+ Data Path Delay: 7.426ns (Levels of Logic = 7)
+ Clock Path Skew: -0.105ns (0.621 - 0.726)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -739,45 +946,45 @@ Slack (setup path): 0.602ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1 to cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_28
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0 to cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_13
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X105Y171.AQ Tcko 0.391 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- SLICE_X105Y173.A4 net (fanout=3) 1.152 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- SLICE_X105Y173.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out3604
+ SLICE_X100Y161.AQ Tcko 0.447 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<1>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0
+ SLICE_X101Y161.A6 net (fanout=34) 0.664 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<0>
+ SLICE_X101Y161.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<3>
cmp_tdc1/cmp_tdc_core/reg_control_block/_n0576<7>11
- SLICE_X113Y172.A5 net (fanout=10) 0.917 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0576<7>1
- SLICE_X113Y172.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_7<31>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out11111
- SLICE_X112Y170.A2 net (fanout=30) 0.702 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out1111
- SLICE_X112Y170.A Tilo 0.203 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_0<11>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2525
- SLICE_X105Y171.B6 net (fanout=1) 0.652 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2524
- SLICE_X105Y171.B Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2529
- SLICE_X105Y171.A6 net (fanout=1) 0.340 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2528
- SLICE_X105Y171.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out25211
- SLICE_X103Y167.B1 net (fanout=1) 1.177 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out25210
- SLICE_X103Y167.B Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<28>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out25212
- SLICE_X103Y167.A5 net (fanout=1) 0.187 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out25211
- SLICE_X103Y167.CLK Tas 0.322 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<28>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out25213
- cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_28
+ SLICE_X98Y168.C6 net (fanout=15) 1.909 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0576<7>1
+ SLICE_X98Y168.C Tilo 0.205 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_4<27>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out10211
+ SLICE_X102Y166.A4 net (fanout=30) 1.054 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out1021
+ SLICE_X102Y166.A Tilo 0.205 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_4<15>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out607
+ SLICE_X107Y163.D3 net (fanout=1) 0.836 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out606
+ SLICE_X107Y163.D Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_0<15>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out6015
+ SLICE_X107Y163.C6 net (fanout=1) 0.118 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out6014
+ SLICE_X107Y163.C Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_0<15>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out6016
+ SLICE_X107Y158.D6 net (fanout=1) 0.512 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out6015
+ SLICE_X107Y158.D Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<13>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out6018_SW0
+ SLICE_X107Y158.C6 net (fanout=1) 0.118 N2731
+ SLICE_X107Y158.CLK Tas 0.322 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<13>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out6018
+ cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_13
------------------------------------------------- ---------------------------
- Total 7.338ns (2.211ns logic, 5.127ns route)
- (30.1% logic, 69.9% route)
+ Total 7.426ns (2.215ns logic, 5.211ns route)
+ (29.8% logic, 70.2% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.689ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0_1 (FF)
- Destination: cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_28 (FF)
+Slack (setup path): 0.492ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5 (FF)
+ Destination: cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_13 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.249ns (Levels of Logic = 7)
- Clock Path Skew: -0.027ns (0.231 - 0.258)
+ Data Path Delay: 7.368ns (Levels of Logic = 6)
+ Clock Path Skew: -0.105ns (0.621 - 0.726)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -788,48 +995,45 @@ Slack (setup path): 0.689ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0_1 to cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_28
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5 to cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_13
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X105Y172.AQ Tcko 0.391 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0_1
- cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0_1
- SLICE_X104Y172.A6 net (fanout=1) 0.743 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0_1
- SLICE_X104Y172.A Tilo 0.203 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5_1
- cmp_tdc1/cmp_tdc_core/reg_control_block/_n0585<7>11
- SLICE_X111Y174.A3 net (fanout=38) 0.768 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0585<7>1
- SLICE_X111Y174.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_0<3>
- cmp_tdc1/cmp_tdc_core/reg_control_block/_n0634<7>1
- SLICE_X112Y170.A6 net (fanout=32) 1.227 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0634
- SLICE_X112Y170.A Tilo 0.203 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_0<11>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2525
- SLICE_X105Y171.B6 net (fanout=1) 0.652 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2524
- SLICE_X105Y171.B Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2529
- SLICE_X105Y171.A6 net (fanout=1) 0.340 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2528
- SLICE_X105Y171.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out25211
- SLICE_X103Y167.B1 net (fanout=1) 1.177 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out25210
- SLICE_X103Y167.B Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<28>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out25212
- SLICE_X103Y167.A5 net (fanout=1) 0.187 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out25211
- SLICE_X103Y167.CLK Tas 0.322 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<28>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out25213
- cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_28
+ SLICE_X100Y161.CQ Tcko 0.447 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<1>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5
+ SLICE_X101Y161.A2 net (fanout=9) 0.469 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<5>
+ SLICE_X101Y161.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<3>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/_n0576<7>11
+ SLICE_X96Y167.B5 net (fanout=15) 1.473 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0576<7>1
+ SLICE_X96Y167.BMUX Tilo 0.251 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_9<27>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/_n0728<7>1
+ SLICE_X103Y170.A4 net (fanout=31) 1.032 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0728
+ SLICE_X103Y170.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_8<15>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out606
+ SLICE_X107Y163.C5 net (fanout=1) 1.708 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out605
+ SLICE_X107Y163.C Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_0<15>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out6016
+ SLICE_X107Y158.D6 net (fanout=1) 0.512 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out6015
+ SLICE_X107Y158.D Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<13>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out6018_SW0
+ SLICE_X107Y158.C6 net (fanout=1) 0.118 N2731
+ SLICE_X107Y158.CLK Tas 0.322 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<13>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out6018
+ cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_13
------------------------------------------------- ---------------------------
- Total 7.249ns (2.155ns logic, 5.094ns route)
- (29.7% logic, 70.3% route)
+ Total 7.368ns (2.056ns logic, 5.312ns route)
+ (27.9% logic, 72.1% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24 (SLICE_X104Y168.B6), 551 paths
+Paths for end point cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_16 (SLICE_X93Y164.A5), 541 paths
--------------------------------------------------------------------------------
-Slack (setup path): 0.313ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1 (FF)
- Destination: cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24 (FF)
+Slack (setup path): 0.298ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_7 (FF)
+ Destination: cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_16 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.635ns (Levels of Logic = 6)
- Clock Path Skew: -0.017ns (0.143 - 0.160)
+ Data Path Delay: 7.649ns (Levels of Logic = 8)
+ Clock Path Skew: -0.018ns (0.240 - 0.258)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -840,42 +1044,48 @@ Slack (setup path): 0.313ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1 to cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_7 to cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_16
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X105Y171.AQ Tcko 0.391 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- SLICE_X104Y172.A3 net (fanout=3) 1.121 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- SLICE_X104Y172.A Tilo 0.203 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5_1
+ SLICE_X98Y161.BQ Tcko 0.408 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<7>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_7
+ SLICE_X103Y161.C5 net (fanout=9) 0.789 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<7>
+ SLICE_X103Y161.C Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_3<23>
cmp_tdc1/cmp_tdc_core/reg_control_block/_n0585<7>11
- SLICE_X107Y177.B5 net (fanout=38) 0.824 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0585<7>1
- SLICE_X107Y177.BMUX Tilo 0.313 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_6<3>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out10311
- SLICE_X107Y179.C4 net (fanout=30) 0.725 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out1031
- SLICE_X107Y179.C Tilo 0.259 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_9<23>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2045
- SLICE_X107Y175.D2 net (fanout=2) 1.478 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2044
- SLICE_X107Y175.D Tilo 0.259 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_8<3>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out20414_SW0
- SLICE_X104Y168.A2 net (fanout=1) 1.452 N1899
- SLICE_X104Y168.A Tilo 0.203 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out20415
- SLICE_X104Y168.B6 net (fanout=1) 0.118 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out20414
- SLICE_X104Y168.CLK Tas 0.289 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out20417
- cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24
+ SLICE_X104Y157.A4 net (fanout=16) 0.826 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0585<7>1
+ SLICE_X104Y157.A Tilo 0.203 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_3<15>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out11011
+ SLICE_X103Y157.B6 net (fanout=32) 0.591 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out1101
+ SLICE_X103Y157.B Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0505_inv
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9611
+ SLICE_X102Y162.A5 net (fanout=1) 1.301 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9610
+ SLICE_X102Y162.A Tilo 0.205 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_10<19>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9614
+ SLICE_X95Y163.B6 net (fanout=1) 0.871 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9613
+ SLICE_X95Y163.B Tilo 0.259 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_2<18>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9615
+ SLICE_X95Y163.A5 net (fanout=1) 0.187 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9614
+ SLICE_X95Y163.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_2<18>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9616
+ SLICE_X93Y164.B6 net (fanout=1) 0.464 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9615
+ SLICE_X93Y164.B Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<17>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9618_SW0
+ SLICE_X93Y164.A5 net (fanout=1) 0.187 N2725
+ SLICE_X93Y164.CLK Tas 0.322 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<17>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9618
+ cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_16
------------------------------------------------- ---------------------------
- Total 7.635ns (1.917ns logic, 5.718ns route)
- (25.1% logic, 74.9% route)
+ Total 7.649ns (2.433ns logic, 5.216ns route)
+ (31.8% logic, 68.2% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.322ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1 (FF)
- Destination: cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24 (FF)
+Slack (setup path): 0.349ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0 (FF)
+ Destination: cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_16 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.626ns (Levels of Logic = 6)
- Clock Path Skew: -0.017ns (0.143 - 0.160)
+ Data Path Delay: 7.597ns (Levels of Logic = 8)
+ Clock Path Skew: -0.019ns (0.240 - 0.259)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -886,42 +1096,48 @@ Slack (setup path): 0.322ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1 to cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0 to cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_16
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X105Y171.AQ Tcko 0.391 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- SLICE_X105Y173.A4 net (fanout=3) 1.152 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- SLICE_X105Y173.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out3604
+ SLICE_X100Y161.AQ Tcko 0.447 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<1>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0
+ SLICE_X101Y161.A6 net (fanout=34) 0.664 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<0>
+ SLICE_X101Y161.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<3>
cmp_tdc1/cmp_tdc_core/reg_control_block/_n0576<7>11
- SLICE_X106Y177.B6 net (fanout=10) 0.713 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0576<7>1
- SLICE_X106Y177.B Tilo 0.205 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_5<15>
- cmp_tdc1/cmp_tdc_core/reg_control_block/_n0728<7>1
- SLICE_X107Y179.C6 net (fanout=31) 0.848 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0728
- SLICE_X107Y179.C Tilo 0.259 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_9<23>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2045
- SLICE_X107Y175.D2 net (fanout=2) 1.478 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2044
- SLICE_X107Y175.D Tilo 0.259 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_8<3>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out20414_SW0
- SLICE_X104Y168.A2 net (fanout=1) 1.452 N1899
- SLICE_X104Y168.A Tilo 0.203 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out20415
- SLICE_X104Y168.B6 net (fanout=1) 0.118 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out20414
- SLICE_X104Y168.CLK Tas 0.289 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out20417
- cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24
+ SLICE_X103Y158.D6 net (fanout=15) 0.723 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0576<7>1
+ SLICE_X103Y158.D Tilo 0.259 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_10<26>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/_n0611<7>1
+ SLICE_X103Y157.B2 net (fanout=32) 0.672 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0611
+ SLICE_X103Y157.B Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0505_inv
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9611
+ SLICE_X102Y162.A5 net (fanout=1) 1.301 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9610
+ SLICE_X102Y162.A Tilo 0.205 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_10<19>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9614
+ SLICE_X95Y163.B6 net (fanout=1) 0.871 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9613
+ SLICE_X95Y163.B Tilo 0.259 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_2<18>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9615
+ SLICE_X95Y163.A5 net (fanout=1) 0.187 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9614
+ SLICE_X95Y163.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_2<18>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9616
+ SLICE_X93Y164.B6 net (fanout=1) 0.464 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9615
+ SLICE_X93Y164.B Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<17>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9618_SW0
+ SLICE_X93Y164.A5 net (fanout=1) 0.187 N2725
+ SLICE_X93Y164.CLK Tas 0.322 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<17>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9618
+ cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_16
------------------------------------------------- ---------------------------
- Total 7.626ns (1.865ns logic, 5.761ns route)
- (24.5% logic, 75.5% route)
+ Total 7.597ns (2.528ns logic, 5.069ns route)
+ (33.3% logic, 66.7% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.355ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_4 (FF)
- Destination: cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24 (FF)
+Slack (setup path): 0.464ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_1 (FF)
+ Destination: cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_16 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.596ns (Levels of Logic = 5)
- Clock Path Skew: -0.014ns (0.234 - 0.248)
+ Data Path Delay: 7.482ns (Levels of Logic = 7)
+ Clock Path Skew: -0.019ns (0.240 - 0.259)
Source Clock: tdc1_clk_125m rising at 0.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -932,118 +1148,122 @@ Slack (setup path): 0.355ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_4 to cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24
+ Maximum Data Path at Slow Process Corner: cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_1 to cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_16
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X105Y167.BQ Tcko 0.391 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<4>
- cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_4
- SLICE_X106Y177.B4 net (fanout=61) 2.094 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<4>
- SLICE_X106Y177.B Tilo 0.205 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_5<15>
- cmp_tdc1/cmp_tdc_core/reg_control_block/_n0728<7>1
- SLICE_X107Y179.C6 net (fanout=31) 0.848 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0728
- SLICE_X107Y179.C Tilo 0.259 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_9<23>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2045
- SLICE_X107Y175.D2 net (fanout=2) 1.478 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out2044
- SLICE_X107Y175.D Tilo 0.259 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_8<3>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out20414_SW0
- SLICE_X104Y168.A2 net (fanout=1) 1.452 N1899
- SLICE_X104Y168.A Tilo 0.203 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out20415
- SLICE_X104Y168.B6 net (fanout=1) 0.118 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out20414
- SLICE_X104Y168.CLK Tas 0.289 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out20417
- cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24
+ SLICE_X100Y161.DQ Tcko 0.447 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<1>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0_1
+ SLICE_X104Y157.A3 net (fanout=53) 1.668 cmp_tdc1/cmp_tdc_core/reg_control_block/reg_adr_pipe0<1>
+ SLICE_X104Y157.A Tilo 0.203 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_3<15>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out11011
+ SLICE_X103Y157.B6 net (fanout=32) 0.591 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out1101
+ SLICE_X103Y157.B Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/_n0505_inv
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9611
+ SLICE_X102Y162.A5 net (fanout=1) 1.301 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9610
+ SLICE_X102Y162.A Tilo 0.205 cmp_tdc1/cmp_tdc_core/reg_control_block/acam_config_10<19>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9614
+ SLICE_X95Y163.B6 net (fanout=1) 0.871 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9613
+ SLICE_X95Y163.B Tilo 0.259 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_2<18>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9615
+ SLICE_X95Y163.A5 net (fanout=1) 0.187 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9614
+ SLICE_X95Y163.A Tilo 0.259 cmp_tdc1/cmp_tdc_core/data_engine_block/acam_config_rdbk_2<18>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9616
+ SLICE_X93Y164.B6 net (fanout=1) 0.464 cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9615
+ SLICE_X93Y164.B Tilo 0.259 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<17>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9618_SW0
+ SLICE_X93Y164.A5 net (fanout=1) 0.187 N2725
+ SLICE_X93Y164.CLK Tas 0.322 cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<17>
+ cmp_tdc1/cmp_tdc_core/reg_control_block/Mmux_dat_out9618
+ cmp_tdc1/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_16
------------------------------------------------- ---------------------------
- Total 7.596ns (1.606ns logic, 5.990ns route)
- (21.1% logic, 78.9% route)
+ Total 7.482ns (2.213ns logic, 5.269ns route)
+ (29.6% logic, 70.4% route)
--------------------------------------------------------------------------------
Hold Paths: TS_tdc1_125m_clk_p_i = PERIOD TIMEGRP "tdc1_125m_clk_p_i" 8 ns HIGH 50%;
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter_0 (SLICE_X83Y163.C5), 1 path
+Paths for end point cmp_tdc1/cmp_tdc_core/acam_data_block/acam_data_st_FSM_FFd3 (SLICE_X104Y179.CX), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.410ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc1/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter_1 (FF)
- Destination: cmp_tdc1/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter_0 (FF)
+Slack (hold path): 0.397ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc1/cmp_tdc_core/acam_data_block/acam_data_st_FSM_FFd4 (FF)
+ Destination: cmp_tdc1/cmp_tdc_core/acam_data_block/acam_data_st_FSM_FFd3 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.410ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
+ Data Path Delay: 0.399ns (Levels of Logic = 0)
+ Clock Path Skew: 0.002ns (0.041 - 0.039)
Source Clock: tdc1_clk_125m rising at 8.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc1/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter_1 to cmp_tdc1/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter_0
+ Minimum Data Path at Fast Process Corner: cmp_tdc1/cmp_tdc_core/acam_data_block/acam_data_st_FSM_FFd4 to cmp_tdc1/cmp_tdc_core/acam_data_block/acam_data_st_FSM_FFd3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X83Y163.CQ Tcko 0.198 cmp_tdc1/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter<1>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter_1
- SLICE_X83Y163.C5 net (fanout=2) 0.057 cmp_tdc1/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter<1>
- SLICE_X83Y163.CLK Tah (-Th) -0.155 cmp_tdc1/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter<1>
- cmp_tdc1/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter_0_glue_set
- cmp_tdc1/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter_0
+ SLICE_X105Y179.CQ Tcko 0.198 cmp_tdc1/cmp_tdc_core/acam_data_block/acam_data_st_FSM_FFd3-In
+ cmp_tdc1/cmp_tdc_core/acam_data_block/acam_data_st_FSM_FFd4
+ SLICE_X104Y179.CX net (fanout=2) 0.160 cmp_tdc1/cmp_tdc_core/acam_data_block/acam_data_st_FSM_FFd3-In
+ SLICE_X104Y179.CLK Tckdi (-Th) -0.041 cmp_tdc1/cmp_tdc_core/acam_data_block/acam_data_st_FSM_FFd3
+ cmp_tdc1/cmp_tdc_core/acam_data_block/acam_data_st_FSM_FFd3
------------------------------------------------- ---------------------------
- Total 0.410ns (0.353ns logic, 0.057ns route)
- (86.1% logic, 13.9% route)
+ Total 0.399ns (0.239ns logic, 0.160ns route)
+ (59.9% logic, 40.1% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1/cmp_tdc_core/TDCboard_leds/cmp_extend_ch3_pulse/extended_int (SLICE_X54Y184.A6), 1 path
+Paths for end point cmp_tdc1_clks_rsts_mgment/internal_rst_synch_1 (SLICE_X81Y156.DX), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.412ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc1/cmp_tdc_core/TDCboard_leds/cmp_extend_ch3_pulse/extended_int (FF)
- Destination: cmp_tdc1/cmp_tdc_core/TDCboard_leds/cmp_extend_ch3_pulse/extended_int (FF)
+Slack (hold path): 0.402ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc1_clks_rsts_mgment/internal_rst_synch_0 (FF)
+ Destination: cmp_tdc1_clks_rsts_mgment/internal_rst_synch_1 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.412ns (Levels of Logic = 1)
+ Data Path Delay: 0.402ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: tdc1_clk_125m rising at 8.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc1/cmp_tdc_core/TDCboard_leds/cmp_extend_ch3_pulse/extended_int to cmp_tdc1/cmp_tdc_core/TDCboard_leds/cmp_extend_ch3_pulse/extended_int
+ Minimum Data Path at Fast Process Corner: cmp_tdc1_clks_rsts_mgment/internal_rst_synch_0 to cmp_tdc1_clks_rsts_mgment/internal_rst_synch_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X54Y184.AQ Tcko 0.200 cmp_tdc1/cmp_tdc_core/TDCboard_leds/cmp_extend_ch3_pulse/extended_int
- cmp_tdc1/cmp_tdc_core/TDCboard_leds/cmp_extend_ch3_pulse/extended_int
- SLICE_X54Y184.A6 net (fanout=2) 0.022 cmp_tdc1/cmp_tdc_core/TDCboard_leds/cmp_extend_ch3_pulse/extended_int
- SLICE_X54Y184.CLK Tah (-Th) -0.190 cmp_tdc1/cmp_tdc_core/TDCboard_leds/cmp_extend_ch3_pulse/extended_int
- cmp_tdc1/cmp_tdc_core/TDCboard_leds/cmp_extend_ch3_pulse/extended_int_rstpot
- cmp_tdc1/cmp_tdc_core/TDCboard_leds/cmp_extend_ch3_pulse/extended_int
+ SLICE_X81Y156.CQ Tcko 0.198 cmp_tdc1_clks_rsts_mgment/internal_rst_synch<1>
+ cmp_tdc1_clks_rsts_mgment/internal_rst_synch_0
+ SLICE_X81Y156.DX net (fanout=4) 0.145 cmp_tdc1_clks_rsts_mgment/internal_rst_synch<0>
+ SLICE_X81Y156.CLK Tckdi (-Th) -0.059 cmp_tdc1_clks_rsts_mgment/internal_rst_synch<1>
+ cmp_tdc1_clks_rsts_mgment/internal_rst_synch_1
------------------------------------------------- ---------------------------
- Total 0.412ns (0.390ns logic, 0.022ns route)
- (94.7% logic, 5.3% route)
+ Total 0.402ns (0.257ns logic, 0.145ns route)
+ (63.9% logic, 36.1% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc1/cmp_tdc_eic/eic_irq_controller_inst/irq_pending_0 (SLICE_X98Y149.A6), 1 path
+Paths for end point cmp_tdc1/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_16 (SLICE_X114Y142.B6), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.412ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc1/cmp_tdc_eic/eic_irq_controller_inst/irq_pending_0 (FF)
- Destination: cmp_tdc1/cmp_tdc_eic/eic_irq_controller_inst/irq_pending_0 (FF)
+Slack (hold path): 0.403ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc1/cmp_tdc_core/data_formatting_block/un_previous_roll_over_nb_8 (FF)
+ Destination: cmp_tdc1/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_16 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.412ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
+ Data Path Delay: 0.405ns (Levels of Logic = 1)
+ Clock Path Skew: 0.002ns (0.043 - 0.041)
Source Clock: tdc1_clk_125m rising at 8.000ns
Destination Clock: tdc1_clk_125m rising at 8.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc1/cmp_tdc_eic/eic_irq_controller_inst/irq_pending_0 to cmp_tdc1/cmp_tdc_eic/eic_irq_controller_inst/irq_pending_0
+ Minimum Data Path at Fast Process Corner: cmp_tdc1/cmp_tdc_core/data_formatting_block/un_previous_roll_over_nb_8 to cmp_tdc1/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_16
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X98Y149.AQ Tcko 0.200 cmp_tdc1/cmp_tdc_eic/eic_irq_controller_inst/irq_pending<1>
- cmp_tdc1/cmp_tdc_eic/eic_irq_controller_inst/irq_pending_0
- SLICE_X98Y149.A6 net (fanout=3) 0.022 cmp_tdc1/cmp_tdc_eic/eic_irq_controller_inst/irq_pending<0>
- SLICE_X98Y149.CLK Tah (-Th) -0.190 cmp_tdc1/cmp_tdc_eic/eic_irq_controller_inst/irq_pending<1>
- cmp_tdc1/cmp_tdc_eic/eic_irq_controller_inst/Mmux_GND_820_o_GND_820_o_MUX_12483_o11
- cmp_tdc1/cmp_tdc_eic/eic_irq_controller_inst/irq_pending_0
+ SLICE_X115Y142.AQ Tcko 0.198 cmp_tdc1/cmp_tdc_core/data_formatting_block/un_previous_roll_over_nb<11>
+ cmp_tdc1/cmp_tdc_core/data_formatting_block/un_previous_roll_over_nb_8
+ SLICE_X114Y142.B6 net (fanout=1) 0.017 cmp_tdc1/cmp_tdc_core/data_formatting_block/un_previous_roll_over_nb<8>
+ SLICE_X114Y142.CLK Tah (-Th) -0.190 cmp_tdc1/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over<18>
+ cmp_tdc1/cmp_tdc_core/data_formatting_block/Mmux_roll_over_nb_i[23]_un_previous_roll_over_nb[23]_mux_74_OUT71
+ cmp_tdc1/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_16
------------------------------------------------- ---------------------------
- Total 0.412ns (0.390ns logic, 0.022ns route)
- (94.7% logic, 5.3% route)
+ Total 0.405ns (0.388ns logic, 0.017ns route)
+ (95.8% logic, 4.2% route)
--------------------------------------------------------------------------------
@@ -1054,7 +1274,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
Logical resource: cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X4Y84.CLKA
+ Location pin: RAMB16_X3Y78.CLKA
Clock network: tdc1_clk_125m
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
@@ -1062,7 +1282,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKB)
Physical resource: cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
Logical resource: cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
- Location pin: RAMB16_X4Y84.CLKB
+ Location pin: RAMB16_X3Y78.CLKB
Clock network: tdc1_clk_125m
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
@@ -1070,7 +1290,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
Logical resource: cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X4Y80.CLKA
+ Location pin: RAMB16_X4Y76.CLKA
Clock network: tdc1_clk_125m
--------------------------------------------------------------------------------
@@ -1091,7 +1311,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
Logical resource: cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X4Y10.CLKA
+ Location pin: RAMB16_X1Y18.CLKA
Clock network: tdc2_clk_125m
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
@@ -1099,7 +1319,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKB)
Physical resource: cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
Logical resource: cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
- Location pin: RAMB16_X4Y10.CLKB
+ Location pin: RAMB16_X1Y18.CLKB
Clock network: tdc2_clk_125m
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
@@ -1107,7 +1327,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
Logical resource: cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X3Y14.CLKA
+ Location pin: RAMB16_X2Y20.CLKA
Clock network: tdc2_clk_125m
--------------------------------------------------------------------------------
@@ -1116,19 +1336,19 @@ Timing constraint: TS_tdc2_tdc_125m_clk_n_i = PERIOD TIMEGRP
"tdc2_125m_clk_n_i" 8 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
- 474724 paths analyzed, 9716 endpoints analyzed, 0 failing endpoints
+ 454435 paths analyzed, 9913 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is 7.706ns.
+ Minimum period is 7.765ns.
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_14 (SLICE_X28Y16.B1), 63 paths
+Paths for end point cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_14 (SLICE_X31Y11.CE), 21 paths
--------------------------------------------------------------------------------
-Slack (setup path): 0.294ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_3 (FF)
- Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_14 (FF)
+Slack (setup path): 0.235ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/cmp_xwb_reg/r_master_adr_5 (FF)
+ Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_14 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.660ns (Levels of Logic = 5)
- Clock Path Skew: -0.011ns (0.246 - 0.257)
+ Data Path Delay: 7.852ns (Levels of Logic = 3)
+ Clock Path Skew: 0.122ns (0.942 - 0.820)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1139,39 +1359,35 @@ Slack (setup path): 0.294ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_3 to cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_14
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_xwb_reg/r_master_adr_5 to cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_14
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X33Y18.AQ Tcko 0.391 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<6>
- cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_3
- SLICE_X30Y17.B5 net (fanout=116) 0.621 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<3>
- SLICE_X30Y17.B Tilo 0.203 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_0<31>
- cmp_tdc2/cmp_tdc_core/reg_control_block/_n0569<7>21
- SLICE_X38Y17.B6 net (fanout=8) 1.201 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0569<7>2
- SLICE_X38Y17.B Tilo 0.205 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0822
- cmp_tdc2/cmp_tdc_core/reg_control_block/_n0831<7>1
- SLICE_X45Y16.C4 net (fanout=32) 1.346 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0831
- SLICE_X45Y16.C Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/one_hz_phase<15>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out722
- SLICE_X42Y16.B3 net (fanout=2) 0.701 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out721
- SLICE_X42Y16.B Tilo 0.205 N1525
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out7217_SW0
- SLICE_X28Y16.B1 net (fanout=1) 2.187 N1525
- SLICE_X28Y16.CLK Tas 0.341 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<15>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out7218
- cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_14
+ SLICE_X42Y34.DQ Tcko 0.408 cmp_tdc2/cmp_xwb_reg/r_master_adr<5>
+ cmp_tdc2/cmp_xwb_reg/r_master_adr_5
+ SLICE_X37Y16.B4 net (fanout=6) 2.304 cmp_tdc2/cmp_xwb_reg/r_master_adr<5>
+ SLICE_X37Y16.B Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<1>
+ cmp_tdc2/cmp_sdb_crossbar/crossbar/master_oe[1]_adr<5>1
+ SLICE_X38Y20.B5 net (fanout=6) 0.785 cmp_tdc2/cnx_master_out[1]_adr<5>
+ SLICE_X38Y20.B Tilo 0.205 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_2<3>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/_n0486_inv11
+ SLICE_X36Y20.D2 net (fanout=4) 0.915 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0486_inv1
+ SLICE_X36Y20.D Tilo 0.203 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_5<3>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/_n0505_inv1
+ SLICE_X31Y11.CE net (fanout=8) 2.433 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0505_inv
+ SLICE_X31Y11.CLK Tceck 0.340 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8<15>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_14
------------------------------------------------- ---------------------------
- Total 7.660ns (1.604ns logic, 6.056ns route)
- (20.9% logic, 79.1% route)
+ Total 7.852ns (1.415ns logic, 6.437ns route)
+ (18.0% logic, 82.0% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.344ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_2 (FF)
- Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_14 (FF)
+Slack (setup path): 0.433ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/cmp_xwb_reg/r_slave_stall (FF)
+ Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_14 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.610ns (Levels of Logic = 5)
- Clock Path Skew: -0.011ns (0.246 - 0.257)
+ Data Path Delay: 7.651ns (Levels of Logic = 3)
+ Clock Path Skew: 0.119ns (0.942 - 0.823)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1182,39 +1398,35 @@ Slack (setup path): 0.344ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_2 to cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_14
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_xwb_reg/r_slave_stall to cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_14
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X33Y18.CQ Tcko 0.391 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<6>
- cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_2
- SLICE_X30Y17.B4 net (fanout=66) 0.571 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<2>
- SLICE_X30Y17.B Tilo 0.203 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_0<31>
- cmp_tdc2/cmp_tdc_core/reg_control_block/_n0569<7>21
- SLICE_X38Y17.B6 net (fanout=8) 1.201 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0569<7>2
- SLICE_X38Y17.B Tilo 0.205 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0822
- cmp_tdc2/cmp_tdc_core/reg_control_block/_n0831<7>1
- SLICE_X45Y16.C4 net (fanout=32) 1.346 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0831
- SLICE_X45Y16.C Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/one_hz_phase<15>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out722
- SLICE_X42Y16.B3 net (fanout=2) 0.701 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out721
- SLICE_X42Y16.B Tilo 0.205 N1525
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out7217_SW0
- SLICE_X28Y16.B1 net (fanout=1) 2.187 N1525
- SLICE_X28Y16.CLK Tas 0.341 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<15>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out7218
- cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_14
+ SLICE_X42Y46.BMUX Tshcko 0.455 cmp_tdc2_clks_crossing/sw_en
+ cmp_tdc2/cmp_xwb_reg/r_slave_stall
+ SLICE_X41Y34.A5 net (fanout=15) 1.675 cmp_tdc2/cmp_xwb_reg/r_slave_stall
+ SLICE_X41Y34.A Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_ack_o_pipe0
+ cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_stb_i_GND_552_o_MUX_12270_o1
+ SLICE_X38Y20.B6 net (fanout=4) 1.166 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_stb_i_GND_552_o_MUX_12270_o
+ SLICE_X38Y20.B Tilo 0.205 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_2<3>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/_n0486_inv11
+ SLICE_X36Y20.D2 net (fanout=4) 0.915 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0486_inv1
+ SLICE_X36Y20.D Tilo 0.203 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_5<3>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/_n0505_inv1
+ SLICE_X31Y11.CE net (fanout=8) 2.433 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0505_inv
+ SLICE_X31Y11.CLK Tceck 0.340 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8<15>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_14
------------------------------------------------- ---------------------------
- Total 7.610ns (1.604ns logic, 6.006ns route)
- (21.1% logic, 78.9% route)
+ Total 7.651ns (1.462ns logic, 6.189ns route)
+ (19.1% logic, 80.9% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.503ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0 (FF)
- Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_14 (FF)
+Slack (setup path): 0.452ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/cmp_sdb_crossbar/crossbar/matrix_old_0_1 (FF)
+ Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_14 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.451ns (Levels of Logic = 5)
- Clock Path Skew: -0.011ns (0.246 - 0.257)
+ Data Path Delay: 7.634ns (Levels of Logic = 3)
+ Clock Path Skew: 0.121ns (0.942 - 0.821)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1225,42 +1437,38 @@ Slack (setup path): 0.503ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0 to cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_14
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_sdb_crossbar/crossbar/matrix_old_0_1 to cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_14
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X30Y18.AQ Tcko 0.447 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<0>
- cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0
- SLICE_X30Y17.B6 net (fanout=74) 0.356 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<0>
- SLICE_X30Y17.B Tilo 0.203 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_0<31>
- cmp_tdc2/cmp_tdc_core/reg_control_block/_n0569<7>21
- SLICE_X38Y17.B6 net (fanout=8) 1.201 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0569<7>2
- SLICE_X38Y17.B Tilo 0.205 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0822
- cmp_tdc2/cmp_tdc_core/reg_control_block/_n0831<7>1
- SLICE_X45Y16.C4 net (fanout=32) 1.346 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0831
- SLICE_X45Y16.C Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/one_hz_phase<15>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out722
- SLICE_X42Y16.B3 net (fanout=2) 0.701 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out721
- SLICE_X42Y16.B Tilo 0.205 N1525
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out7217_SW0
- SLICE_X28Y16.B1 net (fanout=1) 2.187 N1525
- SLICE_X28Y16.CLK Tas 0.341 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<15>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out7218
- cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_14
+ SLICE_X43Y33.CQ Tcko 0.391 cmp_tdc2/cmp_sdb_crossbar/crossbar/matrix_old_0<1>
+ cmp_tdc2/cmp_sdb_crossbar/crossbar/matrix_old_0_1
+ SLICE_X39Y17.B5 net (fanout=100) 1.970 cmp_tdc2/cmp_sdb_crossbar/crossbar/matrix_old_0<1>
+ SLICE_X39Y17.B Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<7>
+ cmp_tdc2/cmp_sdb_crossbar/crossbar/master_oe[1]_adr<9>1
+ SLICE_X38Y20.B2 net (fanout=4) 0.918 cmp_tdc2/cnx_master_out[1]_adr<9>
+ SLICE_X38Y20.B Tilo 0.205 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_2<3>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/_n0486_inv11
+ SLICE_X36Y20.D2 net (fanout=4) 0.915 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0486_inv1
+ SLICE_X36Y20.D Tilo 0.203 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_5<3>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/_n0505_inv1
+ SLICE_X31Y11.CE net (fanout=8) 2.433 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0505_inv
+ SLICE_X31Y11.CLK Tceck 0.340 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8<15>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_14
------------------------------------------------- ---------------------------
- Total 7.451ns (1.660ns logic, 5.791ns route)
- (22.3% logic, 77.7% route)
+ Total 7.634ns (1.398ns logic, 6.236ns route)
+ (18.3% logic, 81.7% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_31 (SLICE_X36Y19.D5), 564 paths
+Paths for end point cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_13 (SLICE_X31Y11.CE), 21 paths
--------------------------------------------------------------------------------
-Slack (setup path): 0.319ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_7 (FF)
- Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_31 (FF)
+Slack (setup path): 0.251ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/cmp_xwb_reg/r_master_adr_5 (FF)
+ Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_13 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.631ns (Levels of Logic = 8)
- Clock Path Skew: -0.015ns (0.241 - 0.256)
+ Data Path Delay: 7.836ns (Levels of Logic = 3)
+ Clock Path Skew: 0.122ns (0.942 - 0.820)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1271,48 +1479,35 @@ Slack (setup path): 0.319ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_7 to cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_31
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_xwb_reg/r_master_adr_5 to cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_13
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X33Y19.AQ Tcko 0.391 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<4>
- cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_7
- SLICE_X33Y16.A5 net (fanout=33) 0.765 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<7>
- SLICE_X33Y16.A Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out3008
- cmp_tdc2/cmp_tdc_core/reg_control_block/_n0585<7>11
- SLICE_X31Y18.C6 net (fanout=38) 0.610 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0585<7>1
- SLICE_X31Y18.C Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out3009
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out11011
- SLICE_X31Y18.D6 net (fanout=32) 1.378 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out1101
- SLICE_X31Y18.D Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out3009
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30010
- SLICE_X33Y16.C4 net (fanout=2) 0.674 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out3009
- SLICE_X33Y16.C Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out3008
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30012_SW0
- SLICE_X35Y18.D5 net (fanout=1) 0.645 N1012
- SLICE_X35Y18.D Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_2<24>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30014_SW0_SW0
- SLICE_X35Y18.C6 net (fanout=1) 0.118 N1410
- SLICE_X35Y18.C Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_2<24>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30015_SW1
- SLICE_X36Y19.C5 net (fanout=1) 0.808 N2328
- SLICE_X36Y19.C Tilo 0.204 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30015
- SLICE_X36Y19.D5 net (fanout=1) 0.195 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30014
- SLICE_X36Y19.CLK Tas 0.289 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30017
- cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_31
+ SLICE_X42Y34.DQ Tcko 0.408 cmp_tdc2/cmp_xwb_reg/r_master_adr<5>
+ cmp_tdc2/cmp_xwb_reg/r_master_adr_5
+ SLICE_X37Y16.B4 net (fanout=6) 2.304 cmp_tdc2/cmp_xwb_reg/r_master_adr<5>
+ SLICE_X37Y16.B Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<1>
+ cmp_tdc2/cmp_sdb_crossbar/crossbar/master_oe[1]_adr<5>1
+ SLICE_X38Y20.B5 net (fanout=6) 0.785 cmp_tdc2/cnx_master_out[1]_adr<5>
+ SLICE_X38Y20.B Tilo 0.205 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_2<3>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/_n0486_inv11
+ SLICE_X36Y20.D2 net (fanout=4) 0.915 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0486_inv1
+ SLICE_X36Y20.D Tilo 0.203 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_5<3>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/_n0505_inv1
+ SLICE_X31Y11.CE net (fanout=8) 2.433 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0505_inv
+ SLICE_X31Y11.CLK Tceck 0.324 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8<15>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_13
------------------------------------------------- ---------------------------
- Total 7.631ns (2.438ns logic, 5.193ns route)
- (31.9% logic, 68.1% route)
+ Total 7.836ns (1.399ns logic, 6.437ns route)
+ (17.9% logic, 82.1% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.471ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_7 (FF)
- Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_31 (FF)
+Slack (setup path): 0.449ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/cmp_xwb_reg/r_slave_stall (FF)
+ Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_13 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.479ns (Levels of Logic = 8)
- Clock Path Skew: -0.015ns (0.241 - 0.256)
+ Data Path Delay: 7.635ns (Levels of Logic = 3)
+ Clock Path Skew: 0.119ns (0.942 - 0.823)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1323,48 +1518,35 @@ Slack (setup path): 0.471ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_7 to cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_31
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_xwb_reg/r_slave_stall to cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_13
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X33Y19.AQ Tcko 0.391 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<4>
- cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_7
- SLICE_X33Y16.A5 net (fanout=33) 0.765 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<7>
- SLICE_X33Y16.A Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out3008
- cmp_tdc2/cmp_tdc_core/reg_control_block/_n0585<7>11
- SLICE_X28Y20.B6 net (fanout=38) 0.978 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0585<7>1
- SLICE_X28Y20.B Tilo 0.205 N2166
- cmp_tdc2/cmp_tdc_core/reg_control_block/_n0634<7>1
- SLICE_X33Y16.D1 net (fanout=32) 1.460 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0634
- SLICE_X33Y16.D Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out3008
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out3009
- SLICE_X33Y16.C6 net (fanout=2) 0.126 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out3008
- SLICE_X33Y16.C Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out3008
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30012_SW0
- SLICE_X35Y18.D5 net (fanout=1) 0.645 N1012
- SLICE_X35Y18.D Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_2<24>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30014_SW0_SW0
- SLICE_X35Y18.C6 net (fanout=1) 0.118 N1410
- SLICE_X35Y18.C Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_2<24>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30015_SW1
- SLICE_X36Y19.C5 net (fanout=1) 0.808 N2328
- SLICE_X36Y19.C Tilo 0.204 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30015
- SLICE_X36Y19.D5 net (fanout=1) 0.195 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30014
- SLICE_X36Y19.CLK Tas 0.289 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30017
- cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_31
+ SLICE_X42Y46.BMUX Tshcko 0.455 cmp_tdc2_clks_crossing/sw_en
+ cmp_tdc2/cmp_xwb_reg/r_slave_stall
+ SLICE_X41Y34.A5 net (fanout=15) 1.675 cmp_tdc2/cmp_xwb_reg/r_slave_stall
+ SLICE_X41Y34.A Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_ack_o_pipe0
+ cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_stb_i_GND_552_o_MUX_12270_o1
+ SLICE_X38Y20.B6 net (fanout=4) 1.166 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_stb_i_GND_552_o_MUX_12270_o
+ SLICE_X38Y20.B Tilo 0.205 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_2<3>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/_n0486_inv11
+ SLICE_X36Y20.D2 net (fanout=4) 0.915 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0486_inv1
+ SLICE_X36Y20.D Tilo 0.203 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_5<3>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/_n0505_inv1
+ SLICE_X31Y11.CE net (fanout=8) 2.433 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0505_inv
+ SLICE_X31Y11.CLK Tceck 0.324 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8<15>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_13
------------------------------------------------- ---------------------------
- Total 7.479ns (2.384ns logic, 5.095ns route)
- (31.9% logic, 68.1% route)
+ Total 7.635ns (1.446ns logic, 6.189ns route)
+ (18.9% logic, 81.1% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.485ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0_1 (FF)
- Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_31 (FF)
+Slack (setup path): 0.468ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/cmp_sdb_crossbar/crossbar/matrix_old_0_1 (FF)
+ Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_13 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.462ns (Levels of Logic = 8)
- Clock Path Skew: -0.018ns (0.241 - 0.259)
+ Data Path Delay: 7.618ns (Levels of Logic = 3)
+ Clock Path Skew: 0.121ns (0.942 - 0.821)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1375,51 +1557,38 @@ Slack (setup path): 0.485ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0_1 to cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_31
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_sdb_crossbar/crossbar/matrix_old_0_1 to cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_13
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X33Y17.BQ Tcko 0.391 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0_1
- cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0_1
- SLICE_X33Y16.A1 net (fanout=1) 0.596 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0_1
- SLICE_X33Y16.A Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out3008
- cmp_tdc2/cmp_tdc_core/reg_control_block/_n0585<7>11
- SLICE_X31Y18.C6 net (fanout=38) 0.610 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0585<7>1
- SLICE_X31Y18.C Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out3009
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out11011
- SLICE_X31Y18.D6 net (fanout=32) 1.378 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out1101
- SLICE_X31Y18.D Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out3009
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30010
- SLICE_X33Y16.C4 net (fanout=2) 0.674 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out3009
- SLICE_X33Y16.C Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out3008
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30012_SW0
- SLICE_X35Y18.D5 net (fanout=1) 0.645 N1012
- SLICE_X35Y18.D Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_2<24>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30014_SW0_SW0
- SLICE_X35Y18.C6 net (fanout=1) 0.118 N1410
- SLICE_X35Y18.C Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_2<24>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30015_SW1
- SLICE_X36Y19.C5 net (fanout=1) 0.808 N2328
- SLICE_X36Y19.C Tilo 0.204 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30015
- SLICE_X36Y19.D5 net (fanout=1) 0.195 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30014
- SLICE_X36Y19.CLK Tas 0.289 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out30017
- cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_31
+ SLICE_X43Y33.CQ Tcko 0.391 cmp_tdc2/cmp_sdb_crossbar/crossbar/matrix_old_0<1>
+ cmp_tdc2/cmp_sdb_crossbar/crossbar/matrix_old_0_1
+ SLICE_X39Y17.B5 net (fanout=100) 1.970 cmp_tdc2/cmp_sdb_crossbar/crossbar/matrix_old_0<1>
+ SLICE_X39Y17.B Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<7>
+ cmp_tdc2/cmp_sdb_crossbar/crossbar/master_oe[1]_adr<9>1
+ SLICE_X38Y20.B2 net (fanout=4) 0.918 cmp_tdc2/cnx_master_out[1]_adr<9>
+ SLICE_X38Y20.B Tilo 0.205 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_2<3>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/_n0486_inv11
+ SLICE_X36Y20.D2 net (fanout=4) 0.915 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0486_inv1
+ SLICE_X36Y20.D Tilo 0.203 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_5<3>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/_n0505_inv1
+ SLICE_X31Y11.CE net (fanout=8) 2.433 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0505_inv
+ SLICE_X31Y11.CLK Tceck 0.324 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8<15>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_8_13
------------------------------------------------- ---------------------------
- Total 7.462ns (2.438ns logic, 5.024ns route)
- (32.7% logic, 67.3% route)
+ Total 7.618ns (1.382ns logic, 6.236ns route)
+ (18.1% logic, 81.9% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_8 (SLICE_X30Y16.A5), 458 paths
+Paths for end point cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_19 (SLICE_X30Y18.C6), 541 paths
--------------------------------------------------------------------------------
-Slack (setup path): 0.371ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_3 (FF)
- Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_8 (FF)
+Slack (setup path): 0.253ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_3_19 (FF)
+ Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_19 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.582ns (Levels of Logic = 7)
- Clock Path Skew: -0.012ns (0.245 - 0.257)
+ Data Path Delay: 7.627ns (Levels of Logic = 6)
+ Clock Path Skew: -0.085ns (0.879 - 0.964)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1430,45 +1599,42 @@ Slack (setup path): 0.371ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_3 to cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_8
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_3_19 to cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_19
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X33Y18.AQ Tcko 0.391 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<6>
- cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_3
- SLICE_X32Y18.A2 net (fanout=116) 1.137 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<3>
- SLICE_X32Y18.A Tilo 0.205 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_7_1
- cmp_tdc2/cmp_tdc_core/reg_control_block/_n0611<7>1
- SLICE_X29Y18.B3 net (fanout=32) 2.392 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0611
- SLICE_X29Y18.B Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out16812
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37211
- SLICE_X29Y18.A5 net (fanout=1) 0.187 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37210
- SLICE_X29Y18.A Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out16812
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37213
- SLICE_X26Y14.B6 net (fanout=1) 0.618 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37212
- SLICE_X26Y14.B Tilo 0.203 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_4<3>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37214
- SLICE_X26Y14.A5 net (fanout=1) 0.222 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37213
- SLICE_X26Y14.A Tilo 0.203 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_4<3>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37215
- SLICE_X30Y16.B5 net (fanout=1) 0.792 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37214
- SLICE_X30Y16.B Tilo 0.203 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<9>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37216
- SLICE_X30Y16.A5 net (fanout=1) 0.222 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37215
- SLICE_X30Y16.CLK Tas 0.289 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<9>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37217
- cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_8
+ SLICE_X29Y10.DQ Tcko 0.391 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_3<19>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_3_19
+ SLICE_X36Y19.C4 net (fanout=2) 2.651 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_3<19>
+ SLICE_X36Y19.C Tilo 0.204 cmp_tdc2/cmp_tdc_core/reg_control_block/acam_config_10<3>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13211
+ SLICE_X31Y9.C5 net (fanout=1) 1.725 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13210
+ SLICE_X31Y9.C Tilo 0.259 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_7<3>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13214
+ SLICE_X31Y13.B5 net (fanout=1) 0.570 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13213
+ SLICE_X31Y13.B Tilo 0.259 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_6<19>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13215
+ SLICE_X31Y13.A5 net (fanout=1) 0.187 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13214
+ SLICE_X31Y13.A Tilo 0.259 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_6<19>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13216
+ SLICE_X30Y18.D6 net (fanout=1) 0.512 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13215
+ SLICE_X30Y18.D Tilo 0.203 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<19>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13218_SW0
+ SLICE_X30Y18.C6 net (fanout=1) 0.118 N2719
+ SLICE_X30Y18.CLK Tas 0.289 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<19>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13218
+ cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_19
------------------------------------------------- ---------------------------
- Total 7.582ns (2.012ns logic, 5.570ns route)
- (26.5% logic, 73.5% route)
+ Total 7.627ns (1.864ns logic, 5.763ns route)
+ (24.4% logic, 75.6% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.571ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5_1 (FF)
- Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_8 (FF)
+Slack (setup path): 0.343ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0 (FF)
+ Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_19 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.380ns (Levels of Logic = 8)
- Clock Path Skew: -0.014ns (0.245 - 0.259)
+ Data Path Delay: 7.607ns (Levels of Logic = 8)
+ Clock Path Skew: -0.015ns (0.244 - 0.259)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1479,48 +1645,48 @@ Slack (setup path): 0.571ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5_1 to cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_8
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0 to cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_19
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X32Y17.AQ Tcko 0.408 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5_1
- cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5_1
- SLICE_X32Y18.B3 net (fanout=3) 0.497 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5_1
- SLICE_X32Y18.B Tilo 0.205 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_7_1
- cmp_tdc2/cmp_tdc_core/reg_control_block/_n0569<7>11
- SLICE_X32Y18.A5 net (fanout=17) 0.216 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0569<7>1
- SLICE_X32Y18.A Tilo 0.205 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_7_1
- cmp_tdc2/cmp_tdc_core/reg_control_block/_n0611<7>1
- SLICE_X29Y18.B3 net (fanout=32) 2.392 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0611
- SLICE_X29Y18.B Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out16812
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37211
- SLICE_X29Y18.A5 net (fanout=1) 0.187 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37210
- SLICE_X29Y18.A Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out16812
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37213
- SLICE_X26Y14.B6 net (fanout=1) 0.618 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37212
- SLICE_X26Y14.B Tilo 0.203 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_4<3>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37214
- SLICE_X26Y14.A5 net (fanout=1) 0.222 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37213
- SLICE_X26Y14.A Tilo 0.203 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_4<3>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37215
- SLICE_X30Y16.B5 net (fanout=1) 0.792 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37214
- SLICE_X30Y16.B Tilo 0.203 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<9>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37216
- SLICE_X30Y16.A5 net (fanout=1) 0.222 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37215
- SLICE_X30Y16.CLK Tas 0.289 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<9>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37217
- cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_8
+ SLICE_X40Y17.BQ Tcko 0.447 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<3>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_0
+ SLICE_X36Y17.A1 net (fanout=34) 0.768 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<0>
+ SLICE_X36Y17.A Tilo 0.203 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_4<25>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/_n0576<7>11
+ SLICE_X33Y17.A5 net (fanout=15) 0.801 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0576<7>1
+ SLICE_X33Y17.A Tilo 0.259 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_10<27>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out10011
+ SLICE_X32Y8.D4 net (fanout=30) 1.531 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out1001
+ SLICE_X32Y8.D Tilo 0.205 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_5<27>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out1329
+ SLICE_X31Y9.C3 net (fanout=1) 0.737 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out1328
+ SLICE_X31Y9.C Tilo 0.259 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_7<3>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13214
+ SLICE_X31Y13.B5 net (fanout=1) 0.570 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13213
+ SLICE_X31Y13.B Tilo 0.259 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_6<19>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13215
+ SLICE_X31Y13.A5 net (fanout=1) 0.187 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13214
+ SLICE_X31Y13.A Tilo 0.259 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_6<19>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13216
+ SLICE_X30Y18.D6 net (fanout=1) 0.512 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13215
+ SLICE_X30Y18.D Tilo 0.203 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<19>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13218_SW0
+ SLICE_X30Y18.C6 net (fanout=1) 0.118 N2719
+ SLICE_X30Y18.CLK Tas 0.289 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<19>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13218
+ cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_19
------------------------------------------------- ---------------------------
- Total 7.380ns (2.234ns logic, 5.146ns route)
- (30.3% logic, 69.7% route)
+ Total 7.607ns (2.383ns logic, 5.224ns route)
+ (31.3% logic, 68.7% route)
--------------------------------------------------------------------------------
-Slack (setup path): 0.604ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1 (FF)
- Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_8 (FF)
+Slack (setup path): 0.511ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5 (FF)
+ Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_19 (FF)
Requirement: 8.000ns
- Data Path Delay: 7.349ns (Levels of Logic = 8)
- Clock Path Skew: -0.012ns (0.245 - 0.257)
+ Data Path Delay: 7.438ns (Levels of Logic = 7)
+ Clock Path Skew: -0.016ns (0.244 - 0.260)
Source Clock: tdc2_clk_125m rising at 0.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.035ns
@@ -1531,127 +1697,121 @@ Slack (setup path): 0.604ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
- Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1 to cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_8
+ Maximum Data Path at Slow Process Corner: cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5 to cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_19
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X32Y18.AQ Tcko 0.408 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_7_1
- cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- SLICE_X32Y18.B2 net (fanout=3) 0.466 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- SLICE_X32Y18.B Tilo 0.205 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_7_1
- cmp_tdc2/cmp_tdc_core/reg_control_block/_n0569<7>11
- SLICE_X32Y18.A5 net (fanout=17) 0.216 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0569<7>1
- SLICE_X32Y18.A Tilo 0.205 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_7_1
- cmp_tdc2/cmp_tdc_core/reg_control_block/_n0611<7>1
- SLICE_X29Y18.B3 net (fanout=32) 2.392 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0611
- SLICE_X29Y18.B Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out16812
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37211
- SLICE_X29Y18.A5 net (fanout=1) 0.187 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37210
- SLICE_X29Y18.A Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out16812
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37213
- SLICE_X26Y14.B6 net (fanout=1) 0.618 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37212
- SLICE_X26Y14.B Tilo 0.203 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_4<3>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37214
- SLICE_X26Y14.A5 net (fanout=1) 0.222 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37213
- SLICE_X26Y14.A Tilo 0.203 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_4<3>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37215
- SLICE_X30Y16.B5 net (fanout=1) 0.792 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37214
- SLICE_X30Y16.B Tilo 0.203 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<9>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37216
- SLICE_X30Y16.A5 net (fanout=1) 0.222 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37215
- SLICE_X30Y16.CLK Tas 0.289 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<9>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out37217
- cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_8
+ SLICE_X37Y16.CQ Tcko 0.391 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<1>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5
+ SLICE_X37Y17.A4 net (fanout=9) 0.450 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0<5>
+ SLICE_X37Y17.A Tilo 0.259 cmp_tdc2/cmp_tdc_core/reg_control_block/reg_adr_pipe0_3_1
+ cmp_tdc2/cmp_tdc_core/reg_control_block/_n0585<7>11
+ SLICE_X47Y16.B5 net (fanout=16) 0.961 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0585<7>1
+ SLICE_X47Y16.B Tilo 0.259 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_1<27>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/_n0687<7>1
+ SLICE_X31Y13.C6 net (fanout=30) 2.705 cmp_tdc2/cmp_tdc_core/reg_control_block/_n0687
+ SLICE_X31Y13.C Tilo 0.259 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_6<19>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out1328
+ SLICE_X31Y13.B4 net (fanout=1) 0.327 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out1327
+ SLICE_X31Y13.B Tilo 0.259 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_6<19>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13215
+ SLICE_X31Y13.A5 net (fanout=1) 0.187 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13214
+ SLICE_X31Y13.A Tilo 0.259 cmp_tdc2/cmp_tdc_core/data_engine_block/acam_config_rdbk_6<19>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13216
+ SLICE_X30Y18.D6 net (fanout=1) 0.512 cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13215
+ SLICE_X30Y18.D Tilo 0.203 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<19>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13218_SW0
+ SLICE_X30Y18.C6 net (fanout=1) 0.118 N2719
+ SLICE_X30Y18.CLK Tas 0.289 cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<19>
+ cmp_tdc2/cmp_tdc_core/reg_control_block/Mmux_dat_out13218
+ cmp_tdc2/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_19
------------------------------------------------- ---------------------------
- Total 7.349ns (2.234ns logic, 5.115ns route)
- (30.4% logic, 69.6% route)
+ Total 7.438ns (2.178ns logic, 5.260ns route)
+ (29.3% logic, 70.7% route)
--------------------------------------------------------------------------------
Hold Paths: TS_tdc2_tdc_125m_clk_n_i = PERIOD TIMEGRP "tdc2_125m_clk_n_i" 8 ns HIGH 50%;
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter_0 (SLICE_X47Y26.C5), 1 path
+Paths for end point cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAMB16_X2Y18.DIA29), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.410ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc2/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter_1 (FF)
- Destination: cmp_tdc2/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter_0 (FF)
+Slack (hold path): 0.278ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc2/cmp_tdc_core/start_retrigger_block/roll_over_c_2 (FF)
+ Destination: cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
Requirement: 0.000ns
- Data Path Delay: 0.410ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
+ Data Path Delay: 0.284ns (Levels of Logic = 0)
+ Clock Path Skew: 0.006ns (0.069 - 0.063)
Source Clock: tdc2_clk_125m rising at 8.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc2/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter_1 to cmp_tdc2/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter_0
+ Minimum Data Path at Fast Process Corner: cmp_tdc2/cmp_tdc_core/start_retrigger_block/roll_over_c_2 to cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X47Y26.CQ Tcko 0.198 cmp_tdc2/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter<1>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter_1
- SLICE_X47Y26.C5 net (fanout=2) 0.057 cmp_tdc2/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter<1>
- SLICE_X47Y26.CLK Tah (-Th) -0.155 cmp_tdc2/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter<1>
- cmp_tdc2/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter_0_glue_set
- cmp_tdc2/cmp_tdc_core/reg_control_block/Pulse_stretcher/counter_0
+ SLICE_X42Y38.CQ Tcko 0.200 cmp_tdc2/cmp_tdc_core/start_retrigger_block/roll_over_c<3>
+ cmp_tdc2/cmp_tdc_core/start_retrigger_block/roll_over_c_2
+ RAMB16_X2Y18.DIA29 net (fanout=8) 0.137 cmp_tdc2/cmp_tdc_core/start_retrigger_block/roll_over_c<2>
+ RAMB16_X2Y18.CLKA Trckd_DIA (-Th) 0.053 cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
------------------------------------------------- ---------------------------
- Total 0.410ns (0.353ns logic, 0.057ns route)
- (86.1% logic, 13.9% route)
+ Total 0.284ns (0.147ns logic, 0.137ns route)
+ (51.8% logic, 48.2% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/slave_wait (SLICE_X42Y37.A6), 1 path
+Paths for end point cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAMB16_X2Y18.DIA28), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.411ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc2/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/slave_wait (FF)
- Destination: cmp_tdc2/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/slave_wait (FF)
+Slack (hold path): 0.293ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc2/cmp_tdc_core/start_retrigger_block/roll_over_c_1 (FF)
+ Destination: cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
Requirement: 0.000ns
- Data Path Delay: 0.411ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
+ Data Path Delay: 0.299ns (Levels of Logic = 0)
+ Clock Path Skew: 0.006ns (0.069 - 0.063)
Source Clock: tdc2_clk_125m rising at 8.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc2/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/slave_wait to cmp_tdc2/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/slave_wait
+ Minimum Data Path at Fast Process Corner: cmp_tdc2/cmp_tdc_core/start_retrigger_block/roll_over_c_1 to cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X42Y37.AQ Tcko 0.200 cmp_tdc2/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/slave_wait
- cmp_tdc2/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/slave_wait
- SLICE_X42Y37.A6 net (fanout=2) 0.021 cmp_tdc2/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/slave_wait
- SLICE_X42Y37.CLK Tah (-Th) -0.190 cmp_tdc2/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/slave_wait
- cmp_tdc2/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/iscl_oen_slave_wait_OR_4035_o1
- cmp_tdc2/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/slave_wait
+ SLICE_X42Y38.BQ Tcko 0.200 cmp_tdc2/cmp_tdc_core/start_retrigger_block/roll_over_c<3>
+ cmp_tdc2/cmp_tdc_core/start_retrigger_block/roll_over_c_1
+ RAMB16_X2Y18.DIA28 net (fanout=8) 0.152 cmp_tdc2/cmp_tdc_core/start_retrigger_block/roll_over_c<1>
+ RAMB16_X2Y18.CLKA Trckd_DIA (-Th) 0.053 cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
------------------------------------------------- ---------------------------
- Total 0.411ns (0.390ns logic, 0.021ns route)
- (94.9% logic, 5.1% route)
+ Total 0.299ns (0.147ns logic, 0.152ns route)
+ (49.2% logic, 50.8% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_tdc2/cmp_fmc_onewire/U_Wrapped_1W/Wrapped_1wire/irq_sts (SLICE_X70Y32.A6), 1 path
+Paths for end point cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAMB16_X1Y16.DIA1), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.411ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc2/cmp_fmc_onewire/U_Wrapped_1W/Wrapped_1wire/irq_sts (FF)
- Destination: cmp_tdc2/cmp_fmc_onewire/U_Wrapped_1W/Wrapped_1wire/irq_sts (FF)
+Slack (hold path): 0.307ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_tdc2/cmp_tdc_core/data_formatting_block/acam_fine_timestamp_1 (FF)
+ Destination: cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
Requirement: 0.000ns
- Data Path Delay: 0.411ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
+ Data Path Delay: 0.309ns (Levels of Logic = 0)
+ Clock Path Skew: 0.002ns (0.079 - 0.077)
Source Clock: tdc2_clk_125m rising at 8.000ns
Destination Clock: tdc2_clk_125m rising at 8.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path at Fast Process Corner: cmp_tdc2/cmp_fmc_onewire/U_Wrapped_1W/Wrapped_1wire/irq_sts to cmp_tdc2/cmp_fmc_onewire/U_Wrapped_1W/Wrapped_1wire/irq_sts
+ Minimum Data Path at Fast Process Corner: cmp_tdc2/cmp_tdc_core/data_formatting_block/acam_fine_timestamp_1 to cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X70Y32.AQ Tcko 0.200 cmp_tdc2/cmp_fmc_onewire/U_Wrapped_1W/Wrapped_1wire/owr_oen
- cmp_tdc2/cmp_fmc_onewire/U_Wrapped_1W/Wrapped_1wire/irq_sts
- SLICE_X70Y32.A6 net (fanout=2) 0.021 cmp_tdc2/cmp_fmc_onewire/U_Wrapped_1W/Wrapped_1wire/irq_sts
- SLICE_X70Y32.CLK Tah (-Th) -0.190 cmp_tdc2/cmp_fmc_onewire/U_Wrapped_1W/Wrapped_1wire/owr_oen
- cmp_tdc2/cmp_fmc_onewire/U_Wrapped_1W/Wrapped_1wire/irq_sts_rstpot
- cmp_tdc2/cmp_fmc_onewire/U_Wrapped_1W/Wrapped_1wire/irq_sts
+ SLICE_X26Y32.BQ Tcko 0.234 cmp_tdc2/cmp_tdc_core/data_formatting_block/acam_fine_timestamp<3>
+ cmp_tdc2/cmp_tdc_core/data_formatting_block/acam_fine_timestamp_1
+ RAMB16_X1Y16.DIA1 net (fanout=2) 0.128 cmp_tdc2/cmp_tdc_core/data_formatting_block/acam_fine_timestamp<1>
+ RAMB16_X1Y16.CLKA Trckd_DIA (-Th) 0.053 cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
+ cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
------------------------------------------------- ---------------------------
- Total 0.411ns (0.390ns logic, 0.021ns route)
- (94.9% logic, 5.1% route)
+ Total 0.309ns (0.181ns logic, 0.128ns route)
+ (58.6% logic, 41.4% route)
--------------------------------------------------------------------------------
@@ -1662,7 +1822,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
Logical resource: cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X4Y10.CLKA
+ Location pin: RAMB16_X1Y18.CLKA
Clock network: tdc2_clk_125m
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
@@ -1670,7 +1830,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKB)
Physical resource: cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
Logical resource: cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
- Location pin: RAMB16_X4Y10.CLKB
+ Location pin: RAMB16_X1Y18.CLKB
Clock network: tdc2_clk_125m
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
@@ -1678,7 +1838,7 @@ Slack: 4.876ns (period - min period limit)
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
Logical resource: cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X3Y14.CLKA
+ Location pin: RAMB16_X2Y20.CLKA
Clock network: tdc2_clk_125m
--------------------------------------------------------------------------------
@@ -1699,7 +1859,7 @@ Slack: 4.875ns (period - min period limit)
Min period limit: 3.125ns (320.000MHz) (Tgtpcper_CLK)
Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/CLK01
Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/CLK01
- Location pin: GTPA1_DUAL_X0Y0.CLK01
+ Location pin: GTPA1_DUAL_X1Y1.CLK11
Clock network: clk_125m_gtp
--------------------------------------------------------------------------------
@@ -1720,7 +1880,7 @@ Slack: 4.875ns (period - min period limit)
Min period limit: 3.125ns (320.000MHz) (Tgtpcper_CLK)
Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/CLK01
Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/CLK01
- Location pin: GTPA1_DUAL_X0Y0.CLK01
+ Location pin: GTPA1_DUAL_X1Y1.CLK11
Clock network: clk_125m_gtp
--------------------------------------------------------------------------------
@@ -1737,18 +1897,36 @@ Clock to Setup on destination clock clk_20m_vcxo_i
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
-tdc1_125m_clk_n_i| 6.270| | | |
-tdc1_125m_clk_p_i| 6.270| | | |
+tdc1_125m_clk_n_i| 5.678| | | |
+tdc1_125m_clk_p_i| 5.678| | | |
-----------------+---------+---------+---------+---------+
+Clock to Setup on destination clock clk_125m_pllref_n_i
+-------------------+---------+---------+---------+---------+
+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
+Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
+-------------------+---------+---------+---------+---------+
+clk_125m_pllref_n_i| 6.624| | 3.406| 1.481|
+clk_125m_pllref_p_i| 6.624| | 3.406| 1.481|
+-------------------+---------+---------+---------+---------+
+
+Clock to Setup on destination clock clk_125m_pllref_p_i
+-------------------+---------+---------+---------+---------+
+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
+Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
+-------------------+---------+---------+---------+---------+
+clk_125m_pllref_n_i| 6.624| | 3.406| 1.481|
+clk_125m_pllref_p_i| 6.624| | 3.406| 1.481|
+-------------------+---------+---------+---------+---------+
+
Clock to Setup on destination clock tdc1_125m_clk_n_i
-----------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
-clk_20m_vcxo_i | 3.855| | | |
-tdc1_125m_clk_n_i| 7.731| | | |
-tdc1_125m_clk_p_i| 7.731| | | |
+clk_20m_vcxo_i | 7.299| | | |
+tdc1_125m_clk_n_i| 7.729| | | |
+tdc1_125m_clk_p_i| 7.729| | | |
-----------------+---------+---------+---------+---------+
Clock to Setup on destination clock tdc1_125m_clk_p_i
@@ -1756,9 +1934,9 @@ Clock to Setup on destination clock tdc1_125m_clk_p_i
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
-clk_20m_vcxo_i | 3.855| | | |
-tdc1_125m_clk_n_i| 7.731| | | |
-tdc1_125m_clk_p_i| 7.731| | | |
+clk_20m_vcxo_i | 7.299| | | |
+tdc1_125m_clk_n_i| 7.729| | | |
+tdc1_125m_clk_p_i| 7.729| | | |
-----------------+---------+---------+---------+---------+
Clock to Setup on destination clock tdc2_125m_clk_n_i
@@ -1766,8 +1944,8 @@ Clock to Setup on destination clock tdc2_125m_clk_n_i
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
-tdc2_125m_clk_n_i| 7.706| | | |
-tdc2_125m_clk_p_i| 7.706| | | |
+tdc2_125m_clk_n_i| 7.765| | | |
+tdc2_125m_clk_p_i| 7.765| | | |
-----------------+---------+---------+---------+---------+
Clock to Setup on destination clock tdc2_125m_clk_p_i
@@ -1775,8 +1953,8 @@ Clock to Setup on destination clock tdc2_125m_clk_p_i
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
-tdc2_125m_clk_n_i| 7.706| | | |
-tdc2_125m_clk_p_i| 7.706| | | |
+tdc2_125m_clk_n_i| 7.765| | | |
+tdc2_125m_clk_p_i| 7.765| | | |
-----------------+---------+---------+---------+---------+
@@ -1785,24 +1963,24 @@ Timing summary:
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
-Constraints cover 949490 paths, 0 nets, and 25468 connections
+Constraints cover 918018 paths, 0 nets, and 26724 connections
Design statistics:
- Minimum period: 7.731ns{1} (Maximum frequency: 129.349MHz)
- Maximum path delay from/to any node: 6.270ns
+ Minimum period: 7.765ns{1} (Maximum frequency: 128.783MHz)
+ Maximum path delay from/to any node: 7.299ns
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
-Analysis completed Tue Jun 03 19:28:20 2014
+Analysis completed Thu Jun 05 18:51:10 2014
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
-Peak Memory Usage: 353 MB
+Peak Memory Usage: 411 MB
diff --git a/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc.xise b/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc.xise
index 9faedd4..e2a69d5 100644
--- a/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc.xise
+++ b/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc.xise
@@ -1195,7 +1195,7 @@
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
- <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="non-default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
diff --git a/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc_map.mrp b/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc_map.mrp
index 1962b43..39c1891 100644
--- a/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc_map.mrp
+++ b/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc_map.mrp
@@ -11,46 +11,49 @@ Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
-Mapped Date : Tue Jun 03 19:21:28 2014
+Mapped Date : Thu Jun 05 18:39:40 2014
Design Summary
--------------
Number of errors: 0
-Number of warnings: 6
+Number of warnings: 10
Slice Logic Utilization:
- Number of Slice Registers: 6,934 out of 184,304 3%
- Number used as Flip Flops: 6,884
+ Number of Slice Registers: 11,618 out of 184,304 6%
+ Number used as Flip Flops: 11,567
Number used as Latches: 4
Number used as Latch-thrus: 0
- Number used as AND/OR logics: 46
- Number of Slice LUTs: 9,193 out of 92,152 9%
- Number used as logic: 8,925 out of 92,152 9%
- Number using O6 output only: 5,941
- Number using O5 output only: 336
- Number using O5 and O6: 2,648
+ Number used as AND/OR logics: 47
+ Number of Slice LUTs: 15,904 out of 92,152 17%
+ Number used as logic: 15,581 out of 92,152 16%
+ Number using O6 output only: 11,173
+ Number using O5 output only: 876
+ Number using O5 and O6: 3,532
Number used as ROM: 0
- Number used as Memory: 37 out of 21,680 1%
- Number used as Dual Port RAM: 0
+ Number used as Memory: 87 out of 21,680 1%
+ Number used as Dual Port RAM: 24
+ Number using O6 output only: 24
+ Number using O5 output only: 0
+ Number using O5 and O6: 0
Number used as Single Port RAM: 0
- Number used as Shift Register: 37
- Number using O6 output only: 11
+ Number used as Shift Register: 63
+ Number using O6 output only: 25
Number using O5 output only: 0
- Number using O5 and O6: 26
- Number used exclusively as route-thrus: 231
- Number with same-slice register load: 177
- Number with same-slice carry load: 54
+ Number using O5 and O6: 38
+ Number used exclusively as route-thrus: 236
+ Number with same-slice register load: 134
+ Number with same-slice carry load: 102
Number with other load: 0
Slice Logic Distribution:
- Number of occupied Slices: 3,373 out of 23,038 14%
- Nummber of MUXCYs used: 2,400 out of 46,076 5%
- Number of LUT Flip Flop pairs used: 10,552
- Number with an unused Flip Flop: 4,275 out of 10,552 40%
- Number with an unused LUT: 1,359 out of 10,552 12%
- Number of fully used LUT-FF pairs: 4,918 out of 10,552 46%
- Number of unique control sets: 245
+ Number of occupied Slices: 6,491 out of 23,038 28%
+ Nummber of MUXCYs used: 3,636 out of 46,076 7%
+ Number of LUT Flip Flop pairs used: 18,634
+ Number with an unused Flip Flop: 7,901 out of 18,634 42%
+ Number with an unused LUT: 2,730 out of 18,634 14%
+ Number of fully used LUT-FF pairs: 8,003 out of 18,634 42%
+ Number of unique control sets: 501
Number of slice register sites lost
- to control set restrictions: 393 out of 184,304 1%
+ to control set restrictions: 1,176 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
@@ -59,50 +62,52 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
- Number of bonded IOBs: 261 out of 540 48%
- Number of LOCed IOBs: 252 out of 261 96%
- IOB Flip Flops: 201
+ Number of bonded IOBs: 269 out of 540 49%
+ Number of LOCed IOBs: 267 out of 269 99%
+ IOB Flip Flops: 203
Number of bonded IPADs: 4 out of 32 12%
+ Number of LOCed IPADs: 4 out of 4 100%
Number of bonded OPADs: 2 out of 16 12%
+ Number of LOCed OPADs: 2 out of 2 100%
Specific Feature Utilization:
- Number of RAMB16BWERs: 14 out of 268 5%
- Number of RAMB8BWERs: 7 out of 536 1%
- Number of BUFIO2/BUFIO2_2CLKs: 2 out of 32 6%
- Number used as BUFIO2s: 2
+ Number of RAMB16BWERs: 65 out of 268 24%
+ Number of RAMB8BWERs: 13 out of 536 2%
+ Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
+ Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
- Number of BUFG/BUFGMUXs: 5 out of 16 31%
- Number used as BUFGs: 5
+ Number of BUFG/BUFGMUXs: 6 out of 16 37%
+ Number used as BUFGs: 6
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
- Number of ILOGIC2/ISERDES2s: 138 out of 586 23%
- Number used as ILOGIC2s: 138
+ Number of ILOGIC2/ISERDES2s: 139 out of 586 23%
+ Number used as ILOGIC2s: 139
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 586 0%
- Number of OLOGIC2/OSERDES2s: 63 out of 586 10%
- Number used as OLOGIC2s: 63
+ Number of OLOGIC2/OSERDES2s: 64 out of 586 10%
+ Number used as OLOGIC2s: 64
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
- Number of DSP48A1s: 0 out of 180 0%
+ Number of DSP48A1s: 3 out of 180 1%
Number of GTPA1_DUALs: 1 out of 4 25%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
- Number of PLL_ADVs: 1 out of 6 16%
+ Number of PLL_ADVs: 2 out of 6 33%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
-Average Fanout of Non-Clock Nets: 3.99
+Average Fanout of Non-Clock Nets: 3.80
-Peak Memory Usage: 530 MB
-Total REAL time to MAP completion: 3 mins 32 secs
-Total CPU time to MAP completion: 3 mins 29 secs
+Peak Memory Usage: 606 MB
+Total REAL time to MAP completion: 5 mins 57 secs
+Total CPU time to MAP completion: 5 mins 53 secs
Table of Contents
-----------------
@@ -128,12 +133,6 @@ Section 2 - Warnings
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
-WARNING:MapLib:701 - Signal sfp_mod_def1_b connected to top level port
- sfp_mod_def1_b has been removed.
-WARNING:MapLib:701 - Signal sfp_mod_def2_b connected to top level port
- sfp_mod_def2_b has been removed.
-WARNING:MapLib:701 - Signal carrier_onewire_b connected to top level port
- carrier_onewire_b has been removed.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc2/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_291_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
@@ -142,6 +141,39 @@ WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc1/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_291_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
+WARNING:PhysDesignRules:367 - The signal
+ <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
+ CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
+ not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+ <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
+ CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
+ not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+ <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
+ CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
+ not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+ <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
+ CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
+ not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+ <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
+ CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
+ not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+ <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
+ CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
+ not drive any load pins in the design.
+WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
+ U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
+ .U_packet_filter/U_microcode_ram/gen_dual_clk.U_RAM_DC/Mram_ram) port(s) with
+ READ_FIRST mode has certain restrictions. Make sure that there is no address
+ collision. A read/write on one port and a write operation from the other port
+ at the same address is not allowed. RAMB16BWER, when both ports are 18 bits
+ wide or smaller, A13-6 including A4 cannot be same. When any one port is 36
+ bits wide, A13-7 including A5 cannot be the same. Violating this restriction
+ may result in the incorrect operation of the BRAM.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
@@ -150,19 +182,14 @@ WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
Section 3 - Informational
-------------------------
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
-INFO:LIT:243 - Logical network
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3
- has no load.
-INFO:LIT:395 - The above info message is repeated 284 more times for the
+INFO:LIT:243 - Logical network VME_BBSY_n_i has no load.
+INFO:LIT:395 - The above info message is repeated 273 more times for the
following (max. 5 shown):
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_p
- d_ddmtd.DMTD_FB/clk_i_d3,
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_p
- d_ddmtd.DMTD_FB/clk_i_d3,
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_p
- d_ddmtd.DMTD_FB/clk_i_d3,
- sfp_mod_def0_b,
- sfp_tx_fault_i
+ tdc1_in_fpga_1_i,
+ tdc1_in_fpga_2_i,
+ tdc1_in_fpga_3_i,
+ tdc1_in_fpga_4_i,
+ tdc1_in_fpga_5_i
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
@@ -176,16 +203,16 @@ INFO:Timing:3386 - Intersecting Constraints found and resolved. For more inform
Command Line Tools User Guide for information on generating a TSI report.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
-INFO:Place:834 - Only a subset of IOs are locked. Out of 261 IOs, 252 are locked
- and 9 are not locked. If you would like to print the names of these IOs,
+INFO:Place:834 - Only a subset of IOs are locked. Out of 269 IOs, 267 are locked
+ and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
- 132 block(s) removed
- 70 block(s) optimized away
- 551 signal(s) removed
+ 2 block(s) removed
+ 4 block(s) optimized away
+ 256 signal(s) removed
Section 5 - Removed Logic
-------------------------
@@ -200,351 +227,6 @@ To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
-The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3"
-is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3"
-(FF) removed.
- The signal "clk_dmtd" is loadless and has been removed.
- Loadless block "cmp_clk_dmtd_buf" (CKBUF) removed.
- The signal "pllout_clk_dmtd" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d2"
-is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d2"
-(FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d1"
-is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d1"
-(FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d0"
-is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d0"
-(FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" is
-loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in"
-(FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in_INV
-_200_o" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in_INV
-_200_o1_INV_0" (BUF) removed.
-The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d3" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d3" (FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d2" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d2" (FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d1" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d1" (FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d0" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d0" (FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_
-ddmtd.DMTD_FB/clk_in" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_
-ddmtd.DMTD_FB/clk_in" (FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_
-ddmtd.DMTD_FB/clk_in_INV_200_o" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_
-ddmtd.DMTD_FB/clk_in_INV_200_o1_INV_0" (BUF) removed.
-The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d3" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d3" (FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d2" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d2" (FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d1" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d1" (FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d0" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d0" (FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_
-ddmtd.DMTD_FB/clk_in" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_
-ddmtd.DMTD_FB/clk_in" (FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_
-ddmtd.DMTD_FB/clk_in_INV_200_o" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_
-ddmtd.DMTD_FB/clk_in_INV_200_o1_INV_0" (BUF) removed.
-The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d3" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d3" (FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d2" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d2" (FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d1" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d1" (FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d0" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_
-ddmtd.DMTD_FB/clk_i_d0" (FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_
-ddmtd.DMTD_FB/clk_in" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_
-ddmtd.DMTD_FB/clk_in" (FF) removed.
- The signal
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_
-ddmtd.DMTD_FB/clk_in_INV_200_o" is loadless and has been removed.
- Loadless block
-"U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_
-ddmtd.DMTD_FB/clk_in_INV_200_o1_INV_0" (BUF) removed.
-Loadless block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/D3" (DSP48A1) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<16>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<15>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<14>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<13>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<12>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<11>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<10>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<9>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<8>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<7>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<6>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<5>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<4>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<3>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<2>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<1>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<0>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<47>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<46>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<45>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<44>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<43>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<42>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<41>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<40>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<39>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<38>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<37>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<36>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<35>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<34>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<33>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<32>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<31>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<30>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<29>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<28>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<27>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<26>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<25>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<24>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<23>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<22>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<21>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<20>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<19>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<18>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<17>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<16>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<15>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<14>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<13>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<12>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<11>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<10>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<9>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<8>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<7>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<6>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<5>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<4>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<3>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<2>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<1>" is loadless and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/au_bl_sum<0>" is loadless and has been removed.
Loadless block
"cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd25" (ROM)
removed.
@@ -1064,1014 +746,8 @@ is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(0)"
is sourceless and has been removed.
-The trimmed logic reported below is either:
- 1. part of a cycle
- 2. part of disabled logic
- 3. a side-effect of other trimmed logic
-
-The signal "sfp_mod_def1_b" is unused and has been removed.
- Unused block "sfp_mod_def1_b_OBUFT" (TRI) removed.
-The signal "sfp_mod_def2_b" is unused and has been removed.
- Unused block "sfp_mod_def2_b_OBUFT" (TRI) removed.
-The signal "carrier_onewire_b" is unused and has been removed.
- Unused block "carrier_onewire_b_OBUFT" (TRI) removed.
-The signal "pllout_clk_fb_dmtd" is unused and has been removed.
-The signal "U_GTP/ch1_gtp_locked" is unused and has been removed.
- Unused block "U_GTP/ch1_gtp_locked1" (ROM) removed.
- The signal "U_GTP/ch1_gtp_pll_lockdet" is unused and has been removed.
- The signal "U_GTP/ch1_gtp_reset_done" is unused and has been removed.
-The signal "U_GTP/ch1_rx_comma_det" is unused and has been removed.
-The signal "U_GTP/ch1_rx_byte_is_aligned" is unused and has been removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<22>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<22>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<21>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<21>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<20>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<20>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<19>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<19>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<18>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<18>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<17>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<17>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<16>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<16>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<15>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<15>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<14>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<14>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<13>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<13>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<12>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<12>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<11>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<11>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<10>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<10>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<9>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<9>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<8>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<8>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<7>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<7>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<6>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<6>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<5>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<5>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<4>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<4>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<3>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<3>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<2>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<2>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<1>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<1>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<0>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<0>" (MUX) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_lu
-t<0>" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_lu
-t<0>_INV_0" (BUF) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<1>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<1>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<2>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<2>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<3>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<3>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<4>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<4>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<5>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<5>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<6>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<6>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<7>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<7>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<8>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<8>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<9>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<9>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<10>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<10>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<11>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<11>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<12>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<12>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<13>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<13>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<14>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<14>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<15>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<15>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<16>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<16>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<17>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<17>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<18>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<18>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<19>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<19>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<20>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<20>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<21>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<21>_rt" (ROM) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<22>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_cy
-<22>_rt" (ROM) removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/state_FSM_FFd1-In" is unused
-and has been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/state_FSM_FFd2-In" is unused
-and has been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/state_FSM_FFd3-In" is unused
-and has been removed.
- Unused block "U_GTP/gen_with_channel1.U_bitslide_ch1/state_FSM_FFd3-In1" (ROM)
-removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0153_inv" is unused and has
-been removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<0>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<0>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<1>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<1>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<2>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<2>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<3>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<3>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<4>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<4>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<5>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<5>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<6>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<6>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<7>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<7>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<8>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<8>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<9>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<9>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<10>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<10>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<11>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<11>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<12>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<12>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<13>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<13>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<14>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<14>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<15>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<15>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<16>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<16>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<17>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<17>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<18>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<18>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<19>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<19>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<20>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<20>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<21>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<21>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<22>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<22>" (XOR) removed.
-The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_add_14_OUT<23>" is
-unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<23>" (XOR) removed.
- The signal
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<23>_rt" is unused and has been removed.
- Unused block
-"U_GTP/gen_with_channel1.U_bitslide_ch1/Madd_counter[23]_GND_380_o_add_14_OUT_xo
-r<23>_rt" (ROM) removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<24>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<23>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<22>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<21>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<20>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<19>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<18>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<17>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<16>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<15>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<14>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<13>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<12>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<11>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<10>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<9>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<8>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<7>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<6>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<5>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<4>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<3>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<2>" is unused and has
-been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/_n0141<1>" is unused and has
-been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<17>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<18>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<19>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<20>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<21>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<22>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<23>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<24>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<25>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<26>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<27>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<28>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<29>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<30>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/d_r
-esult_0<31>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_f<21>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mmux_inst141" (ROM) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/way_match" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_cy<6>" (MUX) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_cy<5>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_cy<5>" (MUX) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_cy<4>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_cy<4>" (MUX) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_cy<3>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_cy<3>" (MUX) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_cy<2>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_cy<2>" (MUX) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_cy<1>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_cy<1>" (MUX) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_cy<0>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_cy<0>" (MUX) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_lut<0>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_lut<0>1" (ROM) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<0>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<1>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<2>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_lut<1>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_lut<1>1" (ROM) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<3>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<4>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<5>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_lut<2>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_lut<2>1" (ROM) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<6>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<7>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<8>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_lut<3>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_lut<3>1" (ROM) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<9>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<10>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<11>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_lut<4>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_lut<4>1" (ROM) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<12>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<13>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<14>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_lut<5>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_lut<5>1" (ROM) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<15>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<16>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<17>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_lut<6>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mcompar_way_match_lut<6>1" (ROM) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<18>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/n0078[19:0]<19>" is unused and has been removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/way_data<0><21>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_f<22>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mmux_inst151" (ROM) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/way_data<0><22>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_f<23>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mmux_inst161" (ROM) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/way_data<0><23>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_f<24>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mmux_inst171" (ROM) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/way_data<0><24>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_f<25>" is unused and has been removed.
- Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/Mmux_inst181" (ROM) removed.
- The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/way_data<0><25>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/al_bl<17>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/al_bl<18>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/al_bl<19>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/al_bl<20>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/al_bl<21>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/al_bl<22>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/al_bl<23>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/al_bl<24>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/al_bl<25>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/al_bl<26>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/al_bl<27>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/al_bl<28>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/al_bl<29>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/al_bl<30>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/al_bl<31>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/al_bl<32>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/al_bl<33>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<0>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<1>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<2>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<3>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<4>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<5>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<6>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<7>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<8>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<9>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<10>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<11>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<12>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<13>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<14>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<15>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<16>" is unused and has been removed.
-The signal
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/bl_forward<17>" is unused and has been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/gtp_rx_cdr_rst_o_rstpot" is
-unused and has been removed.
-The signal "U_GTP/gen_with_channel1.U_bitslide_ch1/gtp_rx_slide_o_rstpot" is
-unused and has been removed.
-Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/memories[0].way_0_data_ram/Mram_mem2" (RAMB16BWER) removed.
-Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/ins
-truction_unit/icache/memories[0].way_0_tag_ram/Mram_mem" (RAMB8BWER) removed.
-Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/D1" (DSP48A1) removed.
-Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/mul
-tiplier/D2" (DSP48A1) removed.
-Unused block
-"U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg
-_0/Mram_ram" (RAMB8BWER) removed.
-Unused block "carrier_onewire_b" (PAD) removed.
-Unused block "cmp_dmtd_clk_pll/PLL_ADV" (PLL_ADV) removed.
-Unused block "sfp_mod_def1_b" (PAD) removed.
-Unused block "sfp_mod_def2_b" (PAD) removed.
-
Optimized Block(s):
TYPE BLOCK
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n0141101
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n014111
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n0141111
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n0141121
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n0141131
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n0141141
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n0141151
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n0141161
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n0141171
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n0141181
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n0141191
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n0141201
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n014121
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n0141211
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n0141221
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n0141231
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n0141241
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n014131
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n014141
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n014151
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n014161
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n014171
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n014181
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/Mmux__n014191
- optimized to 0
-LUT5 U_GTP/gen_with_channel1.U_bitslide_ch1/_n0153_inv1
- optimized to 1
-LUT6
- U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_equal_16_o<23>11
- optimized to 1
-LUT6
- U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_equal_16_o<23>12
- optimized to 1
-LUT6
- U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_equal_16_o<23>2
- optimized to 0
-LUT6
- U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_equal_16_o<23>3
- optimized to 1
-LUT4
- U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_equal_16_o<23>4
- optimized to 0
-LUT5
- U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_equal_9_o<23>1
- optimized to 1
-LUT6
- U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_equal_9_o<23>3
- optimized to 0
-LUT5
- U_GTP/gen_with_channel1.U_bitslide_ch1/counter[23]_GND_380_o_equal_9_o<23>3_SW
-0
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_0
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_1
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_10
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_11
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_12
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_13
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_14
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_15
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_16
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_17
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_18
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_19
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_2
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_20
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_21
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_22
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_23
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_3
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_4
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_5
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_6
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_7
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_8
- optimized to 0
-FDCE U_GTP/gen_with_channel1.U_bitslide_ch1/counter_9
- optimized to 0
-FDC U_GTP/gen_with_channel1.U_bitslide_ch1/gtp_rx_cdr_rst_o
- optimized to 0
-LUT6 U_GTP/gen_with_channel1.U_bitslide_ch1/gtp_rx_cdr_rst_o_rstpot
- optimized to 0
-FDC U_GTP/gen_with_channel1.U_bitslide_ch1/gtp_rx_slide_o
- optimized to 0
-LUT4 U_GTP/gen_with_channel1.U_bitslide_ch1/gtp_rx_slide_o_rstpot
- optimized to 0
-FDC U_GTP/gen_with_channel1.U_bitslide_ch1/state_FSM_FFd1
- optimized to 0
-LUT6 U_GTP/gen_with_channel1.U_bitslide_ch1/state_FSM_FFd1-In1
- optimized to 0
-FDC U_GTP/gen_with_channel1.U_bitslide_ch1/state_FSM_FFd2
- optimized to 0
-LUT6 U_GTP/gen_with_channel1.U_bitslide_ch1/state_FSM_FFd2-In1
- optimized to 0
-FDC U_GTP/gen_with_channel1.U_bitslide_ch1/state_FSM_FFd3
- optimized to 0
GND XST_GND
VCC XST_VCC
GND cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/XST_GND
@@ -2219,6 +895,7 @@ Section 6 - IOB Properties
| VME_RETRY_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OFF | | |
| VME_RST_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_WRITE_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
+| carrier_onewire_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| clk_125m_gtp_n_i | IPAD | INPUT | | | | | | | |
| clk_125m_gtp_p_i | IPAD | INPUT | | | | | | | |
| clk_125m_pllref_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
@@ -2243,8 +920,14 @@ Section 6 - IOB Properties
| pll25dac_sclk_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll25dac_sync_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| por_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
+| sfp_los_i | IOB | INPUT | LVCMOS33 | | | | | | |
+| sfp_mod_def0_b | IOB | INPUT | LVCMOS33 | | | | | | |
+| sfp_mod_def1_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
+| sfp_mod_def2_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| sfp_rxn_i | IPAD | INPUT | | | | | | | |
| sfp_rxp_i | IPAD | INPUT | | | | | | | |
+| sfp_tx_disable_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
+| sfp_tx_fault_i | IOB | INPUT | LVCMOS33 | | | | | | |
| sfp_txn_o | OPAD | OUTPUT | | | | | | | |
| sfp_txp_o | OPAD | OUTPUT | | | | | | | |
| tdc1_125m_clk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
@@ -2305,8 +988,8 @@ Section 6 - IOB Properties
| tdc1_pll_status_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc1_prsntm2c_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| tdc1_rd_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| tdc1_scl_b | IOB | INPUT | LVCMOS33 | | | | | | |
-| tdc1_sda_b | IOB | INPUT | LVCMOS33 | | | | | | |
+| tdc1_scl_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
+| tdc1_sda_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| tdc1_start_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_start_from_fpga_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_stop_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
@@ -2374,8 +1057,8 @@ Section 6 - IOB Properties
| tdc2_pll_status_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc2_prsntm2c_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| tdc2_rd_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| tdc2_scl_b | IOB | INPUT | LVCMOS33 | | | | | | |
-| tdc2_sda_b | IOB | INPUT | LVCMOS33 | | | | | | |
+| tdc2_scl_b | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
+| tdc2_sda_b | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| tdc2_start_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_start_from_fpga_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_stop_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
@@ -2385,7 +1068,8 @@ Section 6 - IOB Properties
| tdc2_term_en_4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_term_en_5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_wr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| uart_txd_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
+| uart_rxd_i | IOB | INPUT | LVCMOS33 | | | | IFF | | |
+| uart_txd_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OFF | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
diff --git a/hdl/wrabbit_tdc/hdl/top/svec/svec_tdc.ucf b/hdl/wrabbit_tdc/hdl/top/svec/svec_tdc.ucf
index 4ac0c9a..76a6deb 100644
--- a/hdl/wrabbit_tdc/hdl/top/svec/svec_tdc.ucf
+++ b/hdl/wrabbit_tdc/hdl/top/svec/svec_tdc.ucf
@@ -546,6 +546,22 @@ NET "tdc2_onewire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# SFP slot
#----------------------------------------
+NET "sfp_txp_o" LOC = B23;
+NET "sfp_txn_o" LOC = A23;
+NET "sfp_rxp_i" LOC = D22;
+NET "sfp_rxn_i" LOC = C22;
+
+NET "clk_125m_gtp_p_i" LOC = B19;
+NET "clk_125m_gtp_n_i" LOC = A19;
+
+NET "sfp_los_i" LOC = W25;
+NET "sfp_mod_def0_b" LOC = Y26;
+NET "sfp_mod_def1_b" LOC = Y27;
+NET "sfp_mod_def2_b" LOC = AA24;
+#NET "sfp_rate_select_o" LOC = W24;
+NET "sfp_tx_disable_o" LOC = AA25;
+NET "sfp_tx_fault_i" LOC = AA27;
+
NET "sfp_los_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def0_b" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS33";
@@ -554,6 +570,13 @@ NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
+NET "pll20dac_din_o" LOC = U28;
+NET "pll20dac_sclk_o" LOC = AA28;
+NET "pll20dac_sync_n_o" LOC = N28;
+NET "pll25dac_din_o" LOC = P25;
+NET "pll25dac_sclk_o" LOC = N27;
+NET "pll25dac_sync_n_o" LOC = P26;
+
NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
@@ -564,6 +587,8 @@ NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# UART
#----------------------------------------
+NET "uart_txd_o" LOC = U27;
+NET "uart_rxd_i" LOC = U25;
NET "uart_txd_o" IOSTANDARD = "LVCMOS33";
NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
diff --git a/hdl/wrabbit_tdc/hdl/top/svec/svec_top_fmc_tdc.vhd b/hdl/wrabbit_tdc/hdl/top/svec/svec_top_fmc_tdc.vhd
index 59efad4..04345e7 100644
--- a/hdl/wrabbit_tdc/hdl/top/svec/svec_top_fmc_tdc.vhd
+++ b/hdl/wrabbit_tdc/hdl/top/svec/svec_top_fmc_tdc.vhd
@@ -336,7 +336,7 @@ architecture rtl of svec_top_fmc_tdc is
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
constant c_FMC_TDC0_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
constant c_FMC_TDC1_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
- constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00000000");
+ constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(7 downto 0) :=
(0 => f_sdb_embed_device (c_ONEWIRE_SDB_DEVICE, x"00010000"),
@@ -877,6 +877,8 @@ begin
wrc_owr_in(0) <= carrier_onewire_b;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- The SFP is permanently enabled.
+ sfp_tx_disable_o <= '0';
---------------------------------------------------------------------------------------------------
-- CSR WISHBONE CROSSBAR --
--
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