diff --git a/hdl/rtl/clks_rsts_manager.vhd b/hdl/rtl/clks_rsts_manager.vhd
index bcfe406b0c689bec2de20cf1eb399de60b9a1107..e1fcf667a3295a1c69f33f329d3641745998a97a 100644
--- a/hdl/rtl/clks_rsts_manager.vhd
+++ b/hdl/rtl/clks_rsts_manager.vhd
@@ -231,8 +231,8 @@ architecture rtl of clks_rsts_manager is
signal tdc_clk_buf : std_logic;
signal sclk, tdc_clk, acam_refclk : std_logic;
-- Resets
- signal internal_rst, interf_rst, rst, vme_rst : std_logic;
- signal rst_cnt, vme_rst_cnt : unsigned(7 downto 0) := "00000000";
+ signal rst : std_logic;
+ signal rst_cnt : unsigned(7 downto 0) := "00000000";
--=================================================================================================
diff --git a/hdl/rtl/data_formatting.vhd b/hdl/rtl/data_formatting.vhd
index 8c7bf1a4b7a83654ce39461365fbcc308987bf22..edae546185b6dc512728a6a1239c197c2cc7434e 100644
--- a/hdl/rtl/data_formatting.vhd
+++ b/hdl/rtl/data_formatting.vhd
@@ -136,7 +136,7 @@ architecture rtl of data_formatting is
signal acam_start_nb : std_logic_vector(7 downto 0);
-- timestamp manipulations
signal un_acam_start_nb, un_clk_i_cycles_offset : unsigned(31 downto 0);
- signal un_roll_over, un_nb_of_retrig, un_retrig_nb_offset : unsigned(31 downto 0);
+ signal un_nb_of_retrig, un_retrig_nb_offset : unsigned(31 downto 0);
signal un_nb_of_cycles, un_retrig_from_roll_over : unsigned(31 downto 0);
signal acam_start_nb_32 : std_logic_vector(31 downto 0);
-- final timestamp fields
@@ -148,8 +148,6 @@ architecture rtl of data_formatting is
signal dacapo_counter : unsigned(19 downto 0);
signal wr_index : unsigned(7 downto 0);
-- coarse time calculations
- signal tstamp_on_first_retrig_case1 : std_logic;
- signal tstamp_on_first_retrig_case2 : std_logic;
signal un_previous_clk_i_cycles_offset : unsigned(31 downto 0);
signal un_previous_retrig_nb_offset : unsigned(31 downto 0);
signal un_previous_roll_over_nb : unsigned(31 downto 0);
diff --git a/hdl/rtl/fmc_tdc_mezzanine.vhd b/hdl/rtl/fmc_tdc_mezzanine.vhd
index 962ee467f87218888988880202b96942a1457625..f105f09a7621224e238830d8073a45b06becaf81 100644
--- a/hdl/rtl/fmc_tdc_mezzanine.vhd
+++ b/hdl/rtl/fmc_tdc_mezzanine.vhd
@@ -183,11 +183,12 @@ architecture rtl of fmc_tdc_mezzanine is
---------------------------------------------------------------------------------------------------
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
- constant c_NUM_WB_MASTERS : integer := 4;
+ constant c_NUM_WB_MASTERS : integer := 5;
constant c_WB_SLAVE_TDC_CORE_CONFIG : integer := 0; -- TDC core configuration registers
constant c_WB_SLAVE_TDC_ONEWIRE : integer := 1; -- TDC mezzanine board UnidueID&Thermometer 1-wire
constant c_WB_SLAVE_TDC_EIC : integer := 2; -- TDC interrupts
constant c_WB_SLAVE_TDC_SYS_I2C : integer := 3; -- TDC mezzanine board system EEPROM I2C
+ constant c_WB_SLAVE_TSTAMP_MEM : integer := 4; -- Access to TDC core timestamps memory
-- Slave port on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
@@ -196,11 +197,12 @@ architecture rtl of fmc_tdc_mezzanine is
-- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- WISHBONE crossbar layout
- constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(3 downto 0) :=
- (0 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00001000"),
- 1 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00001100"),
- 2 => f_sdb_embed_device(c_TDC_EIC_DEVICE, x"00001200"),
- 3 => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00001300"));
+ constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(4 downto 0) :=
+ (0 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00010000"),
+ 1 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00011000"),
+ 2 => f_sdb_embed_device(c_TDC_EIC_DEVICE, x"00012000"),
+ 3 => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00013000"),
+ 4 => f_sdb_embed_device(c_TDC_MEM_SDB_DEVICE, x"00014000"));
---------------------------------------------------------------------------------------------------
@@ -217,7 +219,6 @@ architecture rtl of fmc_tdc_mezzanine is
-- WISHBONE addresses
signal tdc_core_wb_adr : std_logic_vector(31 downto 0);
signal tdc_mem_wb_adr : std_logic_vector(31 downto 0);
- signal dummy_core_wb_adr : std_logic_vector(31 downto 0);
-- 1-wire
signal mezz_owr_en, mezz_owr_i : std_logic_vector(0 downto 0);
-- I2C
@@ -339,19 +340,21 @@ begin
tdc_config_wb_dat_o => cnx_master_in(c_WB_SLAVE_TDC_CORE_CONFIG).dat,
tdc_config_wb_ack_o => cnx_master_in(c_WB_SLAVE_TDC_CORE_CONFIG).ack,
-- WISHBONE for timestamps transfer
- tdc_mem_wb_adr_i => wb_tdc_mem_adr_i,
- tdc_mem_wb_dat_i => wb_tdc_mem_dat_i,
- tdc_mem_wb_stb_i => wb_tdc_mem_stb_i,
- tdc_mem_wb_we_i => wb_tdc_mem_we_i,
- tdc_mem_wb_cyc_i => wb_tdc_mem_cyc_i,
- tdc_mem_wb_ack_o => wb_tdc_mem_ack_o,
- tdc_mem_wb_dat_o => wb_tdc_mem_dat_o,
- tdc_mem_wb_stall_o => wb_tdc_mem_stall_o);
+ tdc_mem_wb_adr_i => tdc_mem_wb_adr,--wb_tdc_mem_adr_i,
+ tdc_mem_wb_dat_i => cnx_master_out(c_WB_SLAVE_TSTAMP_MEM).dat,--wb_tdc_mem_dat_i,
+ tdc_mem_wb_stb_i => cnx_master_out(c_WB_SLAVE_TSTAMP_MEM).stb,--wb_tdc_mem_stb_i,
+ tdc_mem_wb_we_i => cnx_master_out(c_WB_SLAVE_TSTAMP_MEM).we,--wb_tdc_mem_we_i,
+ tdc_mem_wb_cyc_i => cnx_master_out(c_WB_SLAVE_TSTAMP_MEM).cyc,--wb_tdc_mem_cyc_i,
+ tdc_mem_wb_ack_o => cnx_master_in(c_WB_SLAVE_TSTAMP_MEM).ack,--wb_tdc_mem_ack_o,
+ tdc_mem_wb_dat_o => cnx_master_in(c_WB_SLAVE_TSTAMP_MEM).dat,--wb_tdc_mem_dat_o,
+ tdc_mem_wb_stall_o => cnx_master_in(c_WB_SLAVE_TSTAMP_MEM).stall);--wb_tdc_mem_stall_o);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Convert byte address into word address
tdc_core_wb_adr <= "00" & cnx_master_out(c_WB_SLAVE_TDC_CORE_CONFIG).adr(31 downto 2);
+ tdc_mem_wb_adr <= "00" & cnx_master_out(c_WB_SLAVE_TSTAMP_MEM).adr(31 downto 2);
+
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_TDC_CORE_CONFIG).err <= '0';
@@ -359,6 +362,10 @@ begin
cnx_master_in(c_WB_SLAVE_TDC_CORE_CONFIG).stall <= '0';
cnx_master_in(c_WB_SLAVE_TDC_CORE_CONFIG).int <= '0';
+ wb_tdc_mem_ack_o <= '0';
+ wb_tdc_mem_dat_o <= (others => '0');
+ wb_tdc_mem_stall_o <