diff --git a/hdl/wr_spec_tdc/hdl/rtl/data_engine.vhd b/hdl/wr_spec_tdc/hdl/rtl/data_engine.vhd
index f92bd5bd20fb740e35779518be6eae55dbf19dbe..d9f5d14db8b6a9c50910febbfb01c9df3bc3056c 100644
--- a/hdl/wr_spec_tdc/hdl/rtl/data_engine.vhd
+++ b/hdl/wr_spec_tdc/hdl/rtl/data_engine.vhd
@@ -43,7 +43,7 @@
-- Last changes |
-- 06/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
--- 14/2014 v1 EG added state RD_START01 |
+-- 14/2014 v1 EG added state RD_START01 |
-- |
---------------------------------------------------------------------------------------------------
@@ -384,7 +384,10 @@ begin
acam_we <= '0';
-----------------------------------------------
- if acam_ack_i ='1' then
+ if deactivate_acq_p_i = '1' then
+ nxt_engine_st <= INACTIVE;
+
+ elsif acam_ack_i ='1' then
if acam_ef2_i = '0' then
nxt_engine_st <= GET_STAMP2;
@@ -408,7 +411,10 @@ begin
acam_we <= '0';
-----------------------------------------------
- if acam_ack_i ='1' then -- idem.
+ if deactivate_acq_p_i = '1' then
+ nxt_engine_st <= INACTIVE;
+
+ elsif acam_ack_i ='1' then
if acam_ef1_i ='0' then
nxt_engine_st <= GET_STAMP1;
diff --git a/hdl/wr_spec_tdc/hdl/rtl/data_formatting.vhd b/hdl/wr_spec_tdc/hdl/rtl/data_formatting.vhd
index d7d6b6cdec4d95c6a70716f0dece6e14c4756ab0..139bcf11850614886732f37637be6c0dbcef75a8 100644
--- a/hdl/wr_spec_tdc/hdl/rtl/data_formatting.vhd
+++ b/hdl/wr_spec_tdc/hdl/rtl/data_formatting.vhd
@@ -90,7 +90,8 @@ entity data_formatting is
-- Signals from the reg_ctrl unit
dacapo_c_rst_p_i : in std_logic; -- instruction from GN4124/VME to clear dacapo flag
-
+ deactivate_chan_i : in std_logic_vector(4 downto 0); -- instruction from GN4124/VME to stop registering tstamps from a specific channel
+
-- Signals from the one_hz_gen unit
utc_i : in std_logic_vector(31 downto 0); -- local UTC time
@@ -153,7 +154,7 @@ architecture rtl of data_formatting is
signal tstamp_on_first_retrig_case2 : std_logic;
signal un_previous_clk_i_cycles_offset : unsigned(31 downto 0);
signal un_previous_retrig_nb_offset : unsigned(31 downto 0);
- signal un_previous_roll_over_nb, un_previous_roll_over_nb2, un_previous_roll_over_nb3 : unsigned(31 downto 0);
+ signal un_previous_roll_over_nb : unsigned(31 downto 0);
signal un_current_retrig_nb_offset, un_current_roll_over_nb : unsigned(31 downto 0);
signal un_current_retrig_from_roll_over : unsigned(31 downto 0);
signal un_acam_fine_time :unsigned(31 downto 0);
@@ -193,10 +194,45 @@ begin
tstamp_wr_cyc <= '0';
tstamp_wr_we <= '0';
- elsif acam_tstamp1_ok_p_i ='1' or acam_tstamp2_ok_p_i ='1' then
- tstamp_wr_stb <= '1';
- tstamp_wr_cyc <= '1';
- tstamp_wr_we <= '1';
+ elsif acam_tstamp1_ok_p_i = '1' then
+ if deactivate_chan_i = "00000" then
+ tstamp_wr_stb <= '1';
+ tstamp_wr_cyc <= '1';
+ tstamp_wr_we <= '1';
+ else
+ if deactivate_chan_i = "00001" and acam_tstamp1_i(27 downto 26) = "00" then
+ tstamp_wr_stb <= '0';
+ tstamp_wr_cyc <= '0';
+ tstamp_wr_we <= '0';
+ elsif deactivate_chan_i = "00010" and acam_tstamp1_i(27 downto 26) = "01" then
+ tstamp_wr_stb <= '0';
+ tstamp_wr_cyc <= '0';
+ tstamp_wr_we <= '0';
+ elsif deactivate_chan_i = "00100" and acam_tstamp1_i(27 downto 26) = "10" then
+ tstamp_wr_stb <= '0';
+ tstamp_wr_cyc <= '0';
+ tstamp_wr_we <= '0';
+ elsif deactivate_chan_i = "01000" and acam_tstamp1_i(27 downto 26) = "11" then
+ tstamp_wr_stb <= '0';
+ tstamp_wr_cyc <= '0';
+ tstamp_wr_we <= '0';
+ else
+ tstamp_wr_stb <= '1';
+ tstamp_wr_cyc <= '1';
+ tstamp_wr_we <= '1';
+ end if;
+ end if;
+
+ elsif acam_tstamp2_ok_p_i = '1' then
+ if deactivate_chan_i = "10000" then
+ tstamp_wr_stb <= '0';
+ tstamp_wr_cyc <= '0';
+ tstamp_wr_we <= '0';
+ else
+ tstamp_wr_stb <= '1';
+ tstamp_wr_cyc <= '1';
+ tstamp_wr_we <= '1';
+ end if;
elsif tstamp_wr_wb_ack_i = '1' then
tstamp_wr_stb <= '0';
@@ -321,8 +357,6 @@ begin
un_previous_retrig_nb_offset <= (others => '0');
un_previous_roll_over_nb <= (others => '0');
previous_utc <= (others => '0');
- un_previous_roll_over_nb2 <= unsigned(roll_over_nb_i);
- un_previous_roll_over_nb3 <= un_previous_roll_over_nb2;
elsif utc_p_i = '1' then
un_previous_clk_i_cycles_offset <= unsigned(clk_i_cycles_offset_i);
un_previous_retrig_nb_offset <= unsigned(retrig_nb_offset_i);
@@ -444,8 +478,8 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- metadata: information about the timestamp
metadata <= std_logic_vector(acam_start_nb(7 downto 0)) & -- std_logic_vector(un_previous_retrig_nb_offset(7 downto 0)) & -- for debugging (24 MSbits)
- std_logic_vector(un_retrig_from_roll_over(4 downto 0)) & --acam_fifo_ef & roll_over_incr_recent_i & "0" & -- for debugging (3 bits)
- std_logic_vector(un_retrig_nb_offset(7 downto 0)) & std_logic_vector(un_clk_i_cycles_offset(5 downto 0)) &
+ coarse_zero &--acam_fifo_ef & roll_over_incr_recent_i & "0" & -- for debugging (3 bits)
+ std_logic_vector(un_retrig_nb_offset(7 downto 0)) & std_logic_vector(roll_over_nb_i(9 downto 0)) &
acam_slope & roll_over_incr_recent_i & acam_channel; -- 5 LSbits-----------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
diff --git a/hdl/wr_spec_tdc/hdl/rtl/fmc_tdc_core.vhd b/hdl/wr_spec_tdc/hdl/rtl/fmc_tdc_core.vhd
index c74ff801ab34c45f1ad1aa0488a0d7967a1f833d..7e79f70351c0b01e04680f9049ed95400fc191d3 100644
--- a/hdl/wr_spec_tdc/hdl/rtl/fmc_tdc_core.vhd
+++ b/hdl/wr_spec_tdc/hdl/rtl/fmc_tdc_core.vhd
@@ -249,6 +249,7 @@ architecture rtl of fmc_tdc_core is
signal read_acam_config, read_acam_status, read_ififo1 : std_logic;
signal read_ififo2, read_start01, reset_acam, load_utc : std_logic;
signal clear_dacapo_counter, roll_over_incr_recent : std_logic;
+ signal deactivate_chan : std_logic_vector(4 downto 0);
signal pulse_delay, window_delay, clk_period : std_logic_vector(g_width-1 downto 0);
signal starting_utc, acam_inputs_en : std_logic_vector(g_width-1 downto 0);
signal acam_ififo1, acam_ififo2, acam_start01 : std_logic_vector(g_width-1 downto 0);
@@ -275,27 +276,27 @@ architecture rtl of fmc_tdc_core is
signal acam_tstamp_channel : std_logic_vector(2 downto 0);
-- Chipscope
- --component chipscope_ila
- -- port (
- -- CONTROL : inout std_logic_vector(35 downto 0);
- -- CLK : in std_logic;
- -- TRIG0 : in std_logic_vector(31 downto 0);
- -- TRIG1 : in std_logic_vector(31 downto 0);
- -- TRIG2 : in std_logic_vector(31 downto 0);
- -- TRIG3 : in std_logic_vector(31 downto 0));
- --end component;
-
- --component chipscope_icon
- -- port (
- -- CONTROL0 : inout std_logic_vector (35 downto 0));
- --end component;
-
- --signal CONTROL : std_logic_vector(35 downto 0);
- --signal CLK : std_logic;
- --signal TRIG0 : std_logic_vector(31 downto 0);
- --signal TRIG1 : std_logic_vector(31 downto 0);
- --signal TRIG2 : std_logic_vector(31 downto 0);
- --signal TRIG3 : std_logic_vector(31 downto 0);
+ component chipscope_ila
+ port (
+ CONTROL : inout std_logic_vector(35 downto 0);
+ CLK : in std_logic;
+ TRIG0 : in std_logic_vector(31 downto 0);
+ TRIG1 : in std_logic_vector(31 downto 0);
+ TRIG2 : in std_logic_vector(31 downto 0);
+ TRIG3 : in std_logic_vector(31 downto 0));
+ end component;
+
+ component chipscope_icon
+ port (
+ CONTROL0 : inout std_logic_vector (35 downto 0));
+ end component;
+
+ signal CONTROL : std_logic_vector(35 downto 0);
+ signal CLK : std_logic;
+ signal TRIG0 : std_logic_vector(31 downto 0);
+ signal TRIG1 : std_logic_vector(31 downto 0);
+ signal TRIG2 : std_logic_vector(31 downto 0);
+ signal TRIG3 : std_logic_vector(31 downto 0);
--=================================================================================================
-- architecture begin
@@ -330,6 +331,7 @@ begin
acam_rst_p_o => reset_acam,
load_utc_p_o => load_utc,
dacapo_c_rst_p_o => clear_dacapo_counter,
+ deactivate_chan_o => deactivate_chan,
acam_config_rdbk_i => acam_config_rdbk,
acam_ififo1_i => acam_ififo1,
acam_ififo2_i => acam_ififo2,
@@ -524,6 +526,7 @@ begin
acam_tstamp2_i => acam_tstamp2,
acam_tstamp2_ok_p_i => acam_tstamp2_ok_p,
dacapo_c_rst_p_i => clear_dacapo_counter,
+ deactivate_chan_i => deactivate_chan,
roll_over_incr_recent_i => roll_over_incr_recent,
clk_i_cycles_offset_i => clk_i_cycles_offset,
roll_over_nb_i => roll_over_nb,
@@ -614,35 +617,35 @@ begin
-- CHIPSCOPE --
---------------------------------------------------------------------------------------------------
--- chipscope_ila_1 : chipscope_ila
--- port map (
--- CONTROL => CONTROL,
--- CLK => clk_125m_i,
--- TRIG0 => TRIG0,
--- TRIG1 => TRIG1,
--- TRIG2 => TRIG2,
--- TRIG3 => TRIG3);
-
--- chipscope_icon_1 : chipscope_icon
--- port map (
--- CONTROL0 => CONTROL);
+ chipscope_ila_1 : chipscope_ila
+ port map (
+ CONTROL => CONTROL,
+ CLK => clk_125m_i,
+ TRIG0 => TRIG0,
+ TRIG1 => TRIG1,
+ TRIG2 => TRIG2,
+ TRIG3 => TRIG3);
+
+ chipscope_icon_1 : chipscope_icon
+ port map (
+ CONTROL0 => CONTROL);
--- TRIG0(0) <= utc_p;
--- TRIG0(1) <= ef1_i;
--- TRIG0(2) <= int_flag_i;
--- TRIG0(3) <= acam_intflag_f_edge_p;
--- TRIG0(16 downto 4) <= roll_over_nb(12 downto 0);
--- TRIG0(17) <= start_from_fpga;
--- TRIG0(25 downto 18) <= retrig_nb_offset(7 downto 0);
--- TRIG0(31 downto 26) <= clk_i_cycles_offset(5 downto 0);
-
--- TRIG1(30 downto 0) <= acam_tstamp1(30 downto 0);
--- TRIG1(31) <= acam_tstamp1_ok_p;
-
--- TRIG2(31 downto 0) <= utc(31 downto 0);
+ TRIG0(0) <= utc_p;
+ TRIG0(1) <= ef1_i;
+ TRIG0(2) <= int_flag_i;
+ TRIG0(3) <= acam_intflag_f_edge_p;
+ TRIG0(16 downto 4) <= roll_over_nb(12 downto 0);
+ TRIG0(17) <= start_from_fpga;
+ TRIG0(25 downto 18) <= retrig_nb_offset(7 downto 0);
+ TRIG0(31 downto 26) <= clk_i_cycles_offset(5 downto 0);
+
+ TRIG1(30 downto 0) <= acam_tstamp1(30 downto 0);
+ TRIG1(31) <= acam_tstamp1_ok_p;
+
+ TRIG2(31 downto 0) <= utc(31 downto 0);
--- TRIG3(0) <= tdc_in_fpga_1_i;
--- TRIG3(31 downto 1) <= current_retrig_nb(30 downto 0);
+ TRIG3(0) <= tdc_in_fpga_1_i;
+ TRIG3(31 downto 1) <= current_retrig_nb(30 downto 0);
end rtl;
----------------------------------------------------------------------------------------------------
diff --git a/hdl/wr_spec_tdc/hdl/rtl/fmc_tdc_mezzanine.vhd b/hdl/wr_spec_tdc/hdl/rtl/fmc_tdc_mezzanine.vhd
index c78efad7b35501b6a8e6e92499c8b67f1b6d92b5..5bc2938d29b923103a8ed0800d6b6b47c916ff2c 100644
--- a/hdl/wr_spec_tdc/hdl/rtl/fmc_tdc_mezzanine.vhd
+++ b/hdl/wr_spec_tdc/hdl/rtl/fmc_tdc_mezzanine.vhd
@@ -240,6 +240,9 @@ architecture rtl of fmc_tdc_mezzanine is
-- Wishbone buse(s) to crossbar slave port(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array (c_NUM_WB_SLAVES-1 downto 0);
+ -- Wishbone bus from additional registers
+ signal xreg_slave_out : t_wishbone_slave_out;
+ signal xreg_slave_in : t_wishbone_slave_in;
-- WISHBONE addresses
signal tdc_core_wb_adr : std_logic_vector(31 downto 0);
signal tdc_mem_wb_adr : std_logic_vector(31 downto 0);
@@ -275,6 +278,31 @@ begin
-- 0x13000 -> TDC mezzanine board EEPROM I2C
-- 0x14000 -> TDC core timestamps retreival
+ -- Additional register to help timing
+ cmp_xwb_reg : xwb_register_link
+ port map
+ (clk_sys_i => clk_ref_0_i,
+ rst_n_i => rst_ref_0_n,
+ slave_i => xreg_slave_in,
+ slave_o => xreg_slave_out,
+ master_i => cnx_slave_out(c_WB_MASTER),
+ master_o => cnx_slave_in(c_WB_MASTER));
+
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- Unused wishbone signals
+ wb_tdc_csr_dat_o <= xreg_slave_out.dat;
+ wb_tdc_csr_ack_o <= xreg_slave_out.ack;
+ wb_tdc_csr_stall_o <= xreg_slave_out.stall;
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- Connect crossbar slave port to entity port
+ xreg_slave_in.adr <= wb_tdc_csr_adr_i;
+ xreg_slave_in.dat <= wb_tdc_csr_dat_i;
+ xreg_slave_in.sel <= wb_tdc_csr_sel_i;
+ xreg_slave_in.stb <= wb_tdc_csr_stb_i;
+ xreg_slave_in.we <= wb_tdc_csr_we_i;
+ xreg_slave_in.cyc <= wb_tdc_csr_cyc_i;
+
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map
(g_num_masters => c_NUM_WB_SLAVES,
@@ -291,21 +319,7 @@ begin
master_i => cnx_master_in,
master_o => cnx_master_out);
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- -- Unused wishbone signals
- wb_tdc_csr_dat_o <= cnx_slave_out(c_WB_MASTER).dat;
- wb_tdc_csr_ack_o <= cnx_slave_out(c_WB_MASTER).ack;
- wb_tdc_csr_stall_o <= cnx_slave_out(c_WB_MASTER).stall;
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- -- Connect crossbar slave port to entity port
- cnx_slave_in(c_WB_MASTER).adr <= wb_tdc_csr_adr_i;
- cnx_slave_in(c_WB_MASTER).dat <= wb_tdc_csr_dat_i;
- cnx_slave_in(c_WB_MASTER).sel <= wb_tdc_csr_sel_i;
- cnx_slave_in(c_WB_MASTER).stb <= wb_tdc_csr_stb_i;
- cnx_slave_in(c_WB_MASTER).we <= wb_tdc_csr_we_i;
- cnx_slave_in(c_WB_MASTER).cyc <= wb_tdc_csr_cyc_i;
-
-
+
---------------------------------------------------------------------------------------------------
-- TDC CORE --
---------------------------------------------------------------------------------------------------
@@ -506,28 +520,32 @@ begin
---------------------------------------------------------------------------------------------------
-- TDC Mezzanine Board EEPROM I2C --
---------------------------------------------------------------------------------------------------
- cmp_I2C_master : xwb_i2c_master
- generic map
- (g_interface_mode => PIPELINED,
- g_address_granularity => BYTE)
- port map
- (clk_sys_i => clk_ref_0_i,
- rst_n_i => rst_ref_0_n,
- slave_i => cnx_master_out(c_WB_SLAVE_TDC_I2C),
- slave_o => cnx_master_in(c_WB_SLAVE_TDC_I2C),
- desc_o => open,
- scl_pad_i => i2c_scl_i,
- scl_pad_o => sys_scl_out,
- scl_padoen_o => sys_scl_oe_n,
- sda_pad_i => i2c_sda_i,
- sda_pad_o => sys_sda_out,
- sda_padoen_o => sys_sda_oe_n);
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- i2c_sda_oen_o <= sys_sda_oe_n;
- i2c_sda_o <= sys_sda_out;
- i2c_scl_oen_o <= sys_scl_oe_n;
- i2c_scl_o <= sys_scl_out;
+-- cmp_I2C_master : xwb_i2c_master
+-- generic map
+-- (g_interface_mode => PIPELINED,
+-- g_address_granularity => BYTE)
+-- port map
+-- (clk_sys_i => clk_ref_0_i,
+-- rst_n_i => rst_ref_0_n,
+-- slave_i => cnx_master_out(c_WB_SLAVE_TDC_I2C),
+-- slave_o => cnx_master_in(c_WB_SLAVE_TDC_I2C),
+-- desc_o => open,
+-- scl_pad_i => i2c_scl_i,
+-- scl_pad_o => sys_scl_out,
+-- scl_padoen_o => sys_scl_oe_n,
+-- sda_pad_i => i2c_sda_i,
+-- sda_pad_o => sys_sda_out,
+-- sda_padoen_o => sys_sda_oe_n);
+--
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+-- i2c_sda_oen_o <= sys_sda_oe_n;
+-- i2c_sda_o <= sys_sda_out;
+-- i2c_scl_oen_o <= sys_scl_oe_n;
+-- i2c_scl_o <= sys_scl_out;
+ i2c_sda_oen_o <= '0';
+ i2c_sda_o <= '0';
+ i2c_scl_oen_o <= '0';
+ i2c_scl_o <= '0';
end rtl;
diff --git a/hdl/wr_spec_tdc/hdl/rtl/reg_ctrl.vhd b/hdl/wr_spec_tdc/hdl/rtl/reg_ctrl.vhd
index 8984046cee022d0e365c7bb2712af241dc2c2a0c..380da5119f23e72915d6455442ccbd66950057b7 100644
--- a/hdl/wr_spec_tdc/hdl/rtl/reg_ctrl.vhd
+++ b/hdl/wr_spec_tdc/hdl/rtl/reg_ctrl.vhd
@@ -136,8 +136,9 @@ entity reg_ctrl is
-- Signal to the data_formatting unit
dacapo_c_rst_p_o : out std_logic; -- clears the dacapo counter
+ deactivate_chan_o : out std_logic_vector(4 downto 0); -- stops registering timestamps from a specific channel
- -- Signals to the clks_resets_manager ubit
+ -- Signals to the clks_resets_manager unit
send_dac_word_p_o : out std_logic; -- initiates the reconfiguration of the DAC
dac_word_o : out std_logic_vector(23 downto 0);
@@ -174,7 +175,7 @@ architecture rtl of reg_ctrl is
signal dac_word : std_logic_vector(23 downto 0);
signal pulse_extender_en : std_logic;
signal pulse_extender_c : std_logic_vector(2 downto 0);
- signal dat_out, wrabbit_ctrl_reg : std_logic_vector(g_span-1 downto 0);
+ signal dat_out, wrabbit_ctrl_reg, deactivate_chan : std_logic_vector(g_span-1 downto 0);
signal tdc_config_wb_ack_o_pipe0 : std_logic;
@@ -347,6 +348,10 @@ begin
if reg_adr = c_WRABBIT_CTRL_ADR then
wrabbit_ctrl_reg <= tdc_config_wb_dat_i;
end if;
+
+ if reg_adr = c_DEACT_CHAN_ADR then
+ deactivate_chan <= tdc_config_wb_dat_i;
+ end if;
end if;
end if;
@@ -360,6 +365,7 @@ begin
irq_time_threshold_o <= irq_time_threshold;
dac_word_o <= dac_word;
wrabbit_ctrl_reg_o <= wrabbit_ctrl_reg;
+ deactivate_chan_o <= deactivate_chan(4 downto 0);
---------------------------------------------------------------------------------------------------
-- Reception of TDC core Control Register --
@@ -486,7 +492,8 @@ begin
core_status_i when c_CORE_STATUS_ADR,
-- White Rabbit regs
wrabbit_status_reg_i when c_WRABBIT_STATUS_ADR,
- wrabbit_ctrl_reg when c_WRABBIT_CTRL_ADR,
+ wrabbit_ctrl_reg when c_WRABBIT_CTRL_ADR,
+ deactivate_chan when c_DEACT_CHAN_ADR,
-- others
x"C0FFEEEE" when others;
diff --git a/hdl/wr_spec_tdc/hdl/syn/spec/xilinx/spec_top_fmc_tdc/spec_top_fmc_tdc.bin b/hdl/wr_spec_tdc/hdl/syn/spec/xilinx/spec_top_fmc_tdc/spec_top_fmc_tdc.bin
index 4ab54ae867f337a4a1dedb278acc6e0ec54dcbc4..80f3efdf643b8417a6e0936df12e4e3e6ba2473e 100644
Binary files a/hdl/wr_spec_tdc/hdl/syn/spec/xilinx/spec_top_fmc_tdc/spec_top_fmc_tdc.bin and b/hdl/wr_spec_tdc/hdl/syn/spec/xilinx/spec_top_fmc_tdc/spec_top_fmc_tdc.bin differ
diff --git a/hdl/wr_spec_tdc/hdl/syn/spec/xilinx/spec_top_fmc_tdc/spec_top_fmc_tdc.xise b/hdl/wr_spec_tdc/hdl/syn/spec/xilinx/spec_top_fmc_tdc/spec_top_fmc_tdc.xise
index f26f9ff2a8f93879e44e3ddfb5202555b984cc27..f665c7c494189a4012ed1e590234d2e741785ee8 100644
--- a/hdl/wr_spec_tdc/hdl/syn/spec/xilinx/spec_top_fmc_tdc/spec_top_fmc_tdc.xise
+++ b/hdl/wr_spec_tdc/hdl/syn/spec/xilinx/spec_top_fmc_tdc/spec_top_fmc_tdc.xise
@@ -17,71 +17,71 @@
<files>
<file xil_pn:name="../../../../rtl/tdc_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="129"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="127"/>
</file>
<file xil_pn:name="../../../../rtl/acam_databus_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
<file xil_pn:name="../../../../rtl/acam_timecontrol_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="108"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file>
<file xil_pn:name="../../../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="154"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../../../../rtl/circular_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="107"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../../../../rtl/clks_rsts_manager.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="153"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="151"/>
</file>
<file xil_pn:name="../../../../rtl/data_engine.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="../../../../rtl/data_formatting.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
<file xil_pn:name="../../../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="86"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../../../../rtl/fmc_tdc_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="130"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="128"/>
</file>
<file xil_pn:name="../../../../rtl/fmc_tdc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="152"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="150"/>
</file>
<file xil_pn:name="../../../../rtl/free_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../../../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file>
<file xil_pn:name="../../../../rtl/irq_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../../../../rtl/leds_manager.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
<file xil_pn:name="../../../../rtl/reg_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../../../../rtl/start_retrig_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../../../../ip_cores/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
@@ -149,7 +149,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="58"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../../../ip_cores/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
@@ -165,67 +165,67 @@
</file>
<file xil_pn:name="../../../../ip_cores/gnum_core/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="139"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="../../../../ip_cores/gnum_core/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="148"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="../../../../ip_cores/gnum_core/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="126"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="124"/>
</file>
<file xil_pn:name="../../../../ip_cores/gnum_core/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="147"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
<file xil_pn:name="../../../../ip_cores/gnum_core/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="146"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../../../../ip_cores/gnum_core/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="145"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="../../../../ip_cores/gnum_core/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="144"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="104"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="121"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="119"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="105"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="97"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="138"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="108"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="109"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="82"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="110"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="96"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="111"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="119"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="94"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="113"/>
@@ -233,7 +233,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="114"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="74"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
@@ -241,19 +241,19 @@
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="159"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="157"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="117"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="116"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="118"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="116"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="115"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="119"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="137"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="135"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
@@ -261,11 +261,11 @@
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="121"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
@@ -273,7 +273,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="124"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
@@ -281,26 +281,26 @@
</file>
<file xil_pn:name="../../../../top/spec/tdc_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="126"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="83"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
<file xil_pn:name="../../../../top/spec/spec_top_fmc_tdc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="128"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="162"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="../../../../ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="155"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="155"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="153"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="156"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="133"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="131"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="157"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="132"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="130"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="158"/>
@@ -316,7 +316,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="161"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="131"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="129"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile_spartan6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="162"/>
@@ -328,7 +328,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="164"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="156"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="154"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="165"/>
@@ -336,7 +336,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="166"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="91"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wrc_core/wb_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="167"/>
@@ -344,7 +344,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="168"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="136"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="134"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="169"/>
@@ -352,7 +352,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="170"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="114"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="171"/>
@@ -360,27 +360,27 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="173"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="71"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="174"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="92"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="175"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="158"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="156"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="176"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="157"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="155"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="177"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="135"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="133"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="178"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="115"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="179"/>
@@ -396,11 +396,11 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="182"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="113"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="183"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="70"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="184"/>
@@ -408,7 +408,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="185"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="69"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="186"/>
@@ -428,7 +428,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="190"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="68"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="191"/>
@@ -472,7 +472,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="201"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="202"/>
@@ -504,7 +504,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="209"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="210"/>
@@ -512,7 +512,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_endpoint/ep_tx_framer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="211"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="213"/>
@@ -524,23 +524,23 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="215"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="216"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="217"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="110"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="218"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_softpll_ng/spll_bangbang_pd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="219"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_softpll_ng/spll_period_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="220"/>
@@ -548,7 +548,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="221"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="222"/>
@@ -556,11 +556,11 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="223"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="87"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
<file xil_pn:name="../../../../rtl/wrabbit_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="224"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="128"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="126"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_tbi_phy/wr_tbi_phy.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="225"/>
@@ -572,7 +572,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="227"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="134"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="132"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="228"/>
@@ -580,11 +580,11 @@
</file>
<file xil_pn:name="../../../../top/spec/spec_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="229"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="151"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="149"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="230"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="112"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_mini_nic/minic_packet_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="231"/>
@@ -592,7 +592,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="232"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="63"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="233"/>
@@ -600,19 +600,19 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="234"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="89"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="235"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="118"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="117"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="236"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="95"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="237"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="238"/>
@@ -628,11 +628,11 @@
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="243"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="80"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="244"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="79"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="245"/>
@@ -652,7 +652,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="250"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="251"/>
@@ -676,7 +676,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="258"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="77"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="259"/>
@@ -684,7 +684,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="260"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="76"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="261"/>
@@ -692,23 +692,23 @@
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="262"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="75"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="263"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="120"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="118"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="264"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="266"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="267"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="88"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="268"/>
@@ -716,7 +716,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="269"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="72"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/modules/timing/dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="270"/>
@@ -756,7 +756,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="281"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="93"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="282"/>
@@ -784,7 +784,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="288"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="73"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="289"/>
@@ -800,7 +800,7 @@
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="292"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="160"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../../../../ip_cores/wishbone/wb_conmax/xwb_conmax.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="293"/>
@@ -912,7 +912,7 @@
</file>
<file xil_pn:name="../../../../top/spec/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="322"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="150"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="148"/>
</file>
<file xil_pn:name="../../../../ip_cores/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="323"/>
@@ -988,57 +988,61 @@
</file>
<file xil_pn:name="../../../../ip_cores/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="343"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="127"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="125"/>
</file>
<file xil_pn:name="../../../../ip_cores/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="344"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="149"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
<file xil_pn:name="../../../../rtl/local_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="345"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../../../ip_cores/gnum_core/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="334"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="122"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="120"/>
</file>
<file xil_pn:name="../../../../ip_cores/gnum_core/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="335"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="161"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="159"/>
</file>
<file xil_pn:name="../../../../ip_cores/gnum_core/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="336"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="125"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="123"/>
</file>
<file xil_pn:name="../../../../ip_cores/gnum_core/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="337"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="143"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
<file xil_pn:name="../../../../ip_cores/gnum_core/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="338"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="142"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
<file xil_pn:name="../../../../ip_cores/gnum_core/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="339"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="141"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="139"/>
</file>
<file xil_pn:name="../../../../ip_cores/gnum_core/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="340"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="140"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="138"/>
</file>
<file xil_pn:name="../../../../ip_cores/gnum_core/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="341"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="124"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="122"/>
</file>
<file xil_pn:name="../../../../ip_cores/gnum_core/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="342"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="123"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="121"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file>
<file xil_pn:name="../../../../ip_cores/wrabbit/platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="107"/>
+ </file>
+ <file xil_pn:name="../../../../ip_cores/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="314"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="136"/>
</file>
</files>
diff --git a/hdl/wr_spec_tdc/hdl/top/spec/spec_top_fmc_tdc.vhd b/hdl/wr_spec_tdc/hdl/top/spec/spec_top_fmc_tdc.vhd
index 22ba3f9e68c0959ce09519fdc04e83561095b3e6..7ea6a2f99244f8f80ecaa793bd4c0367c4bd8063 100644
--- a/hdl/wr_spec_tdc/hdl/top/spec/spec_top_fmc_tdc.vhd
+++ b/hdl/wr_spec_tdc/hdl/top/spec/spec_top_fmc_tdc.vhd
@@ -700,8 +700,8 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tristates for Carrier EEPROM
- mezz_sys_scl_b <= tdc_scl_out when (tdc_scl_oen = '0') else '0' when (wrc_scl_out = '0') else 'Z';
- mezz_sys_sda_b <= tdc_sda_out when (tdc_sda_oen = '0') else '0' when (wrc_sda_out = '0') else 'Z';
+ mezz_sys_scl_b <= '0' when (wrc_scl_out = '0') else 'Z';--tdc_scl_out when (tdc_scl_oen = '0') else '0' when (wrc_scl_out = '0') else 'Z';
+ mezz_sys_sda_b <= '0' when (wrc_sda_out = '0') else 'Z';--tdc_sda_out when (tdc_sda_oen = '0') else '0' when (wrc_sda_out = '0') else 'Z';
wrc_scl_in <= mezz_sys_scl_b;
wrc_sda_in <= mezz_sys_sda_b;
tdc_scl_in <= mezz_sys_scl_b;
@@ -891,7 +891,7 @@ begin
wrabbit_time_valid_i => tm_time_valid,
wrabbit_cycles_i => tm_cycles,
wrabbit_utc_i => tm_utc(31 downto 0),
- wrabbit_utc_p_o => open,
+ wrabbit_utc_p_o => open, -- for debug
wrabbit_clk_aux_lock_en_o => tm_clk_aux_lock_en,
wrabbit_clk_aux_locked_i => tm_clk_aux_locked,
wrabbit_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the WRCore
diff --git a/hdl/wr_spec_tdc/hdl/top/spec/tdc_core_pkg.vhd b/hdl/wr_spec_tdc/hdl/top/spec/tdc_core_pkg.vhd
index 40c08e1e16a3d736d1063a70e2118bf4f296f594..0d0abd8e1f316d830acd0ad9f900711e6a2a8eb7 100644
--- a/hdl/wr_spec_tdc/hdl/top/spec/tdc_core_pkg.vhd
+++ b/hdl/wr_spec_tdc/hdl/top/spec/tdc_core_pkg.vhd
@@ -269,7 +269,7 @@ package tdc_core_pkg is
constant c_IRQ_TIME_THRESH_ADR : std_logic_vector(7 downto 0) := x"25"; -- address 0x51094 of GN4124 BAR 0
constant c_DAC_WORD_ADR : std_logic_vector(7 downto 0) := x"26"; -- address 0x51098 of GN4124 BAR 0
--- constant c_RESERVED1 : std_logic_vector(7 downto 0) := x"27"; -- address 0x5109C of GN4124 BAR 0
+ constant c_DEACT_CHAN_ADR : std_logic_vector(7 downto 0) := x"27"; -- address 0x5109C of GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Addresses of TDC core Status registers to be written by the different core units
@@ -677,6 +677,7 @@ package tdc_core_pkg is
tdc_config_wb_dat_o : out std_logic_vector(g_width-1 downto 0);
activate_acq_p_o : out std_logic;
deactivate_acq_p_o : out std_logic;
+ deactivate_chan_o : out std_logic_vector(4 downto 0);
acam_wr_config_p_o : out std_logic;
acam_rdbk_config_p_o : out std_logic;
acam_rdbk_status_p_o : out std_logic;
@@ -734,6 +735,7 @@ package tdc_core_pkg is
acam_tstamp2_ok_p_i : in std_logic;
clk_i : in std_logic;
dacapo_c_rst_p_i : in std_logic;
+ deactivate_chan_i : in std_logic_vector(4 downto 0);
rst_i : in std_logic;
roll_over_incr_recent_i : in std_logic;
clk_i_cycles_offset_i : in std_logic_vector(31 downto 0);