From 48f0a742e2505a4e7300f9ef0477f107e63d9192 Mon Sep 17 00:00:00 2001
From: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
Date: Fri, 8 Dec 2017 10:06:46 +0100
Subject: [PATCH] top/spec: cleanup, ports rename
---
hdl/top/spec/wr_spec_tdc.ucf | 280 +++++++++++++++++------------------
hdl/top/spec/wr_spec_tdc.vhd | 125 ++++++++--------
2 files changed, 198 insertions(+), 207 deletions(-)
diff --git a/hdl/top/spec/wr_spec_tdc.ucf b/hdl/top/spec/wr_spec_tdc.ucf
index 40356b7..f367558 100644
--- a/hdl/top/spec/wr_spec_tdc.ucf
+++ b/hdl/top/spec/wr_spec_tdc.ucf
@@ -38,136 +38,130 @@ TIMESPEC TS_tdc_clk_125m_n_i = PERIOD "tdc_clk_125m_n_i" 8 ns HIGH 50%;
#####################################################################
### Gennum ports
#####################################################################
-NET "L_RST_N" LOC = N20;
-NET "L_RST_N" IOSTANDARD = "LVCMOS18";
-
-NET "GPIO[1]" LOC = U16;
-NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
-NET "GPIO[0]" LOC = AB19;
-NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
-
-NET "P2L_RDY" LOC = J16;
-NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
-
-NET "P2L_CLKN" LOC = M19;
-NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
-NET "P2L_CLKP" LOC = M20;
-NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
-NET "P2L_DATA[0]" LOC = K20;
-NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[1]" LOC = H22;
-NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[2]" LOC = H21;
-NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[3]" LOC = L17;
-NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[4]" LOC = K17;
-NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[5]" LOC = G22;
-NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[6]" LOC = G20;
-NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[7]" LOC = K18;
-NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[8]" LOC = K19;
-NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[9]" LOC = H20;
-NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[10]" LOC = J19;
-NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[11]" LOC = E22;
-NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[12]" LOC = E20;
-NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[13]" LOC = F22;
-NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[14]" LOC = F21;
-NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[15]" LOC = H19;
-NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
-
-
-NET "P2L_DFRAME" LOC = J22;
-NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
-
-NET "P2L_VALID" LOC = L19;
-NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
-
-NET "P_WR_REQ[0]" LOC = M22;
-NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
-NET "P_WR_REQ[1]" LOC = M21;
-NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
-
-NET "P_WR_RDY[0]" LOC = L15;
-NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
-NET "P_WR_RDY[1]" LOC = K16;
-NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
-
-NET "RX_ERROR" LOC = J17;
-NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
-
-
-
-NET "L2P_DATA[0]" LOC = P16;
-NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[1]" LOC = P21;
-NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[2]" LOC = P18;
-NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[3]" LOC = T20;
-NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[4]" LOC = V21;
-NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[5]" LOC = V19;
-NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[6]" LOC = W22;
-NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[7]" LOC = Y22;
-NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[8]" LOC = P22;
-NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[9]" LOC = R22;
-NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[10]" LOC = T21;
-NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[11]" LOC = T19;
-NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[12]" LOC = V22;
-NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[13]" LOC = V20;
-NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[14]" LOC = W20;
-NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[15]" LOC = Y21;
-NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DFRAME" LOC = U22;
-NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
-NET "L2P_VALID" LOC = T18;
-NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
-NET "L2P_CLKN" LOC = K22;
-NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
-NET "L2P_CLKP" LOC = K21;
-NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
-NET "L2P_EDB" LOC = U20;
-NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
-
-
-NET "L2P_RDY" LOC = U19;
-NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
-NET "L_WR_RDY[0]" LOC = R20;
-NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
-NET "L_WR_RDY[1]" LOC = T22;
-NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
-NET "P_RD_D_RDY[0]" LOC = N16;
-NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
-NET "P_RD_D_RDY[1]" LOC = P19;
-NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
-NET "TX_ERROR" LOC = M17;
-NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
-NET "VC_RDY[0]" LOC = B21;
-NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
-NET "VC_RDY[1]" LOC = B22;
-NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_rst_n" LOC = N20;
+NET "gn_rst_n" IOSTANDARD = "LVCMOS18";
+
+NET "gn_gpio[1]" LOC = U16;
+NET "gn_gpio[1]" IOSTANDARD = "LVCMOS25";
+NET "gn_gpio[0]" LOC = AB19;
+NET "gn_gpio[0]" IOSTANDARD = "LVCMOS25";
+
+NET "gn_p2l_rdy" LOC = J16;
+NET "gn_p2l_rdy" IOSTANDARD = "SSTL18_I";
+
+NET "gn_p2l_clkn" LOC = M19;
+NET "gn_p2l_clkn" IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_p2l_clkp" LOC = M20;
+NET "gn_p2l_clkp" IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_p2l_data[0]" LOC = K20;
+NET "gn_p2l_data[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[1]" LOC = H22;
+NET "gn_p2l_data[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[2]" LOC = H21;
+NET "gn_p2l_data[2]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[3]" LOC = L17;
+NET "gn_p2l_data[3]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[4]" LOC = K17;
+NET "gn_p2l_data[4]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[5]" LOC = G22;
+NET "gn_p2l_data[5]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[6]" LOC = G20;
+NET "gn_p2l_data[6]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[7]" LOC = K18;
+NET "gn_p2l_data[7]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[8]" LOC = K19;
+NET "gn_p2l_data[8]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[9]" LOC = H20;
+NET "gn_p2l_data[9]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[10]" LOC = J19;
+NET "gn_p2l_data[10]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[11]" LOC = E22;
+NET "gn_p2l_data[11]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[12]" LOC = E20;
+NET "gn_p2l_data[12]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[13]" LOC = F22;
+NET "gn_p2l_data[13]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[14]" LOC = F21;
+NET "gn_p2l_data[14]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[15]" LOC = H19;
+NET "gn_p2l_data[15]" IOSTANDARD = "SSTL18_I";
+
+NET "gn_p2l_dframe" LOC = J22;
+NET "gn_p2l_dframe" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_valid" LOC = L19;
+NET "gn_p2l_valid" IOSTANDARD = "SSTL18_I";
+
+NET "gn_p_wr_req[0]" LOC = M22;
+NET "gn_p_wr_req[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_wr_req[1]" LOC = M21;
+NET "gn_p_wr_req[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_wr_rdy[0]" LOC = L15;
+NET "gn_p_wr_rdy[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_wr_rdy[1]" LOC = K16;
+NET "gn_p_wr_rdy[1]" IOSTANDARD = "SSTL18_I";
+
+NET "gn_rx_error" LOC = J17;
+NET "gn_rx_error" IOSTANDARD = "SSTL18_I";
+
+NET "gn_l2p_data[0]" LOC = P16;
+NET "gn_l2p_data[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[1]" LOC = P21;
+NET "gn_l2p_data[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[2]" LOC = P18;
+NET "gn_l2p_data[2]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[3]" LOC = T20;
+NET "gn_l2p_data[3]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[4]" LOC = V21;
+NET "gn_l2p_data[4]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[5]" LOC = V19;
+NET "gn_l2p_data[5]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[6]" LOC = W22;
+NET "gn_l2p_data[6]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[7]" LOC = Y22;
+NET "gn_l2p_data[7]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[8]" LOC = P22;
+NET "gn_l2p_data[8]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[9]" LOC = R22;
+NET "gn_l2p_data[9]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[10]" LOC = T21;
+NET "gn_l2p_data[10]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[11]" LOC = T19;
+NET "gn_l2p_data[11]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[12]" LOC = V22;
+NET "gn_l2p_data[12]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[13]" LOC = V20;
+NET "gn_l2p_data[13]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[14]" LOC = W20;
+NET "gn_l2p_data[14]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[15]" LOC = Y21;
+NET "gn_l2p_data[15]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_dframe" LOC = U22;
+NET "gn_l2p_dframe" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_valid" LOC = T18;
+NET "gn_l2p_valid" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_clkn" LOC = K22;
+NET "gn_l2p_clkn" IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_l2p_clkp" LOC = K21;
+NET "gn_l2p_clkp" IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_l2p_edb" LOC = U20;
+NET "gn_l2p_edb" IOSTANDARD = "SSTL18_I";
+
+NET "gn_l2p_rdy" LOC = U19;
+NET "gn_l2p_rdy" IOSTANDARD = "SSTL18_I";
+NET "gn_l_wr_rdy[0]" LOC = R20;
+NET "gn_l_wr_rdy[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_l_wr_rdy[1]" LOC = T22;
+NET "gn_l_wr_rdy[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_rd_d_rdy[0]" LOC = N16;
+NET "gn_p_rd_d_rdy[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_rd_d_rdy[1]" LOC = P19;
+NET "gn_p_rd_d_rdy[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_tx_error" LOC = M17;
+NET "gn_tx_error" IOSTANDARD = "SSTL18_I";
+NET "gn_vc_rdy[0]" LOC = B21;
+NET "gn_vc_rdy[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_vc_rdy[1]" LOC = B22;
+NET "gn_vc_rdy[1]" IOSTANDARD = "SSTL18_I";
#----------------------------------------
# FMC slot
@@ -343,20 +337,20 @@ NET "tdc_in_fpga_1_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Carrier Generic Stuff
#----------------------------------------
-NET "led_red" LOC = D5;
-NET "led_red" IOSTANDARD = "LVCMOS25";
-NET "led_green" LOC = E5;
-NET "led_green" IOSTANDARD = "LVCMOS25";
-NET "dac_cs1_n_o" LOC = A3;
-NET "dac_cs1_n_o" IOSTANDARD = "LVCMOS25";
-NET "dac_cs2_n_o" LOC = B3;
-NET "dac_cs2_n_o" IOSTANDARD = "LVCMOS25";
+NET "led_act_o" LOC = D5;
+NET "led_act_o" IOSTANDARD = "LVCMOS25";
+NET "led_link_o" LOC = E5;
+NET "led_link_o" IOSTANDARD = "LVCMOS25";
+NET "wr_dac_cs1_n_o" LOC = A3;
+NET "wr_dac_cs1_n_o" IOSTANDARD = "LVCMOS25";
+NET "wr_dac_cs2_n_o" LOC = B3;
+NET "wr_dac_cs2_n_o" IOSTANDARD = "LVCMOS25";
#NET "dac_clr_n_o" LOC = F7;
#NET "dac_clr_n_o" IOSTANDARD = "LVCMOS25";
-NET "dac_din_o" LOC = C4;
-NET "dac_din_o" IOSTANDARD = "LVCMOS25";
-NET "dac_sclk_o" LOC = A4;
-NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
+NET "wr_dac_din_o" LOC = C4;
+NET "wr_dac_din_o" IOSTANDARD = "LVCMOS25";
+NET "wr_dac_sclk_o" LOC = A4;
+NET "wr_dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "button1_i" LOC = C22;
NET "button1_i" IOSTANDARD = "LVCMOS18";
NET "button2_i" LOC = D21;
@@ -399,7 +393,7 @@ NET "uart_txd_o" IOSTANDARD=LVCMOS25;
# False Path
#----------------------------------------
# GN4124
-NET "l_rst_n" TIG;
+NET "gn_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
diff --git a/hdl/top/spec/wr_spec_tdc.vhd b/hdl/top/spec/wr_spec_tdc.vhd
index 0deaff6..087b819 100644
--- a/hdl/top/spec/wr_spec_tdc.vhd
+++ b/hdl/top/spec/wr_spec_tdc.vhd
@@ -150,10 +150,10 @@ entity wr_spec_tdc is
clk_20m_vcxo_i : in std_logic; -- 20 MHz VCXO
- dac_sclk_o : out std_logic; -- PLL VCXO DAC Drive
- dac_din_o : out std_logic;
- dac_cs1_n_o : out std_logic;
- dac_cs2_n_o : out std_logic;
+ wr_dac_sclk_o : out std_logic; -- PLL VCXO DAC Drive
+ wr_dac_din_o : out std_logic;
+ wr_dac_cs1_n_o : out std_logic;
+ wr_dac_cs2_n_o : out std_logic;
sfp_txp_o : out std_logic; -- SFP
sfp_txn_o : out std_logic;
@@ -182,40 +182,37 @@ entity wr_spec_tdc is
-- GN4124 PCI bridge pins
------------------------------------------------------------------------
- l_rst_n : in std_logic; -- reset from gn4124 (rstout18_n)
-
+ gn_rst_n : in std_logic; -- reset from gn4124 (rstout18_n)
-- general purpose interface
- gpio : inout std_logic_vector(1 downto 0); -- gpio[0] -> gn4124 gpio8
- -- gpio[1] -> gn4124 gpio9
+ gn_gpio : inout std_logic_vector(1 downto 0); -- gpio[0] -> gn4124 gpio8
-- pcie to local [inbound data] - rx
- p2l_rdy : out std_logic; -- rx buffer full flag
- p2l_clkn : in std_logic; -- receiver source synchronous clock-
- p2l_clkp : in std_logic; -- receiver source synchronous clock+
- p2l_data : in std_logic_vector(15 downto 0); -- parallel receive data
- p2l_dframe : in std_logic; -- receive frame
- p2l_valid : in std_logic; -- receive data valid
-
+ gn_p2l_rdy : out std_logic; -- rx buffer full flag
+ gn_p2l_clkn : in std_logic; -- receiver source synchronous clock-
+ gn_p2l_clkp : in std_logic; -- receiver source synchronous clock+
+ gn_p2l_data : in std_logic_vector(15 downto 0); -- parallel receive data
+ gn_p2l_dframe : in std_logic; -- receive frame
+ gn_p2l_valid : in std_logic; -- receive data valid
-- inbound buffer request/status
- p_wr_req : in std_logic_vector(1 downto 0); -- pcie write request
- p_wr_rdy : out std_logic_vector(1 downto 0); -- pcie write ready
- rx_error : out std_logic; -- receive error
-
+ gn_p_wr_req : in std_logic_vector(1 downto 0); -- pcie write request
+ gn_p_wr_rdy : out std_logic_vector(1 downto 0); -- pcie write ready
+ gn_rx_error : out std_logic; -- receive error
-- local to parallel [outbound data] - tx
- l2p_data : out std_logic_vector(15 downto 0); -- parallel transmit data
- l2p_dframe : out std_logic; -- transmit data frame
- l2p_valid : out std_logic; -- transmit data valid
- l2p_clkn : out std_logic; -- transmitter source synchronous clock-
- l2p_clkp : out std_logic; -- transmitter source synchronous clock+
- l2p_edb : out std_logic; -- packet termination and discard
-
+ gn_l2p_data : out std_logic_vector(15 downto 0); -- parallel transmit data
+ gn_l2p_dframe : out std_logic; -- transmit data frame
+ gn_l2p_valid : out std_logic; -- transmit data valid
+ gn_l2p_clkn : out std_logic; -- transmitter source synchronous clock-
+ gn_l2p_clkp : out std_logic; -- transmitter source synchronous clock+
+ gn_l2p_edb : out std_logic; -- packet termination and discard
-- outbound buffer status
- l2p_rdy : in std_logic; -- tx buffer full flag
- l_wr_rdy : in std_logic_vector(1 downto 0); -- local-to-pcie write
- p_rd_d_rdy : in std_logic_vector(1 downto 0); -- pcie-to-local read response data ready
- tx_error : in std_logic; -- transmit error
- vc_rdy : in std_logic_vector(1 downto 0); -- channel ready
+ gn_l2p_rdy : in std_logic; -- tx buffer full flag
+ gn_l_wr_rdy : in std_logic_vector(1 downto 0); -- local-to-pcie write
+ gn_p_rd_d_rdy : in std_logic_vector(1 downto 0); -- pcie-to-local read response data ready
+ gn_tx_error : in std_logic; -- transmit error
+ gn_vc_rdy : in std_logic_vector(1 downto 0); -- channel ready
+ ------------------------------------------------------------------------
-- Interface with the PLL AD9516 and DAC AD5662 on TDC mezzanine
+ ------------------------------------------------------------------------
pll_sclk_o : out std_logic; -- SPI clock
pll_sdi_o : out std_logic; -- data line for PLL and DAC
pll_cs_o : out std_logic; -- PLL chip select
@@ -274,8 +271,8 @@ entity wr_spec_tdc is
mezz_onewire_b : inout std_logic;
-- font panel leds
- led_red : out std_logic;
- led_green : out std_logic;
+ led_act_o : out std_logic;
+ led_link_o : out std_logic;
-- Carrier other signals
pcb_ver_i : in std_logic_vector(3 downto 0); -- PCB version
@@ -545,9 +542,9 @@ begin
-- waits for the system clock PLL to lock + additional 256 clk_62m5_sys cycles before de-asserting
-- the reset.
- p_powerup_reset : process(clk_62m5_sys, l_rst_n)
+ p_powerup_reset : process(clk_62m5_sys, gn_rst_n)
begin
- if(l_rst_n = '0') then
+ if(gn_rst_n = '0') then
rst_n_sys <= '0';
elsif rising_edge(clk_62m5_sys) then
if sys_locked = '1' then
@@ -613,8 +610,8 @@ begin
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
-- SPEC LEDs
- led_act_o => LED_RED,
- led_link_o => LED_GREEN,
+ led_act_o => led_act_o,
+ led_link_o => led_link_o,
-- SFP
scl_o => wrc_scl_out,
scl_i => wrc_scl_in,
@@ -706,11 +703,11 @@ begin
load1_i => dac_dpll_load_p1,
val2_i => dac_hpll_data,
load2_i => dac_hpll_load_p1,
- dac_cs_n_o(0) => dac_cs1_n_o,
- dac_cs_n_o(1) => dac_cs2_n_o,
+ dac_cs_n_o(0) => wr_dac_cs1_n_o,
+ dac_cs_n_o(1) => wr_dac_cs2_n_o,
-- dac_clr_n_o => open,
- dac_sclk_o => dac_sclk_o,
- dac_din_o => dac_din_o);
+ dac_sclk_o => wr_dac_sclk_o,
+ dac_din_o => wr_dac_din_o);
---------------------------------------------------------------------------------------------------
@@ -748,39 +745,39 @@ begin
---------------------------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map
- (rst_n_a_i => l_rst_n,
+ (rst_n_a_i => gn_rst_n,
status_o => gn4124_status,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
- p2l_clk_p_i => P2L_CLKp,
- p2l_clk_n_i => P2L_CLKn,
- p2l_data_i => P2L_DATA,
- p2l_dframe_i => P2L_DFRAME,
- p2l_valid_i => P2L_VALID,
+ p2l_clk_p_i => gn_p2l_clkp,
+ p2l_clk_n_i => gn_p2l_clkn,
+ p2l_data_i => gn_p2l_data,
+ p2l_dframe_i => gn_p2l_dframe,
+ p2l_valid_i => gn_p2l_valid,
-- P2L Control
- p2l_rdy_o => P2L_RDY,
- p_wr_req_i => P_WR_REQ,
- p_wr_rdy_o => P_WR_RDY,
- rx_error_o => RX_ERROR,
- vc_rdy_i => VC_RDY,
+ p2l_rdy_o => gn_p2l_rdy,
+ p_wr_req_i => gn_p_wr_req,
+ p_wr_rdy_o => gn_p_wr_rdy,
+ rx_error_o => gn_rx_error,
+ vc_rdy_i => gn_vc_rdy,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
- l2p_clk_p_o => L2P_CLKp,
- l2p_clk_n_o => L2P_CLKn,
- l2p_data_o => L2P_DATA,
- l2p_dframe_o => L2P_DFRAME,
- l2p_valid_o => L2P_VALID,
+ l2p_clk_p_o => gn_l2p_clkp,
+ l2p_clk_n_o => gn_l2p_clkn,
+ l2p_data_o => gn_l2p_data,
+ l2p_dframe_o => gn_l2p_dframe,
+ l2p_valid_o => gn_l2p_valid,
-- L2P Control
- l2p_edb_o => L2P_EDB,
- l2p_rdy_i => L2P_RDY,
- l_wr_rdy_i => L_WR_RDY,
- p_rd_d_rdy_i => P_RD_D_RDY,
- tx_error_i => TX_ERROR,
+ l2p_edb_o => gn_l2p_edb,
+ l2p_rdy_i => gn_l2p_rdy,
+ l_wr_rdy_i => gn_l_wr_rdy,
+ p_rd_d_rdy_i => gn_p_rd_d_rdy,
+ tx_error_i => gn_tx_error,
dma_irq_o => open,
irq_p_i => '0',
@@ -914,8 +911,8 @@ begin
irqs_i(0) => tdc0_irq,
irq_master_o => irq_to_gn4124);
- gpio(0) <= irq_to_gn4124;
- gpio(1) <= '0';
+ gn_gpio(0) <= irq_to_gn4124;
+ gn_gpio(1) <= '0';
---------------------------------------------------------------------------------------------------
-- Carrier CSR information --
--
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