diff --git a/hdl/spec/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.gise b/hdl/spec/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.gise
index ebb435bfca26acfd261f2e7e101d36bbed2efa42..0ea3da108dafd50a65e4e627fa5c913135473925 100644
--- a/hdl/spec/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.gise
+++ b/hdl/spec/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.gise
@@ -23,9 +23,29 @@
 
   <files xmlns="http://www.xilinx.com/XMLSchema">
     <file xil_pn:fileType="FILE_VHO" xil_pn:name="blk_mem_circ_buff_v6_4.vho" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_v6_2_readme.txt" xil_pn:origination="imported"/>
   </files>
 
-  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+  <transforms xmlns="http://www.xilinx.com/XMLSchema">
+    <transform xil_pn:end_ts="1373529468" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1373529468">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-7640980108902946276" xil_pn:start_ts="1373982765">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4819290180276573634" xil_pn:start_ts="1373982765">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1373982765">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6718039799359289506" xil_pn:start_ts="1373982765">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+  </transforms>
 
 </generated_project>
diff --git a/hdl/spec/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.xise b/hdl/spec/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.xise
index 3a607fd95727c7cc39464e28b391561646627970..a5e5cfe8f9efa238c84ca67396ef46d63b0e9ff7 100644
--- a/hdl/spec/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.xise
+++ b/hdl/spec/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.xise
@@ -12,13 +12,9 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
 
   <files>
-    <file xil_pn:name="blk_mem_circ_buff_v6_4.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-    </file>
     <file xil_pn:name="blk_mem_circ_buff_v6_4.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
@@ -29,354 +25,27 @@
   </files>
 
   <properties>
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-    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
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     <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
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-    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
-    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|blk_mem_circ_buff_v6_4|blk_mem_circ_buff_v6_4_a" xil_pn:valueState="non-default"/>
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     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/blk_mem_circ_buff_v6_4" xil_pn:valueState="non-default"/>
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-    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
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-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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-    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
-    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="blk_mem_circ_buff_v6_4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="blk_mem_circ_buff_v6_4_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="blk_mem_circ_buff_v6_4_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="blk_mem_circ_buff_v6_4_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="blk_mem_circ_buff_v6_4_translate.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="blk_mem_circ_buff_v6_4" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-11-03T17:20:47" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C04346DDB7D4C8A3736523503E81A9A6" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
diff --git a/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_1.gise b/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_1.gise
index 87cba7f42bb174b3b1da5b1c96326f5d1d57cf80..6082855cf81776aaab2aa99f8e06b05e7a1bcc1f 100644
--- a/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_1.gise
+++ b/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_1.gise
@@ -26,6 +26,27 @@
     <file xil_pn:fileType="FILE_VHO" xil_pn:name="blk_mem_gen_v6_1.vho" xil_pn:origination="imported"/>
   </files>
 
-  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+  <transforms xmlns="http://www.xilinx.com/XMLSchema">
+    <transform xil_pn:end_ts="1373529468" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1373529468">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="165936098113533828" xil_pn:start_ts="1373982765">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7071533197450788902" xil_pn:start_ts="1373982765">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1373982765">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="8814703242142704070" xil_pn:start_ts="1373982765">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+  </transforms>
 
 </generated_project>
diff --git a/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_1.xise b/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_1.xise
index 770c4b11093835d05b2a15c65078bbf1a9ad9f49..e4e52d577f7ff664e647ffc53bfdb048e3900493 100644
--- a/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_1.xise
+++ b/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_1.xise
@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="blk_mem_gen_v6_1.ngc" xil_pn:type="FILE_NGC">
@@ -29,354 +29,27 @@
   </files>
 
   <properties>
-    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
     <property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
-    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
-    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|blk_mem_gen_v6_1|blk_mem_gen_v6_1_a" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top File" xil_pn:value="blk_mem_gen_v6_1.vhd" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/blk_mem_gen_v6_1" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
-    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="blk_mem_gen_v6_1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="blk_mem_gen_v6_1_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="blk_mem_gen_v6_1_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="blk_mem_gen_v6_1_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="blk_mem_gen_v6_1_translate.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="blk_mem_gen_v6_1" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-04T19:15:30" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F14F52E8AC65CD04EE5865716F5E9AB1" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
diff --git a/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_2.gise b/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_2.gise
index 476dbfea0f450371c9b2af64aa049b3ff586dd47..9a8327b5a2fa8c0477b4123cf44075bf1962f59d 100644
--- a/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_2.gise
+++ b/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_2.gise
@@ -26,6 +26,27 @@
     <file xil_pn:fileType="FILE_VHO" xil_pn:name="blk_mem_gen_v6_2.vho" xil_pn:origination="imported"/>
   </files>
 
-  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+  <transforms xmlns="http://www.xilinx.com/XMLSchema">
+    <transform xil_pn:end_ts="1373529468" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1373529468">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4883055629214282022" xil_pn:start_ts="1373982765">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="851143268618168456" xil_pn:start_ts="1373982765">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1373982765">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4914921300466099352" xil_pn:start_ts="1373982765">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+  </transforms>
 
 </generated_project>
diff --git a/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_2.xise b/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_2.xise
index f49077c9f3ba6f5dd3a374f271741f9a580be0e3..cb13dd3b32f9225187b064af1b3946fff133de47 100644
--- a/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_2.xise
+++ b/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_2.xise
@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="blk_mem_gen_v6_2.ngc" xil_pn:type="FILE_NGC">
@@ -29,354 +29,27 @@
   </files>
 
   <properties>
-    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
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     <property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
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-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
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-    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
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     <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|blk_mem_gen_v6_2|blk_mem_gen_v6_2_a" xil_pn:valueState="non-default"/>
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     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/blk_mem_gen_v6_2" xil_pn:valueState="non-default"/>
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-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
-    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="blk_mem_gen_v6_2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="blk_mem_gen_v6_2_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="blk_mem_gen_v6_2_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="blk_mem_gen_v6_2_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="blk_mem_gen_v6_2_translate.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="blk_mem_gen_v6_2" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-06T11:33:52" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="154FAA026ABEDC68F3BC7EABEA8B3BB2" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
diff --git a/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_3.gise b/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_3.gise
index bc0bcdce41953aac1bd242eae663bb17ae2efdc4..8a165d867bb0375b968326f227e34e2ef1dc3728 100644
--- a/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_3.gise
+++ b/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_3.gise
@@ -26,6 +26,27 @@
     <file xil_pn:fileType="FILE_VHO" xil_pn:name="blk_mem_gen_v6_3.vho" xil_pn:origination="imported"/>
   </files>
 
-  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+  <transforms xmlns="http://www.xilinx.com/XMLSchema">
+    <transform xil_pn:end_ts="1373529468" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1373529468">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8846568913394521400" xil_pn:start_ts="1373982765">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5369246660214451990" xil_pn:start_ts="1373982765">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1373982765">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-197801769365351158" xil_pn:start_ts="1373982765">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+  </transforms>
 
 </generated_project>
diff --git a/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_3.xise b/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_3.xise
index a0497630c4d28c67eaad64aad05e3eea08a2e389..93e65ab20caf9dc3b47d0f4bd7204de50cb0405f 100644
--- a/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_3.xise
+++ b/hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_3.xise
@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="blk_mem_gen_v6_3.ngc" xil_pn:type="FILE_NGC">
@@ -29,354 +29,27 @@
   </files>
 
   <properties>
-    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
     <property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
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     <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|blk_mem_gen_v6_3|blk_mem_gen_v6_3_a" xil_pn:valueState="non-default"/>
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     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/blk_mem_gen_v6_3" xil_pn:valueState="non-default"/>
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-    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
-    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="blk_mem_gen_v6_3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="blk_mem_gen_v6_3_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="blk_mem_gen_v6_3_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="blk_mem_gen_v6_3_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="blk_mem_gen_v6_3_translate.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="blk_mem_gen_v6_3" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-07T17:51:06" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BA4DA6C5B8B3D7C97D43437C5B9115B5" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
diff --git a/hdl/svec/hdl/ip_cores/common/Manifest.py b/hdl/svec/hdl/ip_cores/common/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..934ac9da9bd7d8a3c3925a7623a734140a6bdf88
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/common/Manifest.py
@@ -0,0 +1,14 @@
+files = [	"gencores_pkg.vhd",
+                "gc_crc_gen.vhd",
+                "gc_moving_average.vhd",
+                "gc_extend_pulse.vhd",
+                "gc_delay_gen.vhd",
+                "gc_dual_pi_controller.vhd",
+                "gc_reset.vhd",
+                "gc_serial_dac.vhd",
+                "gc_sync_ffs.vhd",
+                "gc_arbitrated_mux.vhd",
+                "gc_pulse_synchronizer.vhd",
+                "gc_frequency_meter.vhd",
+                "gc_dual_clock_ram.vhd",
+                "gc_wfifo.vhd"];
diff --git a/hdl/svec/hdl/ip_cores/common/gc_crc_gen.vhd b/hdl/svec/hdl/ip_cores/common/gc_crc_gen.vhd
index 317d564ddc09d7947c2486681ed4c421d08dd8ba..39f9f9ead01d4494de5e3f5517c5001719ab1972 100644
--- a/hdl/svec/hdl/ip_cores/common/gc_crc_gen.vhd
+++ b/hdl/svec/hdl/ip_cores/common/gc_crc_gen.vhd
@@ -72,8 +72,7 @@ entity gc_crc_gen is
 -- word when 0)
     g_dual_width              : integer range 0 to 1   := 0;
 -- if true, match_o output is registered, otherwise it's driven combinatorially
-    g_registered_match_output : boolean                := true;
-    g_registered_crc_output   : boolean                := true); 
+    g_registered_match_output : boolean                := true); 
   port (
     clk_i  : in std_logic;              -- clock
     rst_i  : in std_logic;              -- reset, active high
@@ -81,8 +80,7 @@ entity gc_crc_gen is
     half_i : in std_logic;              -- 1: input word has g_half_width bits
                                         -- 0: input word has g_data_width bits
 
-    data_i    : in std_logic_vector(g_data_width - 1 downto 0);  -- data input
-    restart_i : in std_logic := '0';
+    data_i : in std_logic_vector(g_data_width - 1 downto 0);  -- data input
 
     match_o : out std_logic;            -- CRC match flag: 1 - CRC matches
 
@@ -102,39 +100,32 @@ architecture rtl of gc_crc_gen is
     return v_result;
   end;
 
-  function f_reverse_bytes (a : in std_logic_vector)
-    return std_logic_vector is
-    variable tmp      : std_logic_vector(a'length-1 downto 0);
-    variable v_result : std_logic_vector(a'length-1 downto 0);
-  begin
-    tmp := a;
-    for i in tmp'range loop
-      v_result(i) := tmp(((tmp'length/8-1) - i/8)*8 + (i mod 8));
-    end loop;
-    return v_result;
-  end;
-
-
-  constant msb        : integer                        := g_polynomial'length - 1;
-  constant init_msb   : integer                        := g_init_value'length - 1;
-  constant p          : std_logic_vector(msb downto 0) := g_polynomial;
-  constant dw         : integer                        := g_data_width;
-  constant pw         : integer                        := g_polynomial'length;
-  type     fb_array is array (dw downto 1) of std_logic_vector(msb downto 0);
-  type     dmsb_array is array (dw downto 1) of std_logic_vector(msb downto 1);
-  signal   crca       : fb_array;
-  signal   da, ma     : dmsb_array;
-  signal   crc        : std_logic_vector(msb downto 0);
-  signal   arst, srst : std_logic;
-
-
-  signal data_i2           : std_logic_vector(g_data_width-1 downto 0);
-  signal en_d0             : std_logic;
-  signal crc_cur, crc_next : std_logic_vector(g_polynomial'length-1 downto 0);
+  constant msb      : integer                        := g_polynomial'length - 1;
+  constant init_msb : integer                        := g_init_value'length - 1;
+  constant p        : std_logic_vector(msb downto 0) := g_polynomial;
+  constant dw       : integer                        := g_data_width;
+  constant pw       : integer                        := g_polynomial'length;
+  type fb_array is array (dw downto 1) of std_logic_vector(msb downto 0);
+  type dmsb_array is array (dw downto 1) of std_logic_vector(msb downto 1);
+  signal crca       : fb_array;
+  signal da, ma     : dmsb_array;
+  signal crc, zero  : std_logic_vector(msb downto 0);
+  signal arst, srst : std_logic;
+
+  signal a, b    : std_logic_vector(g_polynomial'length - 1 downto 0);
+  signal data_i2 : std_logic_vector(15 downto 0);
+  signal en_d0   : std_logic;
+  signal half_d0 : std_logic;
+  signal crc_tmp : std_logic_vector(31 downto 0);
+  signal crc_int : std_logic_vector(31 downto 0);
+  
 
   
 begin
 
+  a <= g_init_value;
+  b <= g_polynomial;
+
 -- Parameter checking: Invalid generics will abort simulation/synthesis
   PCHK1 : if msb /= init_msb generate
     process
@@ -163,9 +154,8 @@ begin
     end process;
   end generate PCHK3;
 
-  data_i2 <= f_reverse_bytes(data_i);
-
-  crc_cur <= g_init_value when restart_i = '1' else crc;
+  data_i2(15 downto 0) <= (data_i(7 downto 0) & data_i(15 downto 8));
+--  data_i2(15 downto 0) <= f_reverse_vector(data_i(15 downto 0));
 
 -- Generate vector of each data bit
   CA : for i in 1 to dw generate        -- data bits
@@ -176,7 +166,7 @@ begin
 
 -- Generate vector of each CRC MSB
   MS0 : for i in 1 to msb generate
-    ma(1)(i) <= crc_cur(msb);
+    ma(1)(i) <= crc(msb);
   end generate MS0;
   MSP : for i in 2 to dw generate
     MSU : for j in 1 to msb generate
@@ -185,8 +175,8 @@ begin
   end generate MSP;
 
 -- Generate feedback matrix
-  crca(1)(0)            <= da(1)(1) xor crc_cur(msb);
-  crca(1)(msb downto 1) <= crc_cur(msb - 1 downto 0) xor ((da(1) xor ma(1)) and p(msb downto 1));
+  crca(1)(0)            <= da(1)(1) xor crc(msb);
+  crca(1)(msb downto 1) <= crc(msb - 1 downto 0) xor ((da(1) xor ma(1)) and p(msb downto 1));
   FB : for i in 2 to dw generate
     crca(i)(0)            <= da(i)(1) xor crca(i - 1)(msb);
     crca(i)(msb downto 1) <= crca(i - 1)(msb - 1 downto 0) xor
@@ -203,11 +193,18 @@ begin
     arst <= rst_i;
   end generate AR;
 
+-- CRC process
+  crc_tmp <= f_reverse_vector(not crc);
+  crc_int <= crc_tmp(7 downto 0) & crc_tmp(15 downto 8) & crc_tmp(23 downto 16) & crc_tmp(31 downto 24);
+  zero    <= (others => '0');
+
+  crc_o <= crc_int;
 
   CRCP : process (clk_i, arst)
   begin
     if arst = '1' then                  -- async. reset
       crc     <= g_init_value;
+      half_d0 <= '0';
     elsif rising_edge(clk_i) then
       if srst = '1' then                -- sync. reset
         crc <= g_init_value;
@@ -222,30 +219,6 @@ begin
     end if;
   end process;
 
-  p_crc_next : process(crc, half_i, crca)
-  begin
-    if(g_registered_crc_output) then
-      crc_next <= f_reverse_bytes(f_reverse_vector(not crc));
-    else
-      if(half_i = '1' and g_dual_width = 1) then
-        crc_next <= f_reverse_bytes(f_reverse_vector(not crca(g_half_width)));
-      else
-        crc_next <= f_reverse_bytes(f_reverse_vector(not crca(g_data_width)));
-      end if;
-    end if;
-  end process;
-
-  p_crc_output : process(crc_next, crc, en_i)
-  begin
-    if(g_registered_crc_output) then
-      crc_o <= crc_next;
-    elsif(en_i = '1') then
-      crc_o <= crc_next;
-    else
-      crc_o <= f_reverse_bytes(f_reverse_vector(not crc));
-    end if;
-  end process;
-
   gen_reg_match_output : if(g_registered_match_output) generate
     
     match_gen : process (clk_i, arst)
@@ -261,7 +234,7 @@ begin
           en_d0 <= en_i;
 
           if(en_d0 = '1') then
-            if crc_next = g_residue then
+            if crc_int = g_residue then
               match_o <= '1';
             else
               match_o <= '0';
@@ -274,7 +247,7 @@ begin
   end generate gen_reg_match_output;
 
   gen_comb_match_output : if (not g_registered_match_output) generate
-    match_o <= '1' when crc_next = g_residue else '0';
+    match_o <= '1' when crc_int = g_residue else '0';
   end generate gen_comb_match_output;
 end rtl;
 
diff --git a/hdl/svec/hdl/ip_cores/common/gc_dual_clock_ram.vhd b/hdl/svec/hdl/ip_cores/common/gc_dual_clock_ram.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..90b39f794e4432f29f6c89221ad606e3a1b35453
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/common/gc_dual_clock_ram.vhd
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Read during write has an undefined result
+entity gc_dual_clock_ram is
+   generic(
+      addr_width : natural := 4;
+      data_width : natural := 32);
+   port(
+      -- write port
+      w_clk_i  : in  std_logic;
+      w_en_i   : in  std_logic;
+      w_addr_i : in  std_logic_vector(addr_width-1 downto 0);
+      w_data_i : in  std_logic_vector(data_width-1 downto 0);
+      -- read port
+      r_clk_i  : in  std_logic;
+      r_en_i   : in  std_logic;
+      r_addr_i : in  std_logic_vector(addr_width-1 downto 0);
+      r_data_o : out std_logic_vector(data_width-1 downto 0));
+end gc_dual_clock_ram;
+
+architecture rtl of gc_dual_clock_ram is
+   type ram_t is array(2**addr_width-1 downto 0) of std_logic_vector(data_width-1 downto 0);
+   signal ram : ram_t := (others => (others => '0'));
+   
+   -- Tell synthesizer we do not care about read during write behaviour
+   attribute ramstyle : string;
+   attribute ramstyle of ram : signal is "no_rw_check";
+begin
+   write : process(w_clk_i)
+   begin
+      if rising_edge(w_clk_i) then
+         if w_en_i = '1' then
+            ram(to_integer(unsigned(w_addr_i))) <= w_data_i;
+         end if;
+      end if;
+   end process;
+   
+   read : process(r_clk_i)
+   begin
+      if rising_edge(r_clk_i) then
+         if r_en_i = '1' then
+            r_data_o <= ram(to_integer(unsigned(r_addr_i)));
+         end if;
+      end if;
+   end process;
+end rtl;
diff --git a/hdl/svec/hdl/ip_cores/common/gc_extend_pulse.vhd b/hdl/svec/hdl/ip_cores/common/gc_extend_pulse.vhd
index 42f9f411f9be5d1625b6650b848689cb964b04a6..26d8564cd2a21aab87728b97ff6a326804695531 100644
--- a/hdl/svec/hdl/ip_cores/common/gc_extend_pulse.vhd
+++ b/hdl/svec/hdl/ip_cores/common/gc_extend_pulse.vhd
@@ -46,7 +46,6 @@ use ieee.NUMERIC_STD.all;
 
 library work;
 use work.gencores_pkg.all;
-use work.genram_pkg.all;
 
 entity gc_extend_pulse is
   
@@ -65,7 +64,7 @@ end gc_extend_pulse;
 
 architecture rtl of gc_extend_pulse is
 
-  signal cntr : unsigned(f_log2_size(g_width)-1 downto 0);
+  signal cntr : unsigned(31 downto 0);
   signal extended_int : std_logic;
   
 begin  -- rtl
diff --git a/hdl/svec/hdl/ip_cores/common/gc_sync_ffs.vhd b/hdl/svec/hdl/ip_cores/common/gc_sync_ffs.vhd
index 80ac1a7c6afb9ec26aed23b5a68338981ea9e2f5..43c04f3f653cc385c320a617f9033feb7cf1942e 100644
--- a/hdl/svec/hdl/ip_cores/common/gc_sync_ffs.vhd
+++ b/hdl/svec/hdl/ip_cores/common/gc_sync_ffs.vhd
@@ -58,11 +58,6 @@ end gc_sync_ffs;
 
 architecture behavioral of gc_sync_ffs is
   signal sync0, sync1, sync2 : std_logic;
-
-  attribute shreg_extract : string;
-  attribute shreg_extract of sync0  : signal is "no";
-  attribute shreg_extract of sync1  : signal is "no";
-  attribute shreg_extract of sync2  : signal is "no";
 begin
 
 
diff --git a/hdl/svec/hdl/ip_cores/common/gc_wfifo.vhd b/hdl/svec/hdl/ip_cores/common/gc_wfifo.vhd
index c775eee452059d6b0d49ef336ae1c8cfe87370ec..d09a349f39ce4cbebe4d625806dc0caea11a1e7f 100644
--- a/hdl/svec/hdl/ip_cores/common/gc_wfifo.vhd
+++ b/hdl/svec/hdl/ip_cores/common/gc_wfifo.vhd
@@ -1,10 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
-
-library work;
 use work.gencores_pkg.all;
-use work.genram_pkg.all;
 
 entity gc_wfifo is
    generic(
@@ -34,10 +31,6 @@ entity gc_wfifo is
 end gc_wfifo;
 
 architecture rtl of gc_wfifo is
-   -- Quartus 11 sometimes goes crazy and infers an altshift_taps! Stop it.
-   attribute altera_attribute : string; 
-   attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
-   
    subtype counter is unsigned(addr_width downto 0);
    type counter_shift is array(sync_depth downto 0) of counter;
    
@@ -52,7 +45,11 @@ architecture rtl of gc_wfifo is
    signal r_idx_shift_a : counter_shift; -- r_idx_gray in a_clk
    signal w_idx_shift_r : counter_shift; -- w_idx_gray in r_clk
    
-   signal qb : std_logic_vector(data_width-1 downto 0);
+   attribute altera_attribute : string; 
+   -- Quartus 11 sometimes goes crazy and infers an altshift_taps! Stop it.
+   attribute altera_attribute of r_idx_shift_w : signal is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
+   attribute altera_attribute of r_idx_shift_a : signal is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
+   attribute altera_attribute of w_idx_shift_r : signal is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
    
    function bin2gray(a : unsigned) return unsigned is
       variable o : unsigned(a'length downto 0);
@@ -97,41 +94,25 @@ architecture rtl of gc_wfifo is
       end if;
    end full;
 begin
-
-   ram : generic_simple_dpram
-     generic map(
-       g_data_width               => data_width,
-       g_size                     => 2**addr_width,
-       g_addr_conflict_resolution => "dont_care",
-       g_dual_clock               => gray_code)
-     port map(
-       clka_i => w_clk_i,
-       wea_i  => w_en_i,
-       aa_i   => index(w_idx_bnry),
-       da_i   => w_data_i,
-       clkb_i => r_clk_i,
-       ab_i   => index(r_idx_bnry),
-       qb_o   => qb);
-       
+   ram : gc_dual_clock_ram
+      generic map(addr_width => addr_width, data_width => data_width)
+      port map(w_clk_i => w_clk_i, w_en_i => w_en_i, w_addr_i => index(w_idx_bnry), w_data_i => w_data_i,
+               r_clk_i => r_clk_i, r_en_i => r_en_i, r_addr_i => index(r_idx_bnry), r_data_o => r_data_o);
+   
    read : process(r_clk_i)
       variable idx : counter;
    begin
       if rising_edge(r_clk_i) then
          if r_rst_n_i = '0' then
             idx := (others => '0');
-            r_data_o <= qb;
          elsif r_en_i = '1' then
             idx := r_idx_bnry + 1;
-            r_data_o <= qb;
          else
             idx := r_idx_bnry;
-            --r_data_o <= r_data_o; --implied
          end if;
          r_idx_bnry <= idx;
          r_idx_gray <= bin2gray(idx);
-         if sync_depth > 0 then
-           w_idx_shift_r(sync_depth downto 1) <= w_idx_shift_r(sync_depth-1 downto 0);
-         end if;
+         w_idx_shift_r(sync_depth downto 1) <= w_idx_shift_r(sync_depth-1 downto 0);
       end if;
    end process;
    w_idx_shift_r(0) <= w_idx_gray;
@@ -150,9 +131,7 @@ begin
          end if;
          w_idx_bnry <= idx;
          w_idx_gray <= bin2gray(idx);
-         if sync_depth > 0 then
-           r_idx_shift_w(sync_depth downto 1) <= r_idx_shift_w(sync_depth-1 downto 0);
-         end if;
+         r_idx_shift_w(sync_depth downto 1) <= r_idx_shift_w(sync_depth-1 downto 0);
       end if;
    end process;
    r_idx_shift_w(0) <= r_idx_gray;
@@ -171,12 +150,9 @@ begin
          end if;
          a_idx_bnry <= idx;
          a_idx_gray <= bin2gray(idx);
-         if sync_depth > 0 then
-           r_idx_shift_a(sync_depth downto 1) <= r_idx_shift_a(sync_depth-1 downto 0);
-         end if;
+         r_idx_shift_a(sync_depth downto 1) <= r_idx_shift_a(sync_depth-1 downto 0);
       end if;
    end process;
    r_idx_shift_a(0) <= r_idx_gray;
    a_rdy_o <= not full(a_idx_gray, r_idx_shift_a(sync_depth));
-
 end rtl;
diff --git a/hdl/svec/hdl/ip_cores/common/gencores_pkg.vhd b/hdl/svec/hdl/ip_cores/common/gencores_pkg.vhd
index 60cbd943a358d30d81d5b4a024267bfd3c02d61f..5b32d34414175112839124fa2019e1a5d97ad6ea 100644
--- a/hdl/svec/hdl/ip_cores/common/gencores_pkg.vhd
+++ b/hdl/svec/hdl/ip_cores/common/gencores_pkg.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2009-09-01
--- Last update: 2012-10-04
+-- Last update: 2012-03-12
 -- Platform   : FPGA-generic
 -- Standard   : VHDL '93
 -------------------------------------------------------------------------------
@@ -68,17 +68,15 @@ package gencores_pkg is
       g_half_width              : integer range 2 to 256 := 8;
       g_sync_reset              : integer range 0 to 1   := 1;
       g_dual_width              : integer range 0 to 1   := 0;
-      g_registered_match_output : boolean                := true;
-      g_registered_crc_output   : boolean                := true);
+      g_registered_match_output : boolean                := true);
     port (
-      clk_i     : in  std_logic;
-      rst_i     : in  std_logic;
-      en_i      : in  std_logic;
-      half_i    : in  std_logic;
-      restart_i : in  std_logic := '0';
-      data_i    : in  std_logic_vector(g_data_width - 1 downto 0);
-      match_o   : out std_logic;
-      crc_o     : out std_logic_vector(g_polynomial'length - 1 downto 0));
+      clk_i   : in  std_logic;
+      rst_i   : in  std_logic;
+      en_i    : in  std_logic;
+      half_i  : in  std_logic;
+      data_i  : in  std_logic_vector(g_data_width - 1 downto 0);
+      match_o : out std_logic;
+      crc_o   : out std_logic_vector(g_polynomial'length - 1 downto 0));
   end component;
 
   component gc_moving_average
@@ -190,7 +188,25 @@ package gencores_pkg is
       q_valid_o    : out std_logic;
       q_input_id_o : out std_logic_vector(f_log2_size(g_num_inputs)-1 downto 0));
   end component;
-
+  
+  -- Read during write has an undefined result
+  component gc_dual_clock_ram is
+    generic(
+      addr_width : natural := 4;
+      data_width : natural := 32);
+    port(
+      -- write port
+      w_clk_i  : in  std_logic;
+      w_en_i   : in  std_logic;
+      w_addr_i : in  std_logic_vector(addr_width-1 downto 0);
+      w_data_i : in  std_logic_vector(data_width-1 downto 0);
+      -- read port
+      r_clk_i  : in  std_logic;
+      r_en_i   : in  std_logic;
+      r_addr_i : in  std_logic_vector(addr_width-1 downto 0);
+      r_data_o : out std_logic_vector(data_width-1 downto 0));
+  end component;
+  
   -- A 'Wes' FIFO. Generic FIFO using inferred memory.
   -- Supports clock domain crossing 
   -- Should be safe from fast->slow or reversed
@@ -235,33 +251,6 @@ package gencores_pkg is
       rstn_o     : out std_logic_vector(g_clocks-1 downto 0));
   end component;
 
-  component gc_rr_arbiter
-    generic (
-      g_size : integer);
-    port (
-      clk_i        : in  std_logic;
-      rst_n_i      : in  std_logic;
-      req_i        : in  std_logic_vector(g_size-1 downto 0);
-      grant_o      : out std_logic_vector(g_size-1 downto 0);
-      grant_comb_o : out std_logic_vector(g_size-1 downto 0));
-  end component;
-
-  component gc_word_packer
-    generic (
-      g_input_width  : integer;
-      g_output_width : integer);
-    port (
-      clk_i     : in  std_logic;
-      rst_n_i   : in  std_logic;
-      d_i       : in  std_logic_vector(g_input_width-1 downto 0);
-      d_valid_i : in  std_logic;
-      d_req_o   : out std_logic;
-      flush_i   : in  std_logic := '0';
-      q_o       : out std_logic_vector(g_output_width-1 downto 0);
-      q_valid_o : out std_logic;
-      q_req_i   : in  std_logic);
-  end component;
-  
   procedure f_rr_arbitrate (
     signal req       : in  std_logic_vector;
     signal pre_grant : in  std_logic_vector;
diff --git a/hdl/svec/hdl/ip_cores/genrams/.gitignore b/hdl/svec/hdl/ip_cores/genrams/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..57272a1ed24331695137015f1bf44153ce4a4aca
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/genrams/.gitignore
@@ -0,0 +1 @@
+coregen_ip
\ No newline at end of file
diff --git a/hdl/svec/hdl/ip_cores/genrams/Manifest.py b/hdl/svec/hdl/ip_cores/genrams/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..43f2c122cdcd0ace45069a124365952acc2597df
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/genrams/Manifest.py
@@ -0,0 +1,83 @@
+#############################
+## Xilinx Coregen stuff
+#############################
+import os as __os
+import shutil as __shutil
+
+files = ["genram_pkg.vhd", "memory_loader_pkg.vhd", "generic_shiftreg_fifo.vhd"]
+
+def __copy_vhdls(cg_dir, dest_dir):
+	f = open(cg_dir+"/analyze_order.txt","r")
+	text = f.readlines();
+	f.close()
+	flist = [];
+	for fname in text:
+		f = fname.rstrip('\n')
+		__shutil.copy(cg_dir+"/"+f, dest_dir)
+		flist.append(f.split('/').pop())
+	return flist
+	
+def __import_coregen_module(path, name, work_dir):
+	__os.mkdir(work_dir+"/"+name);
+	flist = __copy_vhdls(path+"/"+name, work_dir+"/"+name)
+
+	f=open(work_dir+"/"+name+"/Manifest.py","w")
+
+	f.write("files = [\n")						
+	first=True
+	for fname in flist:
+		if not first:
+			f.write(",\n")
+		else:
+			first = False
+		f.write("\""+fname+"\"")
+
+	f.write("]\n");
+	f.write("library = \"" + name + "\"\n")
+	f.close()
+
+def __import_coregen_files():
+	xilinx_dir =  __os.getenv("XILINX");
+	if xilinx_dir == None:
+		print("[genrams] FATAL ERROR: XILINX environment variable not set. It must provide the path to ISE_DS directory in ISE installation folder (follow Xilinx instructions).")
+		__os.exit(-1)
+
+
+
+	coregen_path = xilinx_dir + "/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/"
+	if not __os.path.isdir(coregen_path):
+		print("[genrams]: FATAL ERROR: XILINX environment variable seems to be set incorrectly. It must point to ISE_DS directory in the ISE installation folder. For example: XILINX=/opt/Xilinx/ISE_DS")
+		__os.exit(-1)
+
+	work_dir = __manifest + "/coregen_ip";
+
+
+	if __os.path.isdir(work_dir):
+		return
+
+	print("[genrams] creating workdir " + work_dir)
+	__os.mkdir(work_dir);
+
+	print("[genrams] copying ISE files...")			
+	__import_coregen_module(coregen_path, "blk_mem_gen_v4_1", work_dir);
+	__import_coregen_module(coregen_path, "fifo_generator_v6_1", work_dir);
+	
+
+##############################
+## "Normal" manifest        ##
+##############################
+
+#print ("[genrams] action = " + action + ", target = " + target, ", syn_device = ", syn_device[0:4].upper())
+
+if (target == "altera"):
+	modules = {"local" : "altera"}
+elif (target == "xilinx" and action == "synthesis" and syn_device[0:4].upper()=="XC6S"):
+	__import_coregen_files()
+	modules = {"local" : ["xilinx", "xilinx/spartan6", "coregen_ip/blk_mem_gen_v4_1", "coregen_ip/fifo_generator_v6_1"]}
+elif (target == "xilinx" and action == "synthesis" and syn_device[0:4].upper()=="XC6V"):
+	__import_coregen_files()
+	modules = {"local" : ["xilinx", "xilinx/virtex6", "coregen_ip/blk_mem_gen_v4_1", "coregen_ip/fifo_generator_v6_1"]}
+elif (target == "xilinx" and action == "simulation"):
+	modules = {"local" : ["xilinx", "xilinx/spartan6", "xilinx/sim_stub"]}
+else:
+	modules = {"local" : "altera"}
diff --git a/hdl/svec/hdl/ip_cores/genrams/generic_shiftreg_fifo.vhd b/hdl/svec/hdl/ip_cores/genrams/generic_shiftreg_fifo.vhd
index 86f9fb43633f2f29be9cc8a6aae5c676c567125d..8d1b7a41ea7e4dbf22720a7dcce6b0a2c4c47b64 100644
--- a/hdl/svec/hdl/ip_cores/genrams/generic_shiftreg_fifo.vhd
+++ b/hdl/svec/hdl/ip_cores/genrams/generic_shiftreg_fifo.vhd
@@ -72,20 +72,13 @@ end generic_shiftreg_fifo;
 
 architecture rtl of generic_shiftreg_fifo is
 
-  component gc_shiftreg
-    generic (
-      g_size : integer);
-    port (
-      clk_i : in  std_logic;
-      en_i  : in  std_logic;
-      d_i   : in  std_logic;
-      q_o   : out std_logic;
-      a_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0));
-  end component;
-
-  signal pointer : integer range 0 to g_size-1 := 0;
-
-  signal srl_addr            : std_logic_vector(f_log2_size(g_size)-1 downto 0) := (others => '0');
+  constant c_srl_length : integer := g_size;  -- set to srl 'type' 16 or 32 bit length
+
+  type t_srl_array is array (c_srl_length - 1 downto 0) of std_logic_vector (g_data_width - 1 downto 0);
+
+  signal fifo_store : t_srl_array;
+  signal pointer    : integer range 0 to c_srl_length - 1;
+
   signal pointer_zero        : std_logic;
   signal pointer_full        : std_logic;
   signal pointer_almost_full : std_logic;
@@ -99,20 +92,21 @@ begin
   do_write <= '1' when (rd_i = '1' and we_i = '1')
               or (we_i = '1' and pointer_full = '0') else '0';
 
+-- data store SRL's
+  p_data_srl : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+--      if rst_n_i = '0'then
+--        for i in 0 to c_srl_length-1 loop
+--          fifo_store(i) <= (others => '0');
+--        end loop;  -- i
+      if do_write = '1' then
+        fifo_store <= fifo_store(fifo_store'left - 1 downto 0) & d_i;
+      end if;
+    end if;
+  end process;
 
-  gen_sregs : for i in 0 to g_data_width-1 generate
-    U_SRLx : gc_shiftreg
-      generic map (
-        g_size => g_size)
-      port map (
-        clk_i => clk_i,
-        en_i  => do_write,
-        d_i   => d_i(i),
-        q_o   => q_o(i),
-        a_i   => srl_addr);
-  end generate gen_sregs;
-
-  srl_addr <= std_logic_vector(to_unsigned(pointer, srl_addr'length));
+  q_o <= fifo_store(pointer);
 
   p_empty_logic : process(clk_i)
   begin
@@ -143,9 +137,7 @@ begin
   p_gen_address : process(clk_i)
   begin
     if rising_edge(clk_i) then
-      if rst_n_i = '0' then
-        pointer <= 0;
-      elsif valid_count = '1' then
+      if valid_count = '1' then
         if we_i = '1' then
           pointer <= pointer + 1;
         else
@@ -156,9 +148,9 @@ begin
   end process;
 
   -- Detect when pointer is zero and maximum
-  pointer_zero        <= '1' when pointer = 0                                else '0';
-  pointer_full        <= '1' when pointer = g_size - 1                       else '0';
-  pointer_almost_full <= '1' when pointer_full = '1' or pointer = g_size - 2 else '0';
+  pointer_zero        <= '1' when pointer = 0                                      else '0';
+  pointer_full        <= '1' when pointer = c_srl_length - 1                       else '0';
+  pointer_almost_full <= '1' when pointer_full = '1' or pointer = c_srl_length - 2 else '0';
 
 
   -- assign internal signals to outputs
diff --git a/hdl/svec/hdl/ip_cores/genrams/genram_pkg.vhd b/hdl/svec/hdl/ip_cores/genrams/genram_pkg.vhd
index b7c80b9b3c0dd9e7191e5b49ba154520e9fc6f53..0c3654466d86ff4f2ccb74679c4e4515402903ff 100644
--- a/hdl/svec/hdl/ip_cores/genrams/genram_pkg.vhd
+++ b/hdl/svec/hdl/ip_cores/genrams/genram_pkg.vhd
@@ -46,14 +46,18 @@ package genram_pkg is
 
   type t_generic_ram_init is array (integer range <>, integer range <>) of std_logic;
   
+  -- Generic RAM initialized with nothing.
+  constant c_generic_ram_nothing : t_generic_ram_init(-1 downto 0, -1 downto 0) := 
+    (others => (others => '0'));
+
   -- Single-port synchronous RAM
   component generic_spram
     generic (
       g_data_width               : natural;
       g_size                     : natural;
       g_with_byte_enable         : boolean := false;
-      g_init_file                : string  := "none";
-      g_addr_conflict_resolution : string  := "dont_care") ;
+      g_init_file                : string  := "";
+      g_addr_conflict_resolution : string  := "read_first") ;
     port (
       rst_n_i : in  std_logic;
       clk_i   : in  std_logic;
@@ -64,33 +68,14 @@ package genram_pkg is
       q_o     : out std_logic_vector(g_data_width-1 downto 0));
   end component;
 
-  component generic_simple_dpram
-    generic (
-      g_data_width               : natural;
-      g_size                     : natural;
-      g_with_byte_enable         : boolean := false;
-      g_addr_conflict_resolution : string  := "dont_care";
-      g_init_file                : string  := "none";
-      g_dual_clock               : boolean := true);
-    port (
-      rst_n_i : in  std_logic := '1';
-      clka_i  : in  std_logic;
-      bwea_i  : in  std_logic_vector((g_data_width+7)/8 -1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
-      wea_i   : in  std_logic;
-      aa_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
-      da_i    : in  std_logic_vector(g_data_width       -1 downto 0);
-      clkb_i  : in  std_logic;
-      ab_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
-      qb_o    : out std_logic_vector(g_data_width       -1 downto 0));
-  end component;
-
   component generic_dpram
     generic (
       g_data_width               : natural;
       g_size                     : natural;
       g_with_byte_enable         : boolean := false;
-      g_addr_conflict_resolution : string  := "dont_care";
-      g_init_file                : string  := "none";
+      g_addr_conflict_resolution : string  := "read_first";
+      g_init_file                : string  := "";
+      g_init_value               : t_generic_ram_init := c_generic_ram_nothing;
       g_dual_clock               : boolean := true);
     port (
       rst_n_i : in  std_logic := '1';
diff --git a/hdl/svec/hdl/ip_cores/genrams/memory_loader_pkg.vhd b/hdl/svec/hdl/ip_cores/genrams/memory_loader_pkg.vhd
index 6d0c1669113330dc43f3d84a6f59eb1f674159aa..36221c523a4978ff206a68acc2c6ad32abb43ad8 100644
--- a/hdl/svec/hdl/ip_cores/genrams/memory_loader_pkg.vhd
+++ b/hdl/svec/hdl/ip_cores/genrams/memory_loader_pkg.vhd
@@ -147,15 +147,14 @@ package body memory_loader_pkg is
     variable data_tmp : unsigned(mem_width-1 downto 0);
     variable data_int : integer;
   begin
-    if(file_name = "" or file_name = "none") then
+    if(file_name = "") then
       mem := (others => (others => '0'));
       return mem;
     end if;
 
     file_open(status, f_in, file_name, read_mode);
 
-    if(status = open_ok) then
-    else
+    if(status /= open_ok) then
       if(fail_if_notfound) then
         report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity failure;
       else
@@ -203,4 +202,4 @@ package body memory_loader_pkg is
 
 
 
-end memory_loader_pkg;
\ No newline at end of file
+end memory_loader_pkg;
diff --git a/hdl/svec/hdl/ip_cores/genrams/xilinx/Manifest.py b/hdl/svec/hdl/ip_cores/genrams/xilinx/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..93ed8529c8c08fa77129becc4ca5516b724d57d8
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/genrams/xilinx/Manifest.py
@@ -0,0 +1,6 @@
+files = [
+"generic_dpram.vhd",
+"generic_dpram_sameclock.vhd",
+"generic_dpram_dualclock.vhd",
+"generic_spram.vhd"
+]
diff --git a/hdl/svec/hdl/ip_cores/genrams/xilinx/generic_dpram.vhd b/hdl/svec/hdl/ip_cores/genrams/xilinx/generic_dpram.vhd
index 46cab6e596ebb0d344fb51d9ac6ea8a35d66a01f..052789461f72b7f9378785af409ff7b590ac7094 100644
--- a/hdl/svec/hdl/ip_cores/genrams/xilinx/generic_dpram.vhd
+++ b/hdl/svec/hdl/ip_cores/genrams/xilinx/generic_dpram.vhd
@@ -46,6 +46,7 @@ entity generic_dpram is
     g_with_byte_enable         : boolean := false;
     g_addr_conflict_resolution : string  := "read_first";
     g_init_file                : string  := "";
+    g_init_value               : t_generic_ram_init := c_generic_ram_nothing;
     g_dual_clock               : boolean := true;
     g_fail_if_file_not_found   : boolean := true
     );
@@ -83,6 +84,7 @@ architecture syn of generic_dpram is
       g_with_byte_enable         : boolean;
       g_addr_conflict_resolution : string;
       g_init_file                : string;
+      g_init_value               : t_generic_ram_init;
       g_fail_if_file_not_found   : boolean);
     port (
       rst_n_i : in  std_logic := '1';
@@ -106,6 +108,7 @@ architecture syn of generic_dpram is
       g_with_byte_enable         : boolean;
       g_addr_conflict_resolution : string;
       g_init_file                : string;
+      g_init_value               : t_generic_ram_init;
       g_fail_if_file_not_found   : boolean);
     port (
       rst_n_i : in  std_logic := '1';
@@ -133,6 +136,7 @@ begin
       g_with_byte_enable         => g_with_byte_enable,
       g_addr_conflict_resolution => g_addr_conflict_resolution,
       g_init_file                => g_init_file,
+	  g_init_value               => g_init_value,
       g_fail_if_file_not_found   => g_fail_if_file_not_found)
     port map (
       rst_n_i => rst_n_i,
@@ -159,6 +163,7 @@ begin
         g_with_byte_enable         => g_with_byte_enable,
         g_addr_conflict_resolution => g_addr_conflict_resolution,
         g_init_file                => g_init_file,
+   	    g_init_value               => g_init_value,
         g_fail_if_file_not_found   => g_fail_if_file_not_found)
       port map (
         rst_n_i => rst_n_i,
diff --git a/hdl/svec/hdl/ip_cores/genrams/xilinx/generic_dpram_dualclock.vhd b/hdl/svec/hdl/ip_cores/genrams/xilinx/generic_dpram_dualclock.vhd
index 61afc06d59ea283592f0412f5577880d352408cf..d5dcb0ba3ee4a68077f0f94beff8da2981ee21f4 100644
--- a/hdl/svec/hdl/ip_cores/genrams/xilinx/generic_dpram_dualclock.vhd
+++ b/hdl/svec/hdl/ip_cores/genrams/xilinx/generic_dpram_dualclock.vhd
@@ -45,6 +45,7 @@ entity generic_dpram_dualclock is
     g_with_byte_enable         : boolean := false;
     g_addr_conflict_resolution : string  := "read_first";
     g_init_file                : string  := "";
+    g_init_value               : t_generic_ram_init := c_generic_ram_nothing;
     g_fail_if_file_not_found   : boolean := true
     );
 
@@ -100,7 +101,11 @@ architecture syn of generic_dpram_dualclock is
 
   function f_file_contents return t_meminit_array is
   begin
-    return f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
+    if g_init_value'length > 0 then
+      return g_init_value;
+    else
+      return f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
+    end if;
   end f_file_contents;
   
   shared variable ram : t_ram_type := f_memarray_to_ramtype(f_file_contents);
@@ -123,8 +128,7 @@ begin
   s_we_a <= bwea_i and wea_rep;
   s_we_b <= bweb_i and web_rep;
 
-  gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
-                                                                     g_addr_conflict_resolution = "dont_care")) generate
+  gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and g_addr_conflict_resolution = "read_first") generate
 
 
     process (clka_i)
@@ -160,8 +164,7 @@ begin
 
 
 
-  gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
-                                                                         g_addr_conflict_resolution = "dont_care")) generate
+  gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "read_first") generate
 
     process(clka_i)
     begin
diff --git a/hdl/svec/hdl/ip_cores/genrams/xilinx/generic_dpram_sameclock.vhd b/hdl/svec/hdl/ip_cores/genrams/xilinx/generic_dpram_sameclock.vhd
index d53c161f527db0aa3626fbfa6454ff102dacb294..8c03741c4b0bfd3fb829b9ea12cdea294f7831ff 100644
--- a/hdl/svec/hdl/ip_cores/genrams/xilinx/generic_dpram_sameclock.vhd
+++ b/hdl/svec/hdl/ip_cores/genrams/xilinx/generic_dpram_sameclock.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2011-01-25
--- Last update: 2012-07-09
+-- Last update: 2012-03-28
 -- Platform   : 
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -44,6 +44,7 @@ entity generic_dpram_sameclock is
     g_with_byte_enable         : boolean := false;
     g_addr_conflict_resolution : string  := "read_first";
     g_init_file                : string  := "";
+    g_init_value               : t_generic_ram_init := c_generic_ram_nothing;
     g_fail_if_file_not_found   : boolean := true
     );
 
@@ -99,9 +100,13 @@ architecture syn of generic_dpram_sameclock is
 
   function f_file_contents return t_meminit_array is
   begin
-    return f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
+    if g_init_value'length > 0 then
+      return g_init_value;
+    else
+      return f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
+    end if;
   end f_file_contents;
-
+  
   shared variable ram : t_ram_type := f_memarray_to_ramtype(f_file_contents);
 
   signal s_we_a     : std_logic_vector(c_num_bytes-1 downto 0);
@@ -112,17 +117,6 @@ architecture syn of generic_dpram_sameclock is
 
   signal wea_rep, web_rep : std_logic_vector(c_num_bytes-1 downto 0);
 
-  function f_check_bounds(x : integer; minx : integer; maxx : integer) return integer is
-  begin
-    if(x < minx) then
-      return minx;
-    elsif(x > maxx) then
-      return maxx;
-    else
-      return x;
-    end if;
-  end f_check_bounds;
-
 begin
 
   wea_rep <= (others => wea_i);
@@ -131,20 +125,19 @@ begin
   s_we_a <= bwea_i and wea_rep;
   s_we_b <= bweb_i and web_rep;
 
-  gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
-                                                                     g_addr_conflict_resolution = "dont_care")) generate
+  gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and g_addr_conflict_resolution = "read_first") generate
 
     process (clk_i)
     begin
       if rising_edge(clk_i) then
-        qa_o <= ram(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1));
-        qb_o <= ram(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1));
+        qa_o <= ram(to_integer(unsigned(aa_i)));
+        qb_o <= ram(to_integer(unsigned(ab_i)));
         for i in 0 to c_num_bytes-1 loop
           if s_we_a(i) = '1' then
-            ram(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
+            ram(to_integer(unsigned(aa_i)))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
           end if;
           if(s_we_b(i) = '1') then
-            ram(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1))((i+1)*8-1 downto i*8) := db_i((i+1)*8-1 downto i*8);
+            ram(to_integer(unsigned(ab_i)))((i+1)*8-1 downto i*8) := db_i((i+1)*8-1 downto i*8);
           end if;
         end loop;
       end if;
@@ -154,8 +147,7 @@ begin
 
 
 
-  gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
-                                                                         g_addr_conflict_resolution = "dont_care")) generate
+  gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "read_first") generate
 
     process(clk_i)
     begin
diff --git a/hdl/svec/hdl/ip_cores/genrams/xilinx/generic_spram.vhd b/hdl/svec/hdl/ip_cores/genrams/xilinx/generic_spram.vhd
index f7c36c41ed64f1a9ba654f4c067590078fc275c2..d4f46ffd45382cb82f2f522571009347e95d2ead 100644
--- a/hdl/svec/hdl/ip_cores/genrams/xilinx/generic_spram.vhd
+++ b/hdl/svec/hdl/ip_cores/genrams/xilinx/generic_spram.vhd
@@ -86,9 +86,7 @@ architecture syn of generic_spram is
   
   
 begin
-  assert (g_init_file = "" or g_init_file = "none") 
-  report "generic_spram: Memory initialization files not supported yet. Sorry :(" 
-  severity failure;
+  assert (g_init_file = "") report "generic_spram: Memory initialization files not supported yet. Sorry :(" severity failure;
 
 
   gen_with_byte_enable_writefirst : if(g_with_byte_enable = true and g_addr_conflict_resolution = "write_first") generate
@@ -117,8 +115,7 @@ begin
 
   end generate gen_with_byte_enable_writefirst;
 
-  gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
-                                                                     g_addr_conflict_resolution = "dont_care")) generate
+  gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and g_addr_conflict_resolution = "read_first") generate
     s_we <= bwe_i when we_i = '1' else (others => '0');
 
     process(s_we, d_i)
@@ -158,8 +155,7 @@ begin
 
   end generate gen_without_byte_enable_writefirst;
 
-  gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
-                                                                         g_addr_conflict_resolution = "dont_care")) generate
+  gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "read_first") generate
 
     process(clk_i)
     begin
diff --git a/hdl/svec/hdl/ip_cores/genrams/xilinx/sim_stub/Manifest.py b/hdl/svec/hdl/ip_cores/genrams/xilinx/sim_stub/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..601d98bb615753877e0628458724179d0f9d44d7
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/genrams/xilinx/sim_stub/Manifest.py
@@ -0,0 +1,2 @@
+files = ["dummy.vhd"]
+library = "fifo_generator_v6_1"
\ No newline at end of file
diff --git a/hdl/svec/hdl/ip_cores/genrams/xilinx/sim_stub/dummy.vhd b/hdl/svec/hdl/ip_cores/genrams/xilinx/sim_stub/dummy.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..97f0171f31b8c7c6eca76702289a100542d5f961
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/genrams/xilinx/sim_stub/dummy.vhd
@@ -0,0 +1,3 @@
+entity xilinx_dummy_sim is
+
+end xilinx_dummy_sim;
\ No newline at end of file
diff --git a/hdl/svec/hdl/ip_cores/genrams/xilinx/spartan6/Manifest.py b/hdl/svec/hdl/ip_cores/genrams/xilinx/spartan6/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..aa135abaea383e996e0fdc3fa6b8af94deea8ba7
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/genrams/xilinx/spartan6/Manifest.py
@@ -0,0 +1 @@
+files =["generic_async_fifo.vhd", "generic_sync_fifo.vhd"];
\ No newline at end of file
diff --git a/hdl/svec/hdl/ip_cores/genrams/xilinx/spartan6/generic_async_fifo.vhd b/hdl/svec/hdl/ip_cores/genrams/xilinx/spartan6/generic_async_fifo.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0404ca29730ccb7f2702ea9f32e81b1db74d2b18
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/genrams/xilinx/spartan6/generic_async_fifo.vhd
@@ -0,0 +1,423 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable asynchronous FIFO (Xilinx version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_sync_fifo.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2011-05-07
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Dual-clock asynchronous FIFO. 
+-- - configurable data width and size
+-- - "show ahead" mode
+-- - configurable full/empty/almost full/almost empty/word count signals
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library fifo_generator_v6_1;
+use fifo_generator_v6_1.all;
+
+library XilinxCoreLib;
+use XilinxCoreLib.all;
+
+use work.genram_pkg.all;
+
+
+entity generic_async_fifo is
+
+  generic (
+    g_data_width : natural;
+    g_size       : natural;
+    g_show_ahead : boolean := false;
+
+    -- Read-side flag selection
+    g_with_rd_empty        : boolean := true;   -- with empty flag
+    g_with_rd_full         : boolean := false;  -- with full flag
+    g_with_rd_almost_empty : boolean := false;
+    g_with_rd_almost_full  : boolean := false;
+    g_with_rd_count        : boolean := false;  -- with words counter
+
+    g_with_wr_empty        : boolean := false;
+    g_with_wr_full         : boolean := true;
+    g_with_wr_almost_empty : boolean := false;
+    g_with_wr_almost_full  : boolean := false;
+    g_with_wr_count        : boolean := false;
+
+    g_almost_empty_threshold : integer;  -- threshold for almost empty flag
+    g_almost_full_threshold  : integer   -- threshold for almost full flag
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';
+
+
+    -- write port
+    clk_wr_i : in std_logic;
+    d_i      : in std_logic_vector(g_data_width-1 downto 0);
+    we_i     : in std_logic;
+
+    wr_empty_o        : out std_logic;
+    wr_full_o         : out std_logic;
+    wr_almost_empty_o : out std_logic;
+    wr_almost_full_o  : out std_logic;
+    wr_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+
+    -- read port
+    clk_rd_i : in  std_logic;
+    q_o      : out std_logic_vector(g_data_width-1 downto 0);
+    rd_i     : in  std_logic;
+
+    rd_empty_o        : out std_logic;
+    rd_full_o         : out std_logic;
+    rd_almost_empty_o : out std_logic;
+    rd_almost_full_o  : out std_logic;
+    rd_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
+    );
+
+end generic_async_fifo;
+
+
+architecture syn of generic_async_fifo is
+
+
+  component fifo_generator_v6_1_xst
+    generic (
+      c_has_int_clk                  : integer;
+      c_rd_freq                      : integer;
+      c_wr_response_latency          : integer;
+      c_has_srst                     : integer;
+      c_enable_rst_sync              : integer;
+      c_has_rd_data_count            : integer;
+      c_din_width                    : integer;
+      c_has_wr_data_count            : integer;
+      c_full_flags_rst_val           : integer;
+      c_implementation_type          : integer;
+      c_family                       : string;
+      c_use_embedded_reg             : integer;
+      c_has_wr_rst                   : integer;
+      c_wr_freq                      : integer;
+      c_use_dout_rst                 : integer;
+      c_underflow_low                : integer;
+      c_has_meminit_file             : integer;
+      c_has_overflow                 : integer;
+      c_preload_latency              : integer;
+      c_dout_width                   : integer;
+      c_msgon_val                    : integer;
+      c_rd_depth                     : integer;
+      c_default_value                : string;
+      c_mif_file_name                : string;
+      c_error_injection_type         : integer;
+      c_has_underflow                : integer;
+      c_has_rd_rst                   : integer;
+      c_has_almost_full              : integer;
+      c_has_rst                      : integer;
+      c_data_count_width             : integer;
+      c_has_wr_ack                   : integer;
+      c_use_ecc                      : integer;
+      c_wr_ack_low                   : integer;
+      c_common_clock                 : integer;
+      c_rd_pntr_width                : integer;
+      c_use_fwft_data_count          : integer;
+      c_has_almost_empty             : integer;
+      c_rd_data_count_width          : integer;
+      c_enable_rlocs                 : integer;
+      c_wr_pntr_width                : integer;
+      c_overflow_low                 : integer;
+      c_prog_empty_type              : integer;
+      c_optimization_mode            : integer;
+      c_wr_data_count_width          : integer;
+      c_preload_regs                 : integer;
+      c_dout_rst_val                 : string;
+      c_has_data_count               : integer;
+      c_prog_full_thresh_negate_val  : integer;
+      c_wr_depth                     : integer;
+      c_prog_empty_thresh_negate_val : integer;
+      c_prog_empty_thresh_assert_val : integer;
+      c_has_valid                    : integer;
+      c_init_wr_pntr_val             : integer;
+      c_prog_full_thresh_assert_val  : integer;
+      c_use_fifo16_flags             : integer;
+      c_has_backup                   : integer;
+      c_valid_low                    : integer;
+      c_prim_fifo_type               : string;
+      c_count_type                   : integer;
+      c_prog_full_type               : integer;
+      c_memory_type                  : integer);
+    port (
+      clk                      : in  std_logic;
+      backup                   : in  std_logic;
+      backup_marker            : in  std_logic;
+      din                      : in  std_logic_vector(g_data_width-1 downto 0);
+      prog_empty_thresh        : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_empty_thresh_assert : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_empty_thresh_negate : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_full_thresh         : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_full_thresh_assert  : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_full_thresh_negate  : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      rd_clk                   : in  std_logic;
+      rd_en                    : in  std_logic;
+      rd_rst                   : in  std_logic;
+      rst                      : in  std_logic;
+      srst                     : in  std_logic;
+      int_clk                  : in  std_logic;
+      wr_clk                   : in  std_logic;
+      wr_en                    : in  std_logic;
+      wr_rst                   : in  std_logic;
+      injectdbiterr            : in  std_logic;
+      injectsbiterr            : in  std_logic;
+      almost_empty             : out std_logic;
+      almost_full              : out std_logic;
+      data_count               : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      dout                     : out std_logic_vector(g_data_width-1 downto 0);
+      empty                    : out std_logic;
+      full                     : out std_logic;
+      overflow                 : out std_logic;
+      prog_empty               : out std_logic;
+      prog_full                : out std_logic;
+      valid                    : out std_logic;
+      rd_data_count            : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      underflow                : out std_logic;
+      wr_ack                   : out std_logic;
+      wr_data_count            : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      sbiterr                  : out std_logic;
+      dbiterr                  : out std_logic);
+  end component;
+
+  function f_bool_2_string (x : boolean) return string is
+  begin
+    if(x) then
+      return "ON";
+    else
+      return "OFF";
+    end if;
+  end f_bool_2_string;
+
+  function f_bool_2_int (x : boolean) return integer is
+  begin
+    if(x) then
+      return 1;
+    else
+      return 0;
+    end if;
+  end f_bool_2_int;
+
+  signal empty         : std_logic;
+  signal almost_empty  : std_logic;
+  signal almost_full   : std_logic;
+  signal sclr          : std_logic;
+  signal full          : std_logic;
+  signal s_dummy_zeros : std_logic_vector(f_log2_size(g_size)-1 downto 0);
+
+  signal wrusedw : std_logic_vector (f_log2_size(g_size)-1 downto 0);
+  signal rdusedw : std_logic_vector (f_log2_size(g_size)-1 downto 0);
+
+  signal rd_full_d0, rd_full_d1 : std_logic;
+  signal wr_empty_d0, wr_empty_d1 : std_logic;
+  signal rd_almost_full_d0, rd_almost_full_d1 : std_logic;
+  signal wr_almost_empty_d0, wr_almost_empty_d1 : std_logic;
+  
+begin  -- syn
+
+  s_dummy_zeros <= (others => '0');
+
+  sclr <= not rst_n_i;
+
+  wrapped_gen : fifo_generator_v6_1_xst
+    generic map (
+      c_common_clock       => 0,
+      c_count_type         => 0,
+      c_data_count_width   => f_log2_size(g_size),
+      c_default_value      => "BlankString",
+      c_din_width          => g_data_width,
+      c_dout_rst_val       => "0",
+      c_dout_width         => g_data_width,
+      c_enable_rlocs       => 0,
+      c_family             => "spartan6",
+      c_full_flags_rst_val => 1,
+
+      c_has_almost_empty  => 0,
+      c_has_almost_full   => 0,
+      c_has_backup        => 0,
+      c_has_data_count    => 0,
+      c_has_int_clk       => 0,
+      c_has_meminit_file  => 0,
+      c_has_overflow      => 0,
+      c_has_rd_data_count => f_bool_2_int(g_with_rd_count),
+      c_has_rd_rst        => 0,
+      c_has_rst           => 1,
+      c_has_srst          => 0,
+      c_has_underflow     => 0,
+      c_has_valid         => 0,
+      c_has_wr_ack        => 0,
+      c_has_wr_data_count => f_bool_2_int(g_with_wr_count),
+      c_has_wr_rst        => 0,
+
+      c_implementation_type => 2,
+      c_init_wr_pntr_val    => 0,
+      c_memory_type         => 1,
+      c_mif_file_name       => "BlankString",
+      c_optimization_mode   => 0,
+      c_overflow_low        => 0,
+      c_preload_latency     => 1,
+      c_preload_regs        => 0,
+      c_prim_fifo_type      => "1kx18",
+
+      c_prog_empty_thresh_assert_val => g_almost_empty_threshold,
+      c_prog_empty_thresh_negate_val => g_almost_empty_threshold+1,
+      c_prog_empty_type              => f_bool_2_int(g_with_rd_almost_empty or g_with_wr_almost_empty),
+      c_prog_full_thresh_assert_val  => g_almost_full_threshold,
+      c_prog_full_thresh_negate_val  => g_almost_full_threshold-1,
+      c_prog_full_type               => f_bool_2_int(g_with_rd_almost_full or g_with_wr_almost_full),
+
+      c_rd_data_count_width => f_log2_size(g_size),
+      c_rd_depth            => g_size,
+      c_rd_freq             => 1,
+      c_rd_pntr_width       => f_log2_size(g_size),
+      c_underflow_low       => 0,
+      c_use_dout_rst        => 1,
+      c_use_ecc             => 0,
+      c_use_embedded_reg    => 0,
+      c_use_fifo16_flags    => 0,
+      C_USE_FWFT_DATA_COUNT => 0,
+
+      c_wr_ack_low          => 0,
+      c_wr_data_count_width => f_log2_size(g_size),
+      c_wr_depth            => g_size,
+      c_wr_freq             => 1,
+      c_wr_pntr_width       => f_log2_size(g_size),
+      c_wr_response_latency => 1,
+
+      c_valid_low       => 0,
+      c_enable_rst_sync => 1,
+
+      c_msgon_val            => 1,
+      c_error_injection_type => 0
+
+
+      )
+    port map (
+      clk           => '0',
+      backup        => '0',
+      backup_marker => '0',
+      din           => d_i,
+
+      prog_empty_thresh        => s_dummy_zeros,
+      prog_empty_thresh_assert => s_dummy_zeros,
+      prog_empty_thresh_negate => s_dummy_zeros,
+      prog_full_thresh         => s_dummy_zeros,
+      prog_full_thresh_assert  => s_dummy_zeros,
+      prog_full_thresh_negate  => s_dummy_zeros,
+
+      rd_clk        => clk_rd_i,
+      rd_en         => rd_i,
+      rd_rst        => '0',
+      rst           => sclr,
+      srst          => '0',
+      int_clk       => '0',
+      wr_clk        => clk_wr_i,
+      wr_en         => we_i,
+      wr_rst        => '0',
+      injectdbiterr => '0',
+      injectsbiterr => '0',
+      almost_empty  => open,
+      almost_full   => open,
+      data_count    => open,
+      dout          => q_o,
+      empty         => empty,
+      full          => full,
+      overflow      => open,
+      prog_empty    => almost_empty,
+      prog_full     => almost_full,
+      valid         => open,
+      rd_data_count => rdusedw,
+      underflow     => open,
+      wr_ack        => open,
+      wr_data_count => wrusedw,
+      sbiterr       => open,
+      dbiterr       => open);
+
+
+  gen_with_wr_count : if(g_with_wr_count) generate
+    wr_count_o <= wrusedw;
+  end generate gen_with_wr_count;
+
+  gen_with_rd_count : if(g_with_rd_count) generate
+    rd_count_o <= rdusedw;
+  end generate gen_with_rd_count;
+
+  gen_with_wr_empty : if(g_with_wr_empty) generate
+    process(clk_wr_i)                   -- xilinx doesn't provide flags for
+                                        -- both clock domains
+    begin
+      if rising_edge(clk_wr_i) then
+        wr_empty_d0 <= empty;
+        wr_empty_d1 <= wr_empty_d0;
+        wr_empty_o  <= wr_empty_d1;
+      end if;
+    end process;
+  end generate gen_with_wr_empty;
+
+  gen_with_rd_empty : if(g_with_rd_empty) generate
+    rd_empty_o <= empty;
+  end generate gen_with_rd_empty;
+
+  gen_with_wr_full : if(g_with_wr_full) generate
+    wr_full_o <= full;
+  end generate gen_with_wr_full;
+
+  gen_with_rd_full : if(g_with_rd_full) generate
+    process(clk_rd_i)
+    begin
+      if rising_edge(clk_rd_i) then
+        rd_full_d0 <= full;
+        rd_full_d1 <= rd_full_d0;
+        rd_full_o  <= rd_full_d1;
+      end if;
+    end process;
+  end generate gen_with_rd_full;
+
+  gen_with_wr_almost_empty : if(g_with_wr_almost_empty) generate
+    process(clk_wr_i)                   -- xilinx doesn't provide flags for
+    begin
+      if rising_edge(clk_wr_i) then
+        wr_almost_empty_d0 <= almost_empty;
+        wr_almost_empty_d1 <= wr_almost_empty_d0;
+        wr_almost_empty_o  <= wr_almost_empty_d1;
+      end if;
+    end process;
+  end generate gen_with_wr_almost_empty;
+
+  gen_with_rd_almost_empty : if(g_with_rd_almost_empty) generate
+    rd_almost_empty_o <= almost_empty;
+  end generate gen_with_rd_almost_empty;
+
+  gen_with_wr_almost_full : if(g_with_wr_almost_full) generate
+    wr_almost_full_o <= almost_full;
+  end generate gen_with_wr_almost_full;
+
+  gen_with_rd_almost_full : if(g_with_rd_almost_full) generate
+    process(clk_rd_i)
+    begin
+      if rising_edge(clk_rd_i) then
+        rd_almost_full_d0 <= full;
+        rd_almost_full_d1 <= rd_almost_full_d0;
+        rd_almost_full_o  <= rd_almost_full_d1;
+      end if;
+    end process;
+  end generate gen_with_rd_almost_full;
+
+
+end syn;
diff --git a/hdl/svec/hdl/ip_cores/genrams/xilinx/spartan6/generic_sync_fifo.vhd b/hdl/svec/hdl/ip_cores/genrams/xilinx/spartan6/generic_sync_fifo.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1e630d10d8eb44fe6959b03802d93518ce9cb4ba
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/genrams/xilinx/spartan6/generic_sync_fifo.vhd
@@ -0,0 +1,343 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable synchronous FIFO (Xilinx version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_sync_fifo.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2011-05-11
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Single-clock FIFO. 
+-- - configurable data width and size
+-- - "show ahead" mode
+-- - configurable full/empty/almost full/almost empty/word count signals
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library fifo_generator_v6_1;
+use fifo_generator_v6_1.all;
+
+library XilinxCoreLib;
+use XilinxCoreLib.all;
+
+use work.genram_pkg.all;
+
+entity generic_sync_fifo is
+
+  generic (
+    g_data_width : natural;
+    g_size       : natural;
+    g_show_ahead : boolean := false;
+
+    -- Read-side flag selection
+    g_with_empty        : boolean := true;   -- with empty flag
+    g_with_full         : boolean := true;   -- with full flag
+    g_with_almost_empty : boolean := false;
+    g_with_almost_full  : boolean := false;
+    g_with_count        : boolean := false;  -- with words counter
+
+    g_almost_empty_threshold : integer;  -- threshold for almost empty flag
+    g_almost_full_threshold  : integer   -- threshold for almost full flag
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';
+
+    clk_i : in std_logic;
+    d_i   : in std_logic_vector(g_data_width-1 downto 0);
+    we_i  : in std_logic;
+
+    q_o  : out std_logic_vector(g_data_width-1 downto 0);
+    rd_i : in  std_logic;
+
+    empty_o        : out std_logic;
+    full_o         : out std_logic;
+    almost_empty_o : out std_logic;
+    almost_full_o  : out std_logic;
+    count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
+    );
+
+end generic_sync_fifo;
+
+architecture syn of generic_sync_fifo is
+
+
+  component fifo_generator_v6_1_xst
+    generic (
+      c_has_int_clk                  : integer;
+      c_rd_freq                      : integer;
+      c_wr_response_latency          : integer;
+      c_has_srst                     : integer;
+      c_enable_rst_sync              : integer;
+      c_has_rd_data_count            : integer;
+      c_din_width                    : integer;
+      c_has_wr_data_count            : integer;
+      c_full_flags_rst_val           : integer;
+      c_implementation_type          : integer;
+      c_family                       : string;
+      c_use_embedded_reg             : integer;
+      c_has_wr_rst                   : integer;
+      c_wr_freq                      : integer;
+      c_use_dout_rst                 : integer;
+      c_underflow_low                : integer;
+      c_has_meminit_file             : integer;
+      c_has_overflow                 : integer;
+      c_preload_latency              : integer;
+      c_dout_width                   : integer;
+      c_msgon_val                    : integer;
+      c_rd_depth                     : integer;
+      c_default_value                : string;
+      c_mif_file_name                : string;
+      c_error_injection_type         : integer;
+      c_has_underflow                : integer;
+      c_has_rd_rst                   : integer;
+      c_has_almost_full              : integer;
+      c_has_rst                      : integer;
+      c_data_count_width             : integer;
+      c_has_wr_ack                   : integer;
+      c_use_ecc                      : integer;
+      c_wr_ack_low                   : integer;
+      c_common_clock                 : integer;
+      c_rd_pntr_width                : integer;
+      c_use_fwft_data_count          : integer;
+      c_has_almost_empty             : integer;
+      c_rd_data_count_width          : integer;
+      c_enable_rlocs                 : integer;
+      c_wr_pntr_width                : integer;
+      c_overflow_low                 : integer;
+      c_prog_empty_type              : integer;
+      c_optimization_mode            : integer;
+      c_wr_data_count_width          : integer;
+      c_preload_regs                 : integer;
+      c_dout_rst_val                 : string;
+      c_has_data_count               : integer;
+      c_prog_full_thresh_negate_val  : integer;
+      c_wr_depth                     : integer;
+      c_prog_empty_thresh_negate_val : integer;
+      c_prog_empty_thresh_assert_val : integer;
+      c_has_valid                    : integer;
+      c_init_wr_pntr_val             : integer;
+      c_prog_full_thresh_assert_val  : integer;
+      c_use_fifo16_flags             : integer;
+      c_has_backup                   : integer;
+      c_valid_low                    : integer;
+      c_prim_fifo_type               : string;
+      c_count_type                   : integer;
+      c_prog_full_type               : integer;
+      c_memory_type                  : integer);
+    port (
+      clk                      : in  std_logic;
+      backup                   : in  std_logic;
+      backup_marker            : in  std_logic;
+      din                      : in  std_logic_vector(g_data_width-1 downto 0);
+      prog_empty_thresh        : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_empty_thresh_assert : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_empty_thresh_negate : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_full_thresh         : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_full_thresh_assert  : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_full_thresh_negate  : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      rd_clk                   : in  std_logic;
+      rd_en                    : in  std_logic;
+      rd_rst                   : in  std_logic;
+      rst                      : in  std_logic;
+      srst                     : in  std_logic;
+      int_clk                  : in  std_logic;
+      wr_clk                   : in  std_logic;
+      wr_en                    : in  std_logic;
+      wr_rst                   : in  std_logic;
+      injectdbiterr            : in  std_logic;
+      injectsbiterr            : in  std_logic;
+      almost_empty             : out std_logic;
+      almost_full              : out std_logic;
+      data_count               : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      dout                     : out std_logic_vector(g_data_width-1 downto 0);
+      empty                    : out std_logic;
+      full                     : out std_logic;
+      overflow                 : out std_logic;
+      prog_empty               : out std_logic;
+      prog_full                : out std_logic;
+      valid                    : out std_logic;
+      rd_data_count            : out std_logic_vector(c_rd_data_count_width-1 downto 0);
+      underflow                : out std_logic;
+      wr_ack                   : out std_logic;
+      wr_data_count            : out std_logic_vector(c_wr_data_count_width-1 downto 0);
+      sbiterr                  : out std_logic;
+      dbiterr                  : out std_logic);
+  end component;
+
+  function f_bool_2_string (x : boolean) return string is
+  begin
+    if(x) then
+      return "ON";
+    else
+      return "OFF";
+    end if;
+  end f_bool_2_string;
+
+  function f_bool_2_int (x : boolean) return integer is
+  begin
+    if(x) then
+      return 1;
+    else
+      return 0;
+    end if;
+  end f_bool_2_int;
+
+  signal empty         : std_logic;
+  signal almost_empty  : std_logic;
+  signal almost_full   : std_logic;
+  signal sclr          : std_logic;
+  signal full          : std_logic;
+  signal usedw         : std_logic_vector(f_log2_size(g_size)-1 downto 0);
+  signal s_dummy_zeros : std_logic_vector(f_log2_size(g_size)-1 downto 0);
+  
+begin  -- syn
+
+  s_dummy_zeros <= (others => '0');
+
+  sclr <= not rst_n_i;
+
+  wrapped_gen : fifo_generator_v6_1_xst
+    generic map (
+      c_common_clock       => 1,
+      c_count_type         => 0,
+      c_data_count_width   => f_log2_size(g_size),
+      c_default_value      => "BlankString",
+      c_din_width          => g_data_width,
+      c_dout_rst_val       => "0",
+      c_dout_width         => g_data_width,
+      c_enable_rlocs       => 0,
+      c_family             => "spartan6",
+      c_full_flags_rst_val => 1,
+
+      c_has_almost_empty  => 0,
+      c_has_almost_full   => 0,
+      c_has_backup        => 0,
+      c_has_data_count    => f_bool_2_int(g_with_count),
+      c_has_int_clk       => 0,
+      c_has_meminit_file  => 0,
+      c_has_overflow      => 1,
+      c_has_rd_data_count => 0,
+      c_has_rd_rst        => 0,
+      c_has_rst           => 1,
+      c_has_srst          => 0,
+      c_has_underflow     => 0,
+      c_has_valid         => 0,
+      c_has_wr_ack        => 0,
+      c_has_wr_data_count => 0,
+      c_has_wr_rst        => 0,
+
+      c_implementation_type => 0, --2,
+      c_init_wr_pntr_val    => 0,
+      c_memory_type         => 1,
+      c_mif_file_name       => "BlankString",
+      c_optimization_mode   => 0,
+      c_overflow_low        => 0,
+      c_preload_latency     => f_bool_2_int(not g_show_ahead),
+      c_preload_regs        => f_bool_2_int(g_show_ahead),
+      c_prim_fifo_type      => "1kx18",
+
+      c_prog_empty_thresh_assert_val => g_almost_empty_threshold,
+      c_prog_empty_thresh_negate_val => g_almost_empty_threshold+1,
+      c_prog_empty_type              => f_bool_2_int(g_with_almost_empty),
+      c_prog_full_thresh_assert_val  => g_almost_full_threshold,
+      c_prog_full_thresh_negate_val  => g_almost_full_threshold-1,
+      c_prog_full_type               => f_bool_2_int(g_with_almost_full),
+
+      c_rd_data_count_width => f_log2_size(g_size),
+      c_rd_depth            => g_size,
+      c_rd_freq             => 1,
+      c_rd_pntr_width       => f_log2_size(g_size),
+      c_underflow_low       => 0,
+      c_use_dout_rst        => 1,
+      c_use_ecc             => 0,
+      c_use_embedded_reg    => 0,
+      c_use_fifo16_flags    => 0,
+      C_USE_FWFT_DATA_COUNT => 0,
+
+      c_wr_ack_low          => 0,
+      c_wr_data_count_width => f_log2_size(g_size),
+      c_wr_depth            => g_size,
+      c_wr_freq             => 1,
+      c_wr_pntr_width       => f_log2_size(g_size),
+      c_wr_response_latency => 1,
+
+      c_valid_low       => 0,
+      c_enable_rst_sync => 1,
+
+      c_msgon_val            => 1,
+      c_error_injection_type => 0
+
+
+      )
+    port map (
+      clk           => clk_i,
+      backup        => '0',
+      backup_marker => '0',
+      din           => d_i,
+
+      prog_empty_thresh        => s_dummy_zeros,
+      prog_empty_thresh_assert => s_dummy_zeros,
+      prog_empty_thresh_negate => s_dummy_zeros,
+      prog_full_thresh         => s_dummy_zeros,
+      prog_full_thresh_assert  => s_dummy_zeros,
+      prog_full_thresh_negate  => s_dummy_zeros,
+
+      rd_clk        => '0',
+      rd_en         => rd_i,
+      rd_rst        => '0',
+      rst           => sclr,
+      srst          => '0',
+      int_clk       => '0',
+      wr_clk        => '0',
+      wr_en         => we_i,
+      wr_rst        => '0',
+      injectdbiterr => '0',
+      injectsbiterr => '0',
+      almost_empty  => open,
+      almost_full   => open,
+      data_count    => usedw,
+      dout          => q_o,
+      empty         => empty,
+      full          => full,
+      overflow      => open,
+      prog_empty    => almost_empty,
+      prog_full     => almost_full,
+      valid         => open,
+      rd_data_count => open,
+      underflow     => open,
+      wr_ack        => open,
+      wr_data_count => open,
+      sbiterr       => open,
+      dbiterr       => open);
+
+
+  gen_with_count : if(g_with_count) generate
+    count_o <= usedw;
+  end generate gen_with_count;
+
+  gen_with_empty : if(g_with_empty) generate
+    empty_o <= empty;
+  end generate gen_with_empty;
+
+  gen_with_full : if(g_with_full) generate
+    full_o <= full;
+  end generate gen_with_full;
+
+  almost_empty_o <= almost_empty;
+  almost_full_o <= almost_full;
+
+end syn;
diff --git a/hdl/svec/hdl/ip_cores/genrams/xilinx/virtex6/Manifest.py b/hdl/svec/hdl/ip_cores/genrams/xilinx/virtex6/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..aa135abaea383e996e0fdc3fa6b8af94deea8ba7
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/genrams/xilinx/virtex6/Manifest.py
@@ -0,0 +1 @@
+files =["generic_async_fifo.vhd", "generic_sync_fifo.vhd"];
\ No newline at end of file
diff --git a/hdl/svec/hdl/ip_cores/genrams/xilinx/virtex6/generic_async_fifo.vhd b/hdl/svec/hdl/ip_cores/genrams/xilinx/virtex6/generic_async_fifo.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e791b0321c12a88f3d330627dcf9199e8c6fc024
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/genrams/xilinx/virtex6/generic_async_fifo.vhd
@@ -0,0 +1,423 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable asynchronous FIFO (Xilinx version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_sync_fifo.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2011-05-07
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Dual-clock asynchronous FIFO. 
+-- - configurable data width and size
+-- - "show ahead" mode
+-- - configurable full/empty/almost full/almost empty/word count signals
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library fifo_generator_v6_1;
+use fifo_generator_v6_1.all;
+
+library XilinxCoreLib;
+use XilinxCoreLib.all;
+
+use work.genram_pkg.all;
+
+
+entity generic_async_fifo is
+
+  generic (
+    g_data_width : natural;
+    g_size       : natural;
+    g_show_ahead : boolean := false;
+
+    -- Read-side flag selection
+    g_with_rd_empty        : boolean := true;   -- with empty flag
+    g_with_rd_full         : boolean := false;  -- with full flag
+    g_with_rd_almost_empty : boolean := false;
+    g_with_rd_almost_full  : boolean := false;
+    g_with_rd_count        : boolean := false;  -- with words counter
+
+    g_with_wr_empty        : boolean := false;
+    g_with_wr_full         : boolean := true;
+    g_with_wr_almost_empty : boolean := false;
+    g_with_wr_almost_full  : boolean := false;
+    g_with_wr_count        : boolean := false;
+
+    g_almost_empty_threshold : integer;  -- threshold for almost empty flag
+    g_almost_full_threshold  : integer   -- threshold for almost full flag
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';
+
+
+    -- write port
+    clk_wr_i : in std_logic;
+    d_i      : in std_logic_vector(g_data_width-1 downto 0);
+    we_i     : in std_logic;
+
+    wr_empty_o        : out std_logic;
+    wr_full_o         : out std_logic;
+    wr_almost_empty_o : out std_logic;
+    wr_almost_full_o  : out std_logic;
+    wr_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+
+    -- read port
+    clk_rd_i : in  std_logic;
+    q_o      : out std_logic_vector(g_data_width-1 downto 0);
+    rd_i     : in  std_logic;
+
+    rd_empty_o        : out std_logic;
+    rd_full_o         : out std_logic;
+    rd_almost_empty_o : out std_logic;
+    rd_almost_full_o  : out std_logic;
+    rd_count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
+    );
+
+end generic_async_fifo;
+
+
+architecture syn of generic_async_fifo is
+
+
+  component fifo_generator_v6_1_xst
+    generic (
+      c_has_int_clk                  : integer;
+      c_rd_freq                      : integer;
+      c_wr_response_latency          : integer;
+      c_has_srst                     : integer;
+      c_enable_rst_sync              : integer;
+      c_has_rd_data_count            : integer;
+      c_din_width                    : integer;
+      c_has_wr_data_count            : integer;
+      c_full_flags_rst_val           : integer;
+      c_implementation_type          : integer;
+      c_family                       : string;
+      c_use_embedded_reg             : integer;
+      c_has_wr_rst                   : integer;
+      c_wr_freq                      : integer;
+      c_use_dout_rst                 : integer;
+      c_underflow_low                : integer;
+      c_has_meminit_file             : integer;
+      c_has_overflow                 : integer;
+      c_preload_latency              : integer;
+      c_dout_width                   : integer;
+      c_msgon_val                    : integer;
+      c_rd_depth                     : integer;
+      c_default_value                : string;
+      c_mif_file_name                : string;
+      c_error_injection_type         : integer;
+      c_has_underflow                : integer;
+      c_has_rd_rst                   : integer;
+      c_has_almost_full              : integer;
+      c_has_rst                      : integer;
+      c_data_count_width             : integer;
+      c_has_wr_ack                   : integer;
+      c_use_ecc                      : integer;
+      c_wr_ack_low                   : integer;
+      c_common_clock                 : integer;
+      c_rd_pntr_width                : integer;
+      c_use_fwft_data_count          : integer;
+      c_has_almost_empty             : integer;
+      c_rd_data_count_width          : integer;
+      c_enable_rlocs                 : integer;
+      c_wr_pntr_width                : integer;
+      c_overflow_low                 : integer;
+      c_prog_empty_type              : integer;
+      c_optimization_mode            : integer;
+      c_wr_data_count_width          : integer;
+      c_preload_regs                 : integer;
+      c_dout_rst_val                 : string;
+      c_has_data_count               : integer;
+      c_prog_full_thresh_negate_val  : integer;
+      c_wr_depth                     : integer;
+      c_prog_empty_thresh_negate_val : integer;
+      c_prog_empty_thresh_assert_val : integer;
+      c_has_valid                    : integer;
+      c_init_wr_pntr_val             : integer;
+      c_prog_full_thresh_assert_val  : integer;
+      c_use_fifo16_flags             : integer;
+      c_has_backup                   : integer;
+      c_valid_low                    : integer;
+      c_prim_fifo_type               : string;
+      c_count_type                   : integer;
+      c_prog_full_type               : integer;
+      c_memory_type                  : integer);
+    port (
+      clk                      : in  std_logic;
+      backup                   : in  std_logic;
+      backup_marker            : in  std_logic;
+      din                      : in  std_logic_vector(g_data_width-1 downto 0);
+      prog_empty_thresh        : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_empty_thresh_assert : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_empty_thresh_negate : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_full_thresh         : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_full_thresh_assert  : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_full_thresh_negate  : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      rd_clk                   : in  std_logic;
+      rd_en                    : in  std_logic;
+      rd_rst                   : in  std_logic;
+      rst                      : in  std_logic;
+      srst                     : in  std_logic;
+      int_clk                  : in  std_logic;
+      wr_clk                   : in  std_logic;
+      wr_en                    : in  std_logic;
+      wr_rst                   : in  std_logic;
+      injectdbiterr            : in  std_logic;
+      injectsbiterr            : in  std_logic;
+      almost_empty             : out std_logic;
+      almost_full              : out std_logic;
+      data_count               : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      dout                     : out std_logic_vector(g_data_width-1 downto 0);
+      empty                    : out std_logic;
+      full                     : out std_logic;
+      overflow                 : out std_logic;
+      prog_empty               : out std_logic;
+      prog_full                : out std_logic;
+      valid                    : out std_logic;
+      rd_data_count            : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      underflow                : out std_logic;
+      wr_ack                   : out std_logic;
+      wr_data_count            : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      sbiterr                  : out std_logic;
+      dbiterr                  : out std_logic);
+  end component;
+
+  function f_bool_2_string (x : boolean) return string is
+  begin
+    if(x) then
+      return "ON";
+    else
+      return "OFF";
+    end if;
+  end f_bool_2_string;
+
+  function f_bool_2_int (x : boolean) return integer is
+  begin
+    if(x) then
+      return 1;
+    else
+      return 0;
+    end if;
+  end f_bool_2_int;
+
+  signal empty         : std_logic;
+  signal almost_empty  : std_logic;
+  signal almost_full   : std_logic;
+  signal sclr          : std_logic;
+  signal full          : std_logic;
+  signal s_dummy_zeros : std_logic_vector(f_log2_size(g_size)-1 downto 0);
+
+  signal wrusedw : std_logic_vector (f_log2_size(g_size)-1 downto 0);
+  signal rdusedw : std_logic_vector (f_log2_size(g_size)-1 downto 0);
+
+  signal rd_full_d0, rd_full_d1 : std_logic;
+  signal wr_empty_d0, wr_empty_d1 : std_logic;
+  signal rd_almost_full_d0, rd_almost_full_d1 : std_logic;
+  signal wr_almost_empty_d0, wr_almost_empty_d1 : std_logic;
+  
+begin  -- syn
+
+  s_dummy_zeros <= (others => '0');
+
+  sclr <= not rst_n_i;
+
+  wrapped_gen : fifo_generator_v6_1_xst
+    generic map (
+      c_common_clock       => 0,
+      c_count_type         => 0,
+      c_data_count_width   => f_log2_size(g_size),
+      c_default_value      => "BlankString",
+      c_din_width          => g_data_width,
+      c_dout_rst_val       => "0",
+      c_dout_width         => g_data_width,
+      c_enable_rlocs       => 0,
+      c_family             => "virtex6",
+      c_full_flags_rst_val => 1,
+
+      c_has_almost_empty  => 0,
+      c_has_almost_full   => 0,
+      c_has_backup        => 0,
+      c_has_data_count    => 0,
+      c_has_int_clk       => 0,
+      c_has_meminit_file  => 0,
+      c_has_overflow      => 0,
+      c_has_rd_data_count => f_bool_2_int(g_with_rd_count),
+      c_has_rd_rst        => 0,
+      c_has_rst           => 1,
+      c_has_srst          => 0,
+      c_has_underflow     => 0,
+      c_has_valid         => 0,
+      c_has_wr_ack        => 0,
+      c_has_wr_data_count => f_bool_2_int(g_with_wr_count),
+      c_has_wr_rst        => 0,
+
+      c_implementation_type => 2,
+      c_init_wr_pntr_val    => 0,
+      c_memory_type         => 1,
+      c_mif_file_name       => "BlankString",
+      c_optimization_mode   => 0,
+      c_overflow_low        => 0,
+      c_preload_latency     => 1,
+      c_preload_regs        => 0,
+      c_prim_fifo_type      => "1kx18",
+
+      c_prog_empty_thresh_assert_val => g_almost_empty_threshold,
+      c_prog_empty_thresh_negate_val => g_almost_empty_threshold+1,
+      c_prog_empty_type              => f_bool_2_int(g_with_rd_almost_empty or g_with_wr_almost_empty),
+      c_prog_full_thresh_assert_val  => g_almost_full_threshold,
+      c_prog_full_thresh_negate_val  => g_almost_full_threshold-1,
+      c_prog_full_type               => f_bool_2_int(g_with_rd_almost_full or g_with_wr_almost_full),
+
+      c_rd_data_count_width => f_log2_size(g_size),
+      c_rd_depth            => g_size,
+      c_rd_freq             => 1,
+      c_rd_pntr_width       => f_log2_size(g_size),
+      c_underflow_low       => 0,
+      c_use_dout_rst        => 1,
+      c_use_ecc             => 0,
+      c_use_embedded_reg    => 0,
+      c_use_fifo16_flags    => 0,
+      C_USE_FWFT_DATA_COUNT => 0,
+
+      c_wr_ack_low          => 0,
+      c_wr_data_count_width => f_log2_size(g_size),
+      c_wr_depth            => g_size,
+      c_wr_freq             => 1,
+      c_wr_pntr_width       => f_log2_size(g_size),
+      c_wr_response_latency => 1,
+
+      c_valid_low       => 0,
+      c_enable_rst_sync => 1,
+
+      c_msgon_val            => 1,
+      c_error_injection_type => 0
+
+
+      )
+    port map (
+      clk           => '0',
+      backup        => '0',
+      backup_marker => '0',
+      din           => d_i,
+
+      prog_empty_thresh        => s_dummy_zeros,
+      prog_empty_thresh_assert => s_dummy_zeros,
+      prog_empty_thresh_negate => s_dummy_zeros,
+      prog_full_thresh         => s_dummy_zeros,
+      prog_full_thresh_assert  => s_dummy_zeros,
+      prog_full_thresh_negate  => s_dummy_zeros,
+
+      rd_clk        => clk_rd_i,
+      rd_en         => rd_i,
+      rd_rst        => '0',
+      rst           => sclr,
+      srst          => '0',
+      int_clk       => '0',
+      wr_clk        => clk_wr_i,
+      wr_en         => we_i,
+      wr_rst        => '0',
+      injectdbiterr => '0',
+      injectsbiterr => '0',
+      almost_empty  => open,
+      almost_full   => open,
+      data_count    => open,
+      dout          => q_o,
+      empty         => empty,
+      full          => full,
+      overflow      => open,
+      prog_empty    => almost_empty,
+      prog_full     => almost_full,
+      valid         => open,
+      rd_data_count => rdusedw,
+      underflow     => open,
+      wr_ack        => open,
+      wr_data_count => wrusedw,
+      sbiterr       => open,
+      dbiterr       => open);
+
+
+  gen_with_wr_count : if(g_with_wr_count) generate
+    wr_count_o <= wrusedw;
+  end generate gen_with_wr_count;
+
+  gen_with_rd_count : if(g_with_rd_count) generate
+    rd_count_o <= rdusedw;
+  end generate gen_with_rd_count;
+
+  gen_with_wr_empty : if(g_with_wr_empty) generate
+    process(clk_wr_i)                   -- xilinx doesn't provide flags for
+                                        -- both clock domains
+    begin
+      if rising_edge(clk_wr_i) then
+        wr_empty_d0 <= empty;
+        wr_empty_d1 <= wr_empty_d0;
+        wr_empty_o  <= wr_empty_d1;
+      end if;
+    end process;
+  end generate gen_with_wr_empty;
+
+  gen_with_rd_empty : if(g_with_rd_empty) generate
+    rd_empty_o <= empty;
+  end generate gen_with_rd_empty;
+
+  gen_with_wr_full : if(g_with_wr_full) generate
+    wr_full_o <= full;
+  end generate gen_with_wr_full;
+
+  gen_with_rd_full : if(g_with_rd_full) generate
+    process(clk_rd_i)
+    begin
+      if rising_edge(clk_rd_i) then
+        rd_full_d0 <= full;
+        rd_full_d1 <= rd_full_d0;
+        rd_full_o  <= rd_full_d1;
+      end if;
+    end process;
+  end generate gen_with_rd_full;
+
+  gen_with_wr_almost_empty : if(g_with_wr_almost_empty) generate
+    process(clk_wr_i)                   -- xilinx doesn't provide flags for
+    begin
+      if rising_edge(clk_wr_i) then
+        wr_almost_empty_d0 <= almost_empty;
+        wr_almost_empty_d1 <= wr_almost_empty_d0;
+        wr_almost_empty_o  <= wr_almost_empty_d1;
+      end if;
+    end process;
+  end generate gen_with_wr_almost_empty;
+
+  gen_with_rd_almost_empty : if(g_with_rd_almost_empty) generate
+    rd_almost_empty_o <= almost_empty;
+  end generate gen_with_rd_almost_empty;
+
+  gen_with_wr_almost_full : if(g_with_wr_almost_full) generate
+    wr_almost_full_o <= almost_full;
+  end generate gen_with_wr_almost_full;
+
+  gen_with_rd_almost_full : if(g_with_rd_almost_full) generate
+    process(clk_rd_i)
+    begin
+      if rising_edge(clk_rd_i) then
+        rd_almost_full_d0 <= full;
+        rd_almost_full_d1 <= rd_almost_full_d0;
+        rd_almost_full_o  <= rd_almost_full_d1;
+      end if;
+    end process;
+  end generate gen_with_rd_almost_full;
+
+
+end syn;
diff --git a/hdl/svec/hdl/ip_cores/genrams/xilinx/virtex6/generic_sync_fifo.vhd b/hdl/svec/hdl/ip_cores/genrams/xilinx/virtex6/generic_sync_fifo.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f597b0306a3b8816fd25c4df2f1a8fd12dfd1e71
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/genrams/xilinx/virtex6/generic_sync_fifo.vhd
@@ -0,0 +1,343 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable synchronous FIFO (Xilinx version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_sync_fifo.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-01-25
+-- Last update: 2011-05-11
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Single-clock FIFO. 
+-- - configurable data width and size
+-- - "show ahead" mode
+-- - configurable full/empty/almost full/almost empty/word count signals
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-01-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library fifo_generator_v6_1;
+use fifo_generator_v6_1.all;
+
+library XilinxCoreLib;
+use XilinxCoreLib.all;
+
+use work.genram_pkg.all;
+
+entity generic_sync_fifo is
+
+  generic (
+    g_data_width : natural;
+    g_size       : natural;
+    g_show_ahead : boolean := false;
+
+    -- Read-side flag selection
+    g_with_empty        : boolean := true;   -- with empty flag
+    g_with_full         : boolean := true;   -- with full flag
+    g_with_almost_empty : boolean := false;
+    g_with_almost_full  : boolean := false;
+    g_with_count        : boolean := false;  -- with words counter
+
+    g_almost_empty_threshold : integer;  -- threshold for almost empty flag
+    g_almost_full_threshold  : integer   -- threshold for almost full flag
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';
+
+    clk_i : in std_logic;
+    d_i   : in std_logic_vector(g_data_width-1 downto 0);
+    we_i  : in std_logic;
+
+    q_o  : out std_logic_vector(g_data_width-1 downto 0);
+    rd_i : in  std_logic;
+
+    empty_o        : out std_logic;
+    full_o         : out std_logic;
+    almost_empty_o : out std_logic;
+    almost_full_o  : out std_logic;
+    count_o        : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
+    );
+
+end generic_sync_fifo;
+
+architecture syn of generic_sync_fifo is
+
+
+  component fifo_generator_v6_1_xst
+    generic (
+      c_has_int_clk                  : integer;
+      c_rd_freq                      : integer;
+      c_wr_response_latency          : integer;
+      c_has_srst                     : integer;
+      c_enable_rst_sync              : integer;
+      c_has_rd_data_count            : integer;
+      c_din_width                    : integer;
+      c_has_wr_data_count            : integer;
+      c_full_flags_rst_val           : integer;
+      c_implementation_type          : integer;
+      c_family                       : string;
+      c_use_embedded_reg             : integer;
+      c_has_wr_rst                   : integer;
+      c_wr_freq                      : integer;
+      c_use_dout_rst                 : integer;
+      c_underflow_low                : integer;
+      c_has_meminit_file             : integer;
+      c_has_overflow                 : integer;
+      c_preload_latency              : integer;
+      c_dout_width                   : integer;
+      c_msgon_val                    : integer;
+      c_rd_depth                     : integer;
+      c_default_value                : string;
+      c_mif_file_name                : string;
+      c_error_injection_type         : integer;
+      c_has_underflow                : integer;
+      c_has_rd_rst                   : integer;
+      c_has_almost_full              : integer;
+      c_has_rst                      : integer;
+      c_data_count_width             : integer;
+      c_has_wr_ack                   : integer;
+      c_use_ecc                      : integer;
+      c_wr_ack_low                   : integer;
+      c_common_clock                 : integer;
+      c_rd_pntr_width                : integer;
+      c_use_fwft_data_count          : integer;
+      c_has_almost_empty             : integer;
+      c_rd_data_count_width          : integer;
+      c_enable_rlocs                 : integer;
+      c_wr_pntr_width                : integer;
+      c_overflow_low                 : integer;
+      c_prog_empty_type              : integer;
+      c_optimization_mode            : integer;
+      c_wr_data_count_width          : integer;
+      c_preload_regs                 : integer;
+      c_dout_rst_val                 : string;
+      c_has_data_count               : integer;
+      c_prog_full_thresh_negate_val  : integer;
+      c_wr_depth                     : integer;
+      c_prog_empty_thresh_negate_val : integer;
+      c_prog_empty_thresh_assert_val : integer;
+      c_has_valid                    : integer;
+      c_init_wr_pntr_val             : integer;
+      c_prog_full_thresh_assert_val  : integer;
+      c_use_fifo16_flags             : integer;
+      c_has_backup                   : integer;
+      c_valid_low                    : integer;
+      c_prim_fifo_type               : string;
+      c_count_type                   : integer;
+      c_prog_full_type               : integer;
+      c_memory_type                  : integer);
+    port (
+      clk                      : in  std_logic;
+      backup                   : in  std_logic;
+      backup_marker            : in  std_logic;
+      din                      : in  std_logic_vector(g_data_width-1 downto 0);
+      prog_empty_thresh        : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_empty_thresh_assert : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_empty_thresh_negate : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_full_thresh         : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_full_thresh_assert  : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      prog_full_thresh_negate  : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      rd_clk                   : in  std_logic;
+      rd_en                    : in  std_logic;
+      rd_rst                   : in  std_logic;
+      rst                      : in  std_logic;
+      srst                     : in  std_logic;
+      int_clk                  : in  std_logic;
+      wr_clk                   : in  std_logic;
+      wr_en                    : in  std_logic;
+      wr_rst                   : in  std_logic;
+      injectdbiterr            : in  std_logic;
+      injectsbiterr            : in  std_logic;
+      almost_empty             : out std_logic;
+      almost_full              : out std_logic;
+      data_count               : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      dout                     : out std_logic_vector(g_data_width-1 downto 0);
+      empty                    : out std_logic;
+      full                     : out std_logic;
+      overflow                 : out std_logic;
+      prog_empty               : out std_logic;
+      prog_full                : out std_logic;
+      valid                    : out std_logic;
+      rd_data_count            : out std_logic_vector(c_rd_data_count_width-1 downto 0);
+      underflow                : out std_logic;
+      wr_ack                   : out std_logic;
+      wr_data_count            : out std_logic_vector(c_wr_data_count_width-1 downto 0);
+      sbiterr                  : out std_logic;
+      dbiterr                  : out std_logic);
+  end component;
+
+  function f_bool_2_string (x : boolean) return string is
+  begin
+    if(x) then
+      return "ON";
+    else
+      return "OFF";
+    end if;
+  end f_bool_2_string;
+
+  function f_bool_2_int (x : boolean) return integer is
+  begin
+    if(x) then
+      return 1;
+    else
+      return 0;
+    end if;
+  end f_bool_2_int;
+
+  signal empty         : std_logic;
+  signal almost_empty  : std_logic;
+  signal almost_full   : std_logic;
+  signal sclr          : std_logic;
+  signal full          : std_logic;
+  signal usedw         : std_logic_vector(f_log2_size(g_size)-1 downto 0);
+  signal s_dummy_zeros : std_logic_vector(f_log2_size(g_size)-1 downto 0);
+  
+begin  -- syn
+
+  s_dummy_zeros <= (others => '0');
+
+  sclr <= not rst_n_i;
+
+  wrapped_gen : fifo_generator_v6_1_xst
+    generic map (
+      c_common_clock       => 1,
+      c_count_type         => 0,
+      c_data_count_width   => f_log2_size(g_size),
+      c_default_value      => "BlankString",
+      c_din_width          => g_data_width,
+      c_dout_rst_val       => "0",
+      c_dout_width         => g_data_width,
+      c_enable_rlocs       => 0,
+      c_family             => "virtex6",
+      c_full_flags_rst_val => 1,
+
+      c_has_almost_empty  => 0,
+      c_has_almost_full   => 0,
+      c_has_backup        => 0,
+      c_has_data_count    => f_bool_2_int(g_with_count),
+      c_has_int_clk       => 0,
+      c_has_meminit_file  => 0,
+      c_has_overflow      => 1,
+      c_has_rd_data_count => 0,
+      c_has_rd_rst        => 0,
+      c_has_rst           => 1,
+      c_has_srst          => 0,
+      c_has_underflow     => 0,
+      c_has_valid         => 0,
+      c_has_wr_ack        => 0,
+      c_has_wr_data_count => 0,
+      c_has_wr_rst        => 0,
+
+      c_implementation_type => 0, --2,
+      c_init_wr_pntr_val    => 0,
+      c_memory_type         => 1,
+      c_mif_file_name       => "BlankString",
+      c_optimization_mode   => 0,
+      c_overflow_low        => 0,
+      c_preload_latency     => 1,
+      c_preload_regs        => 0,
+      c_prim_fifo_type      => "1kx18",
+
+      c_prog_empty_thresh_assert_val => g_almost_empty_threshold,
+      c_prog_empty_thresh_negate_val => g_almost_empty_threshold+1,
+      c_prog_empty_type              => f_bool_2_int(g_with_almost_empty),
+      c_prog_full_thresh_assert_val  => g_almost_full_threshold,
+      c_prog_full_thresh_negate_val  => g_almost_full_threshold-1,
+      c_prog_full_type               => f_bool_2_int(g_with_almost_full),
+
+      c_rd_data_count_width => f_log2_size(g_size),
+      c_rd_depth            => g_size,
+      c_rd_freq             => 1,
+      c_rd_pntr_width       => f_log2_size(g_size),
+      c_underflow_low       => 0,
+      c_use_dout_rst        => 1,
+      c_use_ecc             => 0,
+      c_use_embedded_reg    => 0,
+      c_use_fifo16_flags    => 0,
+      C_USE_FWFT_DATA_COUNT => 0,
+
+      c_wr_ack_low          => 0,
+      c_wr_data_count_width => f_log2_size(g_size),
+      c_wr_depth            => g_size,
+      c_wr_freq             => 1,
+      c_wr_pntr_width       => f_log2_size(g_size),
+      c_wr_response_latency => 1,
+
+      c_valid_low       => 0,
+      c_enable_rst_sync => 1,
+
+      c_msgon_val            => 1,
+      c_error_injection_type => 0
+
+
+      )
+    port map (
+      clk           => clk_i,
+      backup        => '0',
+      backup_marker => '0',
+      din           => d_i,
+
+      prog_empty_thresh        => s_dummy_zeros,
+      prog_empty_thresh_assert => s_dummy_zeros,
+      prog_empty_thresh_negate => s_dummy_zeros,
+      prog_full_thresh         => s_dummy_zeros,
+      prog_full_thresh_assert  => s_dummy_zeros,
+      prog_full_thresh_negate  => s_dummy_zeros,
+
+      rd_clk        => '0',
+      rd_en         => rd_i,
+      rd_rst        => '0',
+      rst           => sclr,
+      srst          => '0',
+      int_clk       => '0',
+      wr_clk        => '0',
+      wr_en         => we_i,
+      wr_rst        => '0',
+      injectdbiterr => '0',
+      injectsbiterr => '0',
+      almost_empty  => open,
+      almost_full   => open,
+      data_count    => usedw,
+      dout          => q_o,
+      empty         => empty,
+      full          => full,
+      overflow      => open,
+      prog_empty    => almost_empty,
+      prog_full     => almost_full,
+      valid         => open,
+      rd_data_count => open,
+      underflow     => open,
+      wr_ack        => open,
+      wr_data_count => open,
+      sbiterr       => open,
+      dbiterr       => open);
+
+
+  gen_with_count : if(g_with_count) generate
+    count_o <= usedw;
+  end generate gen_with_count;
+
+  gen_with_empty : if(g_with_empty) generate
+    empty_o <= empty;
+  end generate gen_with_empty;
+
+  gen_with_full : if(g_with_full) generate
+    full_o <= full;
+  end generate gen_with_full;
+
+  almost_empty_o <= almost_empty;
+  almost_full_o <= almost_full;
+
+end syn;
diff --git a/hdl/svec/hdl/ip_cores/wishbone/Manifest.py b/hdl/svec/hdl/ip_cores/wishbone/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..140fc12c15686bd11d205ab955a5ee00675ca126
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/wishbone/Manifest.py
@@ -0,0 +1,28 @@
+def __helper():
+  dirs = [
+    "wb_async_bridge",
+    "wb_onewire_master",
+    "wb_i2c_master",
+    "wb_bus_fanout",
+    "wb_dpram",
+    "wb_gpio_port",
+    "wb_simple_timer",
+    "wb_uart",
+    "wb_vic",
+    "wb_spi",
+    "wb_crossbar",
+    "wb_lm32",
+    "wb_slave_adapter",
+    "wb_xilinx_fpga_loader",
+    "wb_clock_crossing",
+    "wb_dma",
+    "wb_serial_lcd",
+		"wb_simple_pwm",
+    "wbgen2"
+    ]
+  if (target == "altera"): dirs.extend(["wb_pcie"]);
+  return dirs
+
+modules =  { "local" : __helper() };
+
+files = ["wishbone_pkg.vhd"];
diff --git a/hdl/svec/hdl/ip_cores/wishbone/wb_clock_crossing/Manifest.py b/hdl/svec/hdl/ip_cores/wishbone/wb_clock_crossing/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..2e2cf232d123f2558f2d56e39199b10f37e81e66
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/wishbone/wb_clock_crossing/Manifest.py
@@ -0,0 +1 @@
+files = [ "xwb_clock_crossing.vhd" ];
diff --git a/hdl/svec/hdl/ip_cores/wishbone/wb_crossbar/Manifest.py b/hdl/svec/hdl/ip_cores/wishbone/wb_crossbar/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..25b9af39fe055eb4631dec5a68318c24998a0277
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/wishbone/wb_crossbar/Manifest.py
@@ -0,0 +1,4 @@
+files = [
+  "sdb_rom.vhd", 
+  "xwb_crossbar.vhd",
+  "xwb_sdb_crossbar.vhd" ];
diff --git a/hdl/svec/hdl/ip_cores/wishbone/wb_i2c_master/Manifest.py b/hdl/svec/hdl/ip_cores/wishbone/wb_i2c_master/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..5cb08fbae6c15a977c94bfce59e34d9bfaf6c155
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/wishbone/wb_i2c_master/Manifest.py
@@ -0,0 +1,5 @@
+files= ["i2c_master_bit_ctrl.vhd",
+"i2c_master_byte_ctrl.vhd",
+"i2c_master_top.vhd",
+"wb_i2c_master.vhd",
+"xwb_i2c_master.vhd"];
diff --git a/hdl/svec/hdl/ip_cores/wishbone/wb_onewire_master/Manifest.py b/hdl/svec/hdl/ip_cores/wishbone/wb_onewire_master/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..79f1f2ae040b8c419d5165ffa34234d1745f7637
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/wishbone/wb_onewire_master/Manifest.py
@@ -0,0 +1,3 @@
+files = ["wb_onewire_master.vhd",
+				 "xwb_onewire_master.vhd",
+				 "sockit_owm.v"];
diff --git a/hdl/svec/hdl/ip_cores/wishbone/wb_slave_adapter/Manifest.py b/hdl/svec/hdl/ip_cores/wishbone/wb_slave_adapter/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..de5a1a9afaf6b5e9dfd5fcba7b36fbc8d0eb2cc5
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/wishbone/wb_slave_adapter/Manifest.py
@@ -0,0 +1 @@
+files = ["wb_slave_adapter.vhd"]
diff --git a/hdl/svec/hdl/ip_cores/wishbone/wb_slave_adapter/wb_slave_adapter.vhd b/hdl/svec/hdl/ip_cores/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
index 98f5eb9b1cc0fd21978eeb1d0e1d47334519398c..f56b2d415a69dcacbc64f04f56b24486457cf02c 100644
--- a/hdl/svec/hdl/ip_cores/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
+++ b/hdl/svec/hdl/ip_cores/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
@@ -116,7 +116,7 @@ begin  -- rtl
   sl_stall_o <= slave_out.stall;
   sl_dat_o   <= slave_out.dat;
   sl_int_o   <= slave_out.int;
-  
+
 
   gen_master_use_struct : if (g_master_use_struct) generate
     master_in <= master_i;
@@ -133,12 +133,6 @@ begin  -- rtl
   end generate gen_master_use_slv;
 
   master_o <= master_out;
-  ma_adr_o <= master_out.adr;
-  ma_dat_o <= master_out.dat;
-  ma_sel_o <= master_out.sel;
-  ma_cyc_o <= master_out.cyc;
-  ma_stb_o <= master_out.stb;
-  ma_we_o  <= master_out.we;
 
   p_gen_address : process(slave_in, master_out)
   begin
diff --git a/hdl/svec/hdl/ip_cores/wishbone/wb_spi/Manifest.py b/hdl/svec/hdl/ip_cores/wishbone/wb_spi/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..8993e24f815d88ff6b6dd8063cfd4d4e76a1161e
--- /dev/null
+++ b/hdl/svec/hdl/ip_cores/wishbone/wb_spi/Manifest.py
@@ -0,0 +1,6 @@
+files = [ "spi_clgen.v",
+ 				  "spi_shift.v",
+				  "spi_top.v",
+				  "wb_spi.vhd",
+				  "xwb_spi.vhd" ];
+
diff --git a/hdl/svec/hdl/ip_cores/wishbone/wishbone_pkg.vhd b/hdl/svec/hdl/ip_cores/wishbone/wishbone_pkg.vhd
index d6774bb9def5af54a0cc4bc41757c8a97dbe7a09..88617070dd621f826da0e964f0eeec87a91ca9ad 100644
--- a/hdl/svec/hdl/ip_cores/wishbone/wishbone_pkg.vhd
+++ b/hdl/svec/hdl/ip_cores/wishbone/wishbone_pkg.vhd
@@ -57,7 +57,7 @@ package wishbone_pkg is
   type t_wishbone_slave_in_array is array (natural range <>) of t_wishbone_slave_in;
 
 
-  constant cc_dummy_address : std_logic_vector(c_wishbone_address_width-1 downto 0) :=
+  constant cc_dummy_address : std_logic_vector(c_wishbone_address_width-1 downto 0):=
     (others => 'X');
   constant cc_dummy_data : std_logic_vector(c_wishbone_address_width-1 downto 0) :=
     (others => 'X');
@@ -66,18 +66,15 @@ package wishbone_pkg is
   constant cc_dummy_slave_in : t_wishbone_slave_in :=
     ('0', 'X', cc_dummy_address, cc_dummy_sel, 'X', cc_dummy_data);
   constant cc_dummy_master_out : t_wishbone_master_out := cc_dummy_slave_in;
-
+  
   -- Dangerous! Will stall a bus.
   constant cc_dummy_slave_out : t_wishbone_slave_out :=
     ('X', 'X', 'X', 'X', 'X', cc_dummy_data);
   constant cc_dummy_master_in : t_wishbone_master_in := cc_dummy_slave_out;
 
-  constant cc_dummy_address_array : t_wishbone_address_array(0 downto 0) := (0 => cc_dummy_address);
-
   -- A generally useful function.
-  function f_ceil_log2(x   : natural) return natural;
+  function f_ceil_log2(x : natural) return natural;
   function f_bits2string(s : std_logic_vector) return string;
-
   function f_string2bits(s : string) return std_logic_vector;
   function f_string2svl (s : string) return std_logic_vector;
   function f_slv2string (slv : std_logic_vector) return string;
@@ -85,36 +82,36 @@ package wishbone_pkg is
 ------------------------------------------------------------------------------
 -- SDB declaration
 ------------------------------------------------------------------------------
-
-  constant c_sdb_device_length : natural := 512;  -- bits
-  subtype  t_sdb_record is std_logic_vector(c_sdb_device_length-1 downto 0);
-  type     t_sdb_record_array is array(natural range <>) of t_sdb_record;
-
+  
+  constant c_sdb_device_length : natural := 512; -- bits
+  subtype t_sdb_record is std_logic_vector(c_sdb_device_length-1 downto 0);
+  type t_sdb_record_array is array(natural range <>) of t_sdb_record;
+  
   type t_sdb_product is record
-    vendor_id : std_logic_vector(63 downto 0);
-    device_id : std_logic_vector(31 downto 0);
-    version   : std_logic_vector(31 downto 0);
-    date      : std_logic_vector(31 downto 0);
-    name      : string(1 to 19);
+    vendor_id     : std_logic_vector(63 downto 0);
+    device_id     : std_logic_vector(31 downto 0);
+    version       : std_logic_vector(31 downto 0);
+    date          : std_logic_vector(31 downto 0);
+    name          : string(1 to 19);
   end record t_sdb_product;
-
+  
   type t_sdb_component is record
-    addr_first : std_logic_vector(63 downto 0);
-    addr_last  : std_logic_vector(63 downto 0);
-    product    : t_sdb_product;
+    addr_first    : std_logic_vector(63 downto 0);
+    addr_last     : std_logic_vector(63 downto 0);
+    product       : t_sdb_product;
   end record t_sdb_component;
-
+  
   constant c_sdb_endian_big    : std_logic := '0';
   constant c_sdb_endian_little : std_logic := '1';
-  type     t_sdb_device is record
+  type t_sdb_device is record
     abi_class     : std_logic_vector(15 downto 0);
     abi_ver_major : std_logic_vector(7 downto 0);
     abi_ver_minor : std_logic_vector(7 downto 0);
-    wbd_endian    : std_logic;          -- 0 = big, 1 = little
-    wbd_width     : std_logic_vector(3 downto 0);  -- 3=64-bit, 2=32-bit, 1=16-bit, 0=8-bit
+    wbd_endian    : std_logic;                    -- 0 = big, 1 = little
+    wbd_width     : std_logic_vector(3 downto 0); -- 3=64-bit, 2=32-bit, 1=16-bit, 0=8-bit
     sdb_component : t_sdb_component;
   end record t_sdb_device;
-
+  
   type t_sdb_bridge is record
     sdb_child     : std_logic_vector(63 downto 0);
     sdb_component : t_sdb_component;
@@ -151,10 +148,10 @@ package wishbone_pkg is
   function f_sdb_extract_synthesis(sdb_record : t_sdb_record) return t_sdb_synthesis;
 
   -- For internal use by the crossbar
-  function f_sdb_embed_product(product         : t_sdb_product) return std_logic_vector;  -- (319 downto 8)
-  function f_sdb_embed_component(sdb_component : t_sdb_component; address : t_wishbone_address) return std_logic_vector;  -- (447 downto 8)
-  function f_sdb_extract_product(sdb_record    : std_logic_vector(319 downto 8)) return t_sdb_product;
-  function f_sdb_extract_component(sdb_record  : std_logic_vector(447 downto 8)) return t_sdb_component;
+  function f_sdb_embed_product(product : t_sdb_product) return std_logic_vector; -- (319 downto 8)
+  function f_sdb_embed_component(sdb_component : t_sdb_component; address : t_wishbone_address) return std_logic_vector; -- (447 downto 8)
+  function f_sdb_extract_product(sdb_record : std_logic_vector(319 downto 8))  return t_sdb_product;
+  function f_sdb_extract_component(sdb_record : std_logic_vector(447 downto 8)) return t_sdb_component;
 
 ------------------------------------------------------------------------------
 -- Components declaration
@@ -271,24 +268,24 @@ package wishbone_pkg is
       g_address     : t_wishbone_address_array;
       g_mask        : t_wishbone_address_array);
     port (
-      clk_sys_i : in  std_logic;
-      rst_n_i   : in  std_logic;
-      slave_i   : in  t_wishbone_slave_in_array(g_num_masters-1 downto 0);
-      slave_o   : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
-      master_i  : in  t_wishbone_master_in_array(g_num_slaves-1 downto 0);
-      master_o  : out t_wishbone_master_out_array(g_num_slaves-1 downto 0));
+      clk_sys_i     : in  std_logic;
+      rst_n_i       : in  std_logic;
+      slave_i       : in  t_wishbone_slave_in_array(g_num_masters-1 downto 0);
+      slave_o       : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
+      master_i      : in  t_wishbone_master_in_array(g_num_slaves-1 downto 0);
+      master_o      : out t_wishbone_master_out_array(g_num_slaves-1 downto 0));
   end component;
 
   -- Use the f_xwb_bridge_*_sdb to bridge a crossbar to another
-  function f_xwb_bridge_manual_sdb(     -- take a manual bus size
-    g_size     : t_wishbone_address;
-    g_sdb_addr : t_wishbone_address) return t_sdb_bridge;
-
-  function f_xwb_bridge_layout_sdb(     -- determine bus size from layout
-    g_wraparound : boolean := true;
-    g_layout     : t_sdb_record_array;
-    g_sdb_addr   : t_wishbone_address) return t_sdb_bridge;
+  function f_xwb_bridge_manual_sdb( -- take a manual bus size
+      g_size        : t_wishbone_address;
+      g_sdb_addr    : t_wishbone_address) return t_sdb_bridge;
 
+  function f_xwb_bridge_layout_sdb( -- determine bus size from layout
+      g_wraparound  : boolean := true;
+      g_layout      : t_sdb_record_array;
+      g_sdb_addr    : t_wishbone_address) return t_sdb_bridge;
+  
   component xwb_sdb_crossbar
     generic (
       g_num_masters : integer;
@@ -298,12 +295,12 @@ package wishbone_pkg is
       g_layout      : t_sdb_record_array;
       g_sdb_addr    : t_wishbone_address);
     port (
-      clk_sys_i : in  std_logic;
-      rst_n_i   : in  std_logic;
-      slave_i   : in  t_wishbone_slave_in_array(g_num_masters-1 downto 0);
-      slave_o   : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
-      master_i  : in  t_wishbone_master_in_array(g_num_slaves-1 downto 0);
-      master_o  : out t_wishbone_master_out_array(g_num_slaves-1 downto 0));
+      clk_sys_i     : in  std_logic;
+      rst_n_i       : in  std_logic;
+      slave_i       : in  t_wishbone_slave_in_array(g_num_masters-1 downto 0);
+      slave_o       : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
+      master_i      : in  t_wishbone_master_in_array(g_num_slaves-1 downto 0);
+      master_o      : out t_wishbone_master_out_array(g_num_slaves-1 downto 0));
   end component;
 
   component sdb_rom is
@@ -311,26 +308,26 @@ package wishbone_pkg is
       g_layout      : t_sdb_record_array;
       g_bus_end     : unsigned(63 downto 0));
     port(
-      clk_sys_i : in  std_logic;
-      slave_i   : in  t_wishbone_slave_in;
-      slave_o   : out t_wishbone_slave_out);
+      clk_sys_i     : in  std_logic;
+      slave_i       : in  t_wishbone_slave_in;
+      slave_o       : out t_wishbone_slave_out);
   end component;
   
   constant c_xwb_dma_sdb : t_sdb_device := (
-    abi_class     => x"0000",              -- undocumented device
+    abi_class     => x"0000", -- undocumented device
     abi_ver_major => x"01",
     abi_ver_minor => x"00",
     wbd_endian    => c_sdb_endian_big,
-    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    wbd_width     => x"7", -- 8/16/32-bit port granularity
     sdb_component => (
-      addr_first  => x"0000000000000000",
-      addr_last   => x"000000000000001f",
-      product     => (
-        vendor_id => x"0000000000000651",  -- GSI
-        device_id => x"cababa56",
-        version   => x"00000001",
-        date      => x"20120518",
-        name      => "WB4-Streaming-DMA_0")));
+    addr_first    => x"0000000000000000",
+    addr_last     => x"000000000000001f",
+    product => (
+    vendor_id     => x"0000000000000651", -- GSI
+    device_id     => x"cababa56",
+    version       => x"00000001",
+    date          => x"20120518",
+    name          => "WB4-Streaming-DMA_0")));
   component xwb_dma is
     generic(
       -- Value 0 cannot stream
@@ -340,7 +337,7 @@ package wishbone_pkg is
       -- Value 4 only slaves with combined latency <= 14 can stream
       -- ....
       logRingLen : integer := 4
-      );
+    );
     port(
       -- Common wishbone signals
       clk_i       : in  std_logic;
@@ -356,9 +353,9 @@ package wishbone_pkg is
       w_master_o  : out t_wishbone_master_out;
       -- Pulsed high completion signal
       interrupt_o : out std_logic
-      );
+    );
   end component;
-
+  
   -- If you reset one clock domain, you must reset BOTH!
   -- Release of the reset lines may be arbitrarily out-of-phase
   component xwb_clock_crossing is
@@ -377,13 +374,17 @@ package wishbone_pkg is
       master_i       : in  t_wishbone_master_in;
       master_o       : out t_wishbone_master_out);
   end component;
-
+  
+  subtype t_xwb_dpram_init is t_generic_ram_init;
+  constant c_xwb_dpram_init_nothing : t_xwb_dpram_init := c_generic_ram_nothing;
+  
   -- g_size is in words
   function f_xwb_dpram(g_size : natural) return t_sdb_device;
   component xwb_dpram
     generic (
       g_size                  : natural;
       g_init_file             : string                         := "";
+      g_init_value            : t_xwb_dpram_init               := c_xwb_dpram_init_nothing;
       g_must_have_init_file   : boolean                        := true;
       g_slave1_interface_mode : t_wishbone_interface_mode      := CLASSIC;
       g_slave2_interface_mode : t_wishbone_interface_mode      := CLASSIC;
@@ -398,24 +399,6 @@ package wishbone_pkg is
       slave2_o  : out t_wishbone_slave_out);
   end component;
 
-
-  constant c_xwb_gpio_port_sdb : t_sdb_device := (
-    abi_class     => x"0000",              -- undocumented device
-    abi_ver_major => x"01",
-    abi_ver_minor => x"01",
-    wbd_endian    => c_sdb_endian_big,
-    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
-    sdb_component => (
-      addr_first  => x"0000000000000000",
-      addr_last   => x"00000000000000ff",
-      product     => (
-        vendor_id => x"000000000000CE42",  -- CERN
-        device_id => x"441c5143",
-        version   => x"00000001",
-        date      => x"20121129",
-        name      => "WB-GPIO-Port       ")));
-
-
   component wb_gpio_port
     generic (
       g_interface_mode         : t_wishbone_interface_mode      := CLASSIC;
@@ -458,23 +441,6 @@ package wishbone_pkg is
       gpio_oen_o : out   std_logic_vector(g_num_pins-1 downto 0));
   end component;
 
-  constant c_xwb_i2c_master_sdb : t_sdb_device := (
-    abi_class     => x"0000",              -- undocumented device
-    abi_ver_major => x"01",
-    abi_ver_minor => x"01",
-    wbd_endian    => c_sdb_endian_big,
-    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
-    sdb_component => (
-      addr_first  => x"0000000000000000",
-      addr_last   => x"00000000000000ff",
-      product     => (
-        vendor_id => x"000000000000CE42",  -- CERN
-        device_id => x"123c5443",
-        version   => x"00000001",
-        date      => x"20121129",
-        name      => "WB-I2C-Master      ")));
-
-
   component wb_i2c_master
     generic (
       g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
@@ -520,8 +486,7 @@ package wishbone_pkg is
 
   component xwb_lm32
     generic (
-      g_profile : string;
-      g_reset_vector : std_logic_vector(31 downto 0) := x"00000000");
+      g_profile : string);
     port (
       clk_sys_i : in  std_logic;
       rst_n_i   : in  std_logic;
@@ -532,22 +497,6 @@ package wishbone_pkg is
       iwb_i     : in  t_wishbone_master_in);
   end component;
 
-  constant c_xwb_onewire_master_sdb : t_sdb_device := (
-    abi_class     => x"0000",              -- undocumented device
-    abi_ver_major => x"01",
-    abi_ver_minor => x"01",
-    wbd_endian    => c_sdb_endian_big,
-    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
-    sdb_component => (
-      addr_first  => x"0000000000000000",
-      addr_last   => x"00000000000000ff",
-      product     => (
-        vendor_id => x"000000000000CE42",  -- CERN
-        device_id => x"779c5443",
-        version   => x"00000001",
-        date      => x"20121129",
-        name      => "WB-OneWire-Master  ")));
-
   component wb_onewire_master
     generic (
       g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
@@ -669,45 +618,6 @@ package wishbone_pkg is
       uart_txd_o : out std_logic);
   end component;
 
-  component wb_simple_pwm
-    generic (
-      g_num_channels        : integer range 1 to 8;
-      g_default_period      : integer range 0 to 255 := 0;
-      g_default_presc       : integer range 0 to 255 := 0;
-      g_default_val         : integer range 0 to 255 := 0;
-      g_interface_mode      : t_wishbone_interface_mode      := PIPELINED;
-      g_address_granularity : t_wishbone_address_granularity := BYTE);
-    port (
-      clk_sys_i  : in  std_logic;
-      rst_n_i    : in  std_logic;
-      wb_adr_i   : in  std_logic_vector(5 downto 0);
-      wb_dat_i   : in  std_logic_vector(31 downto 0);
-      wb_dat_o   : out std_logic_vector(31 downto 0);
-      wb_cyc_i   : in  std_logic;
-      wb_sel_i   : in  std_logic_vector(3 downto 0);
-      wb_stb_i   : in  std_logic;
-      wb_we_i    : in  std_logic;
-      wb_ack_o   : out std_logic;
-      wb_stall_o : out std_logic;
-      pwm_o      : out std_logic_vector(g_num_channels-1 downto 0));
-  end component;
-
-  component xwb_simple_pwm
-    generic (
-      g_num_channels        : integer range 1 to 8;
-      g_default_period      : integer range 0 to 255 := 0;
-      g_default_presc       : integer range 0 to 255 := 0;
-      g_default_val         : integer range 0 to 255 := 0;
-      g_interface_mode      : t_wishbone_interface_mode      := PIPELINED;
-      g_address_granularity : t_wishbone_address_granularity := BYTE);
-    port (
-      clk_sys_i : in  std_logic;
-      rst_n_i   : in  std_logic;
-      slave_i   : in  t_wishbone_slave_in;
-      slave_o   : out t_wishbone_slave_out;
-      pwm_o     : out std_logic_vector(g_num_channels-1 downto 0));
-  end component;
-
   component wb_tics
     generic (
       g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
@@ -744,9 +654,7 @@ package wishbone_pkg is
     generic (
       g_interface_mode      : t_wishbone_interface_mode;
       g_address_granularity : t_wishbone_address_granularity;
-      g_num_interrupts      : natural;
-      g_init_vectors        : t_wishbone_address_array := cc_dummy_address_array
-      );
+      g_num_interrupts      : natural);
     port (
       clk_sys_i    : in  std_logic;
       rst_n_i      : in  std_logic;
@@ -763,28 +671,11 @@ package wishbone_pkg is
       irq_master_o : out std_logic);
   end component;
 
-  constant c_xwb_vic_sdb : t_sdb_device := (
-    abi_class     => x"0000",              -- undocumented device
-    abi_ver_major => x"01",
-    abi_ver_minor => x"01",
-    wbd_endian    => c_sdb_endian_big,
-    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
-    sdb_component => (
-      addr_first  => x"0000000000000000",
-      addr_last   => x"00000000000000ff",
-      product     => (
-        vendor_id => x"000000000000CE42",  -- CERN
-        device_id => x"00000013",
-        version   => x"00000002",
-        date      => x"20120113",
-        name      => "WB-VIC-Int.Control ")));   
-
   component xwb_vic
     generic (
       g_interface_mode      : t_wishbone_interface_mode;
       g_address_granularity : t_wishbone_address_granularity;
-      g_num_interrupts      : natural;
-      g_init_vectors        : t_wishbone_address_array := cc_dummy_address_array);
+      g_num_interrupts      : natural);
     port (
       clk_sys_i    : in  std_logic;
       rst_n_i      : in  std_logic;
@@ -837,9 +728,9 @@ package body wishbone_pkg is
     else return f_ceil_log2((x+1)/2) +1;
     end if;
   end f_ceil_log2;
-
+  
   function f_sdb_embed_product(product : t_sdb_product)
-    return std_logic_vector             -- (319 downto 8)
+    return std_logic_vector -- (319 downto 8)
   is
     variable result : std_logic_vector(319 downto 8);
   begin
@@ -847,13 +738,13 @@ package body wishbone_pkg is
     result(255 downto 224) := product.device_id;
     result(223 downto 192) := product.version;
     result(191 downto 160) := product.date;
-    for i in 0 to 18 loop               -- string to ascii
-      result(159-i*8 downto 152-i*8) :=
+    for i in 0 to 18 loop -- string to ascii
+      result(159-i*8 downto 152-i*8) := 
         std_logic_vector(to_unsigned(character'pos(product.name(i+1)), 8));
     end loop;
     return result;
   end;
-
+  
   function f_sdb_extract_product(sdb_record : std_logic_vector(319 downto 8))
     return t_sdb_product
   is
@@ -863,29 +754,29 @@ package body wishbone_pkg is
     result.device_id := sdb_record(255 downto 224);
     result.version   := sdb_record(223 downto 192);
     result.date      := sdb_record(191 downto 160);
-    for i in 0 to 18 loop               -- ascii to string
+    for i in 0 to 18 loop -- ascii to string
       result.name(i+1) := character'val(to_integer(unsigned(sdb_record(159-i*8 downto 152-i*8))));
     end loop;
     return result;
   end;
-
+  
   function f_sdb_embed_component(sdb_component : t_sdb_component; address : t_wishbone_address)
-    return std_logic_vector             -- (447 downto 8)
+    return std_logic_vector -- (447 downto 8)
   is
     variable result : std_logic_vector(447 downto 8);
-
+    
     constant first : unsigned(63 downto 0) := unsigned(sdb_component.addr_first);
     constant last  : unsigned(63 downto 0) := unsigned(sdb_component.addr_last);
     variable base  : unsigned(63 downto 0) := (others => '0');
   begin
     base(address'length-1 downto 0) := unsigned(address);
-
+    
     result(447 downto 384) := std_logic_vector(base);
     result(383 downto 320) := std_logic_vector(base + last - first);
-    result(319 downto 8)   := f_sdb_embed_product(sdb_component.product);
+    result(319 downto   8) := f_sdb_embed_product(sdb_component.product);
     return result;
   end;
-
+  
   function f_sdb_extract_component(sdb_record : std_logic_vector(447 downto 8))
     return t_sdb_component
   is
@@ -896,7 +787,7 @@ package body wishbone_pkg is
     result.product    := f_sdb_extract_product(sdb_record(319 downto 8));
     return result;
   end;
-
+  
   function f_sdb_embed_device(device : t_sdb_device; address : t_wishbone_address)
     return t_sdb_record
   is
@@ -908,11 +799,11 @@ package body wishbone_pkg is
     result(479 downto 453) := (others => '0');
     result(452)            := device.wbd_endian;
     result(451 downto 448) := device.wbd_width;
-    result(447 downto 8)   := f_sdb_embed_component(device.sdb_component, address);
-    result(7 downto 0)     := x"01";    -- device
+    result(447 downto   8) := f_sdb_embed_component(device.sdb_component, address);
+    result(  7 downto   0) := x"01"; -- device
     return result;
   end;
-
+  
   function f_sdb_extract_device(sdb_record : t_sdb_record)
     return t_sdb_device
   is
@@ -924,10 +815,10 @@ package body wishbone_pkg is
     result.wbd_endian    := sdb_record(452);
     result.wbd_width     := sdb_record(451 downto 448);
     result.sdb_component := f_sdb_extract_component(sdb_record(447 downto 8));
-
+    
     assert sdb_record(7 downto 0) = x"01"
-      report "Cannot extract t_sdb_device from record of type " & integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
-      severity failure;
+    report "Cannot extract t_sdb_device from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
+    severity Failure;
     
     return result;
   end;
@@ -1019,20 +910,20 @@ package body wishbone_pkg is
     return t_sdb_record
   is
     variable result : t_sdb_record;
-
+    
     constant first : unsigned(63 downto 0) := unsigned(bridge.sdb_component.addr_first);
     constant child : unsigned(63 downto 0) := unsigned(bridge.sdb_child);
     variable base  : unsigned(63 downto 0) := (others => '0');
   begin
     base(address'length-1 downto 0) := unsigned(address);
-
+    
     result(511 downto 448) := std_logic_vector(base + child - first);
-    result(447 downto 8)   := f_sdb_embed_component(bridge.sdb_component, address);
-    result(7 downto 0)     := x"02";    -- bridge
+    result(447 downto   8) := f_sdb_embed_component(bridge.sdb_component, address);
+    result(  7 downto   0) := x"02"; -- bridge
     return result;
   end;
-
-  function f_sdb_extract_bridge(sdb_record : t_sdb_record)
+  
+  function f_sdb_extract_bridge(sdb_record : t_sdb_record) 
     return t_sdb_bridge
   is
     variable result : t_sdb_bridge;
@@ -1041,45 +932,45 @@ package body wishbone_pkg is
     result.sdb_component := f_sdb_extract_component(sdb_record(447 downto 8));
 
     assert sdb_record(7 downto 0) = x"02"
-      report "Cannot extract t_sdb_bridge from record of type " & integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
-      severity failure;
+    report "Cannot extract t_sdb_bridge from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
+    severity Failure;
     
     return result;
   end;
   
   function f_xwb_bridge_manual_sdb(
-    g_size     : t_wishbone_address;
-    g_sdb_addr : t_wishbone_address) return t_sdb_bridge
+    g_size       : t_wishbone_address;
+    g_sdb_addr   : t_wishbone_address) return t_sdb_bridge
   is
     variable result : t_sdb_bridge;
   begin
-    result.sdb_child                                      := (others => '0');
+    result.sdb_child := (others => '0');
     result.sdb_child(c_wishbone_address_width-1 downto 0) := g_sdb_addr;
-
-    result.sdb_component.addr_first                                     := (others => '0');
-    result.sdb_component.addr_last                                      := (others => '0');
+    
+    result.sdb_component.addr_first := (others => '0');
+    result.sdb_component.addr_last  := (others => '0');
     result.sdb_component.addr_last(c_wishbone_address_width-1 downto 0) := g_size;
-
-    result.sdb_component.product.vendor_id := x"0000000000000651";  -- GSI
+    
+    result.sdb_component.product.vendor_id := x"0000000000000651"; -- GSI
     result.sdb_component.product.device_id := x"eef0b198";
     result.sdb_component.product.version   := x"00000001";
     result.sdb_component.product.date      := x"20120511";
     result.sdb_component.product.name      := "WB4-Bridge-GSI     ";
-
+    
     return result;
   end f_xwb_bridge_manual_sdb;
   
   function f_xwb_bridge_layout_sdb(
-    g_wraparound : boolean := true;
-    g_layout     : t_sdb_record_array;
-    g_sdb_addr   : t_wishbone_address) return t_sdb_bridge
+    g_wraparound  : boolean := true;
+    g_layout      : t_sdb_record_array;
+    g_sdb_addr    : t_wishbone_address) return t_sdb_bridge
   is
     alias c_layout : t_sdb_record_array(g_layout'length-1 downto 0) is g_layout;
 
     -- How much space does the ROM need?
     constant c_used_entries : natural := c_layout'length + 1;
-    constant c_rom_entries  : natural := 2**f_ceil_log2(c_used_entries);  -- next power of 2
-    constant c_sdb_bytes    : natural := c_sdb_device_length / 8;
+    constant c_rom_entries  : natural := 2**f_ceil_log2(c_used_entries); -- next power of 2
+    constant c_sdb_bytes   : natural := c_sdb_device_length / 8;
     constant c_rom_bytes    : natural := c_rom_entries * c_sdb_bytes;
     
     variable result : unsigned(63 downto 0);
@@ -1110,29 +1001,29 @@ package body wishbone_pkg is
     
     return f_xwb_bridge_manual_sdb(std_logic_vector(result(c_wishbone_address_width-1 downto 0)), g_sdb_addr);
   end f_xwb_bridge_layout_sdb;
-
+  
   function f_xwb_dpram(g_size : natural) return t_sdb_device
   is
     variable result : t_sdb_device;
   begin
-    result.abi_class     := x"0001";    -- RAM device
+    result.abi_class     := x"0001"; -- RAM device
     result.abi_ver_major := x"01";
     result.abi_ver_minor := x"00";
-    result.wbd_width     := x"7";       -- 32/16/8-bit supported
+    result.wbd_width     := x"7"; -- 32/16/8-bit supported
     result.wbd_endian    := c_sdb_endian_big;
-
+    
     result.sdb_component.addr_first := (others => '0');
     result.sdb_component.addr_last  := std_logic_vector(to_unsigned(g_size*4-1, 64));
-
-    result.sdb_component.product.vendor_id := x"000000000000CE42";  -- CERN
+    
+    result.sdb_component.product.vendor_id := x"000000000000CE42"; -- CERN
     result.sdb_component.product.device_id := x"66cfeb52";
     result.sdb_component.product.version   := x"00000001";
     result.sdb_component.product.date      := x"20120305";
     result.sdb_component.product.name      := "WB4-BlockRAM       ";
-
+    
     return result;
   end f_xwb_dpram;
-
+  
   function f_bits2string(s : std_logic_vector) return string is
     --- extend length to full hex nibble
     variable result : string((s'length+7)/4 downto 1);
@@ -1163,13 +1054,13 @@ package body wishbone_pkg is
         when others => result(i+1) := 'X';
       end case;
     end loop;
-
+    
     -- trim leading 0s
     strip : for i in result'length downto 1 loop
       cut := i;
       exit strip when result(i) /= '0';
     end loop;
-
+    
     return "0x" & result(cut downto 1);
   end f_bits2string;
 
diff --git a/hdl/svec/hdl/rtl/acam_databus_interface.vhd b/hdl/svec/hdl/rtl/acam_databus_interface.vhd
index a6e9e106fe95723db8705b7ed70e82225aa93e17..5396e8eada4305293d6124aa07237c246e6d106b 100644
--- a/hdl/svec/hdl/rtl/acam_databus_interface.vhd
+++ b/hdl/svec/hdl/rtl/acam_databus_interface.vhd
@@ -14,8 +14,8 @@
 --                                                                                                |
 -- Description  The unit interfaces with the ACAM chip pins for the configuration of the registers|
 --              and the aquisition of the timestamps.                                             |
---              The ACAM proprietary interface is converted to a WISHBONE classic interface,      |
---              through which the unit communicates with the data_engine unit.                    |
+--              The ACAM proprietary interface is converted to a WISHBONE classic interface, with |
+--              which the unit communicates with the data_engine unit.                            |
 --              The WISHBONE master is implemented in the data_engine and the slave in this unit. |
 --                                                                                                |
 --              ___________               ____________              ___________                   |
@@ -78,13 +78,13 @@ entity acam_databus_interface is
   port
 
   -- INPUTS
-     -- Signals from the clks_rsts_manager unit
+     -- Signals from the clk_rst_manager unit
     (clk_i        : in std_logic; -- 125 MHz clock
-     rst_i        : in std_logic; -- global reset, synched to clk_i
+     rst_i        : in std_logic; -- global reset
 
      -- Signals from the ACAM chip
      ef1_i        : in std_logic; -- FIFO1 empty flag
-     ef2_i        : in std_logic; -- FIFO2 empty flag
+     ef2_i        : in std_logic; -- FIFO1 empty flag
 
      data_bus_io   : inout std_logic_vector(27 downto 0);
 
@@ -92,27 +92,27 @@ entity acam_databus_interface is
      cyc_i        : in std_logic; -- WISHBONE cycle
      stb_i        : in std_logic; -- WISHBONE strobe
      we_i         : in std_logic; -- WISHBONE write enable
-     adr_i        : in std_logic_vector(7 downto 0);  -- address of ACAM to write to/ read from (only 4 LSB are output)
-     dat_i        : in std_logic_vector(31 downto 0); -- data to load to ACAM (only 28 LSB are output)
+     adr_i        : in std_logic_vector(7 downto 0);  -- address of Acam to write to/ read from (only 4 LSB are output)
+     dat_i        : in std_logic_vector(31 downto 0); -- data to load to Acam (only 28 LSB are output)
 
 
   -- OUTPUTS
      -- signals internal to the chip: interface with other modules
-     ef1_o        : out std_logic; -- ACAM FIFO1 empty flag (bouble registered with clk_i)
-     ef1_synch1_o : out std_logic; -- ACAM FIFO1 empty flag (after 1 clk_i register)
-     ef2_o        : out std_logic; -- ACAM FIFO2 empty flag (bouble registered with clk_i)
-     ef2_synch1_o : out std_logic; -- ACAM FIFO2 empty flag (after 1 clk_i register)
+     ef1_o        : out std_logic; -- acam FIFO1 empty flag (bouble registered with clk_i)
+     ef1_synch1_o : out std_logic; -- acam FIFO1 empty flag (after 1 clk_i register)
+     ef2_o        : out std_logic; -- acam FIFO2 empty flag (bouble registered with clk_i)
+     ef2_synch1_o : out std_logic; -- acam FIFO2 empty flag (after 1 clk_i register)
 
      -- Signals to ACAM interface
-     adr_o        : out std_logic_vector(3 downto 0);   -- ACAM address
-     cs_n_o       : out std_logic;                      -- ACAM chip select, active low
-     oe_n_o       : out std_logic;                      -- ACAM output enble, active low
-     rd_n_o       : out std_logic;                      -- ACAM read enable, active low
-     wr_n_o       : out std_logic;                      -- ACAM write enable, active low
+     adr_o        : out std_logic_vector(3 downto 0);   -- acam address
+     cs_n_o       : out std_logic;                      -- acam chip select, active low
+     oe_n_o       : out std_logic;                      -- acam output enble, active low
+     rd_n_o       : out std_logic;                      -- acam read enable, active low
+     wr_n_o       : out std_logic;                      -- acam write enable, active low
 
      -- Signals to the data_engine unit
      ack_o        : out std_logic;                      -- WISHBONE ack 
-     dat_o        : out std_logic_vector(31 downto 0)); -- ef1 & ef2 & 0 & 0 & 28 bits ACAM data_bus_io
+     dat_o        : out std_logic_vector(31 downto 0)); -- ef1 & ef2 & 0 & 0 & 28 bits acam data_bus_io
 
 end acam_databus_interface;
 
@@ -320,7 +320,7 @@ output_registers: process (clk_i)
   cs           <= ((stb_i and cyc_i)               or cs_extend) and not(ack);
   rd           <= ((stb_i and cyc_i and not(we_i)) or rd_extend) and not(ack);
   wr           <= ((stb_i and cyc_i and we_i)      or wr_extend) and not(wr_remove) and not(ack); 
-               -- the wr signal has to be removed to respect the ACAM specs
+               -- the wr signal has to be removed to respect the Acam specs
   data_bus_io  <= dat_i(27 downto 0) when we_i='1' else (others =>'Z');
   adr_o        <= adr_i(3 downto 0);
 
diff --git a/hdl/svec/hdl/rtl/acam_timecontrol_interface.vhd b/hdl/svec/hdl/rtl/acam_timecontrol_interface.vhd
index b2e951e74b8c6b9b432dee03d87d381a294d83c1..51d87d7ebbba338f681fea5f08746b3296f28b81 100644
--- a/hdl/svec/hdl/rtl/acam_timecontrol_interface.vhd
+++ b/hdl/svec/hdl/rtl/acam_timecontrol_interface.vhd
@@ -12,30 +12,7 @@
 ---------------------------------------------------------------------------------------------------
 -- File         acam_timecontrol_interface.vhd                                                    |
 --                                                                                                |
--- Description  Interface with the ACAM chip pins for the timing issues.                          |
---              o The unit is responsible for delivering to the ACAM, the Start pulse, upon the   |
---                activation-of-the-aquisition command (activate_acq_p_i) coming through the      |
---                Control Register bit 0, from the PCIe/VME interface.                            |
---                All ACAM timestamps will be referring to this Start pulse (a timestamp is the   |
---                time difference between this pulse and a pulse arriving to any of the channels).|
---                Since though in this application we are only interested in calculating timestamp|
---                differences, the exact arrival of this Start pulse is not actually significant. |
---                Note that the timestamps subtraction takes place on the software level of this  | 
---                TDC application.                                                                |
---                Start       :  ______|-|_______________________________________________________ |
---                Stop Ch1    :  _______________|-|______________________________________________ |
---                Stop Ch2    :  _________________________________|-|____________________________ |
---                ACAM tstamp1:        <-------->                                                 |
---                ACAM tstamp2:        <------------------------->                                |
---                Tstamps diff:                 <---------------->
---              o The unit is also receiving the ACAM signal int_flag_i, which is following       |
---                the ACAM Start# MSB (configuration set through the ACAM register 12);           |
---                it makes it synchronous to the clk_i and makes it availabe to the               |
---                start_retrig_ctrl unit.                                                         |
---              o Finally, the unit is receiving the the ACAM signal err_flag_i, which is         |
---                following the ACAM Full Flags of the Hit FIFOs(configuration set through the    |
---                ACAM register 11); it detects a rising edge and makes it available to the       |
---                irq_generator unit.                                                             |
+-- Description  interface with the acam chip pins for control and timing                          |
 --                                                                                                |
 --                                                                                                |
 -- Authors      Gonzalo Penacoba  (Gonzalo.Penacoba@cern.ch)                                      |
@@ -85,31 +62,28 @@ use work.tdc_core_pkg.all;   -- definitions of types, constants, entities
 entity acam_timecontrol_interface is
   port
   -- INPUTS
-    -- Signals from the clks_rsts_manager unit
-    (clk_i                   : in std_logic;  -- 125 MHz clock
-     rst_i                   : in std_logic;  -- global reset, synched to clk_i
-     acam_refclk_r_edge_p_i  : in std_logic;  -- pulse upon ACAM RefClk rising edge
+    -- Signals from the clk_rst_manager unit
+    (clk_i                   : in std_logic; -- 125 MHz clock
+     rst_i                   : in std_logic; -- reset
+     acam_refclk_r_edge_p_i  : in std_logic; -- pulse upon ACAM RefClk rising edge
 
     -- Signals from the ACAM chip
-     int_flag_i              : in std_logic;  -- ACAM interrupt flag, active HIGH; through ACAM config
-                                              -- reg 12 it is set to the MSB of Start#
-     err_flag_i              : in std_logic;  -- ACAM error flag, active HIGH; through ACAM config
-                                              -- reg 11 is set to report for any HitFIFOs full flags
+     err_flag_i              : in std_logic; -- ACAM error flag, active HIGH; through ACAM config
+                                             -- reg 11 is set to report for any HitFIFOs full flags
+     int_flag_i              : in std_logic; -- ACAM interrupt flag, active HIGH; through ACAM config
+                                             -- reg 12 it is set to the MSB of Start#
 
     -- Signals from the reg_ctrl unit
-     activate_acq_p_i        : in std_logic;  -- signal from PCIe/VME to send the Start pulse 
-                                              -- and to start retrieving the ACAM timestamps
-     window_delay_i          : in std_logic_vector(31 downto 0); -- eva: think not used
+     activate_acq_p_i        : in std_logic; -- signal from PCIe to start following the ACAM chip
+                                             -- for tstamps aquisition
+     window_delay_i          : in std_logic_vector(31 downto 0); -- eva: don t know yet:s
 
 
   -- OUTPUTS
     -- Signals to the ACAM chip
-     start_from_fpga_o       : out std_logic; -- Start pulse, to which all timestamps will be refering to;
-                                              -- note though that in this application we are only interested
-                                              -- in time differences, therefore the exact arrival of this 
-                                              -- pulse is not significant.
+     start_from_fpga_o       : out std_logic;
 
-    -- Signals to the start_retrig_ctrl unit
+    -- Signals to the 
      acam_errflag_r_edge_p_o : out std_logic; -- ACAM ErrFlag rising edge
      acam_errflag_f_edge_p_o : out std_logic; -- ACAM ErrFlag falling edge
      acam_intflag_f_edge_p_o : out std_logic);-- ACAM IntFlag falling edge
@@ -168,9 +142,8 @@ begin
   acam_intflag_f_edge_p_o   <= not(int_flag_synch(1)) and int_flag_synch(0);
 
 
-
 ---------------------------------------------------------------------------------------------------
---                                     Start Pulse Generation                                    --
+--                                      Input Synchronizers                                      --
 ---------------------------------------------------------------------------------------------------   
 -- Generation of the start pulse and the enable window:
 -- the start pulse originates from an internal signal at the same time, the StartDis is de-asserted.
@@ -209,8 +182,8 @@ begin
   total_delay          <= std_logic_vector(unsigned(window_delay_i)+constant_delay);
 
     
-  start_pulse_from_fpga: process (clk_i)             -- start pulse in the middle of the
-  begin                                              -- de-assertion window of StartDisable
+  start_pulse_from_fpga: process (clk_i)                  -- start pulse in the middle of the
+  begin                                                   -- de-assertion window of StartDisable
     if rising_edge (clk_i) then
       if rst_i ='1' then
         start_from_fpga_o <= '0';
@@ -225,6 +198,7 @@ begin
   end process;
 
 
+
   -- Synchronization of the activate_acq_p with the acam_refclk_p_i
   ready_to_trigger: process (clk_i)
   begin
@@ -244,8 +218,8 @@ begin
 
 
 
-  actual_trigger_received: process (clk_i)           -- signal needed to exclude the generation of
-  begin                                              -- the start_from_fpga_o after a general rst_i
+  actual_trigger_received: process (clk_i)        -- signal needed to exclude the generation of
+  begin                                           -- the start_from_fpga_o after a general rst_i
     if rising_edge (clk_i) then
       if rst_i ='1' then  
         start_trig_received <= '0';
diff --git a/hdl/svec/hdl/rtl/circular_buffer.vhd b/hdl/svec/hdl/rtl/circular_buffer.vhd
index fa2a0a0d19834591f5d5ee1e013ba67a3ca3c63c..783003a5e0b49636d03b1701ffec2cb368009734 100644
--- a/hdl/svec/hdl/rtl/circular_buffer.vhd
+++ b/hdl/svec/hdl/rtl/circular_buffer.vhd
@@ -17,17 +17,17 @@
 --               o The data_formatting unit is writing 128-bit long timestamps, using a WISHBONE  |
 --                 classic interface. The unit implements a WISHBONE classic slave.               |
 --                 As figure 1 indicates, from this side the memory is of size: 255 * 128.        |
---               o The PCIe/VME core is reading 32-bit words. Readings take place using a         |
---                 pipelined WISHBONE interface; the unit implements a WISHBONE pipelined slave   |
---                 on the reading side. As figure 1 indicates, from this side the memory is of    |
---                 size: 1024 * 32.                                                               |
+--               o The GNUM core is reading 32-bit words. Readings take place using a pipelined   |
+--                 WISHBONE interface, allowing for Direct Memory Access from the PCI-e.          |
+--                 The unit implements a WISHBONE pipelined slave.                                |
+--                 As figure 1 indicates, from this side the memory is of size: 1024 * 32.        |
 --                                                                                                |
 --              Note also that in principle the data_formatting unit is only writing in the RAM   |
---              and the GNUM/VME_core is only reading from it.                                    |
+--              and the GNUM core is only reading from it.                                        |
 --                                                                                                |
 --                                                                                                |
 --                         RAM as seen from the                             RAM as seen from the  |
---                         data_formatting unit                                GNUM/VME_core      |
+--                         data_formatting unit                                   GNUM core       |
 --     ____________________________________________________________            _______________    |
 --  0 |                          128 bits                          |        0 |    32 bits    |   |
 --    |____________________________________________________________|          |_______________|   |
@@ -104,8 +104,8 @@ use work.tdc_core_pkg.all;   -- definitions of types, constants, entities
 entity circular_buffer is
   port
   -- INPUTS
-     -- Signal from the clks_rsts_manager
-    (clk_i             : in std_logic; -- 125 MHz clock; same for both ports
+     -- Signal from the clk_rst_manager
+    (clk_i                : in std_logic; -- 125 MHz clock; same for both ports
 
      -- Signals from the data_formatting unit (WISHBONE classic): timestamps writing
      tstamp_wr_rst_i   : in std_logic; -- timestamp writing WISHBONE reset
@@ -115,24 +115,23 @@ entity circular_buffer is
      tstamp_wr_adr_i   : in std_logic_vector(7 downto 0);   -- adr 8 bits long 2^8 = 255
      tstamp_wr_dat_i   : in std_logic_vector(127 downto 0); -- timestamp 128 bits long
 
-     -- Signals from the GNUM/VME_core unit (WISHBONE pipelined): timestamps reading
-     tdc_mem_wb_rst_i  : in std_logic; -- timestamp reading WISHBONE reset
-     tdc_mem_wb_stb_i  : in std_logic; -- timestamp reading WISHBONE strobe
-     tdc_mem_wb_cyc_i  : in std_logic; -- timestamp reading WISHBONE cycle
-     tdc_mem_wb_we_i   : in std_logic; -- timestamp reading WISHBONE write enable; not used
-     tdc_mem_wb_adr_i  : in std_logic_vector(31 downto 0);  -- adr 10 bits long 2^10 = 1024
-     tdc_mem_wb_dat_i  : in std_logic_vector(31 downto 0);  -- not used
-
+     -- Signals from the GNUM core unit (WISHBONE pipelined): timestamps reading
+     tdc_mem_wb_rst_i    : in std_logic; -- timestamp reading WISHBONE reset
+     tdc_mem_wb_stb_i    : in std_logic; -- timestamp reading WISHBONE strobe
+     tdc_mem_wb_cyc_i    : in std_logic; -- timestamp reading WISHBONE cycle
+     tdc_mem_wb_we_i     : in std_logic; -- timestamp reading WISHBONE write enable; not used
+     tdc_mem_wb_adr_i    : in std_logic_vector(31 downto 0);  -- adr 10 bits long 2^10 = 1024
+     tdc_mem_wb_dat_i    : in std_logic_vector(31 downto 0);  -- not used
 
   -- OUTPUTS
      -- Signals to the data_formatting unit (WISHBONE classic): timestamps writing
      tstamp_wr_ack_p_o : out std_logic; -- timestamp writing WISHBONE classic acknowledge
      tstamp_wr_dat_o   : out std_logic_vector(127 downto 0); -- not used
 
-     -- Signals to the CNUM/VME core unit (WISHBONE pipelined): timestamps reading
-     tdc_mem_wb_ack_o  : out std_logic; -- timestamp reading WISHBONE pepelined acknowledge
-     tdc_mem_wb_dat_o  : out std_logic_vector(31 downto 0); -- 32 bit words
-     tdc_mem_wb_stall_o: out std_logic);-- timestamp reading WISHBONE pipelined stall
+     -- Signals to the GNUM core unit (WISHBONE pipelined): timestamps reading
+     tdc_mem_wb_ack_o     : out std_logic; -- timestamp reading WISHBONE pepelined acknowledge
+     tdc_mem_wb_dat_o     : out std_logic_vector(31 downto 0); -- 32 bit words
+     tdc_mem_wb_stall_o   : out std_logic);-- timestamp reading WISHBONE pipelined stall
 
 end circular_buffer;
 
@@ -160,7 +159,7 @@ begin
   begin
     if rising_edge (clk_i) then
       if tstamp_wr_rst_i ='1' then
-        tstamp_wr_ack_p <= '0';
+        --tstamp_wr_ack_p <= '0';
 
       elsif tstamp_wr_stb_i = '1' and tstamp_wr_cyc_i = '1' and tstamp_wr_ack_p = '0' then
         tstamp_wr_ack_p <= '1';                    -- a new 1 clk-wide ack is given for each stb
@@ -271,58 +270,6 @@ begin
   tdc_mem_wb_stall_o <= '0';
 
 
-
----------------------------------------------------------------------------------------------------
---                                             Dummy 0                                           --
----------------------------------------------------------------------------------------------------
---Note: c_WB_SLAVE_DUMMY = 0
---  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  -- dummy0_ack_generator: process (clk_125m_i)
-  -- begin
-    -- if rising_edge (clk_125m_i) then
-      -- if general_rst_n = '0' then
-        -- cnx_master_in(c_WB_SLAVE_DUMMY).ack <= '0';
-      -- else
-        -- cnx_master_in(c_WB_SLAVE_DUMMY).ack <= cnx_master_out(c_WB_SLAVE_DUMMY).stb and cnx_master_out(c_WB_SLAVE_DUMMY).cyc;
-      -- end if;
-    -- end if;
-  -- end process;
-
- --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  -- dummy0: process (clk_125m_i)
-  -- begin
-    -- if rising_edge (clk_125m_i) then
-      -- if general_rst_n = '0' then
-        -- dummy_reg_1 <= x"F000000D";
-
-      -- elsif cnx_master_out(c_WB_SLAVE_DUMMY).cyc = '1' and cnx_master_out(c_WB_SLAVE_DUMMY).stb = '1' and cnx_master_out(c_WB_SLAVE_DUMMY).we = '1' then
-
-        -- if dummy_core_wb_adr(7 downto 0) = x"00" then
-          -- dummy_reg_1 <= cnx_master_out(c_WB_SLAVE_DUMMY).dat;
-        -- end if;
-
-      -- elsif cnx_master_out(c_WB_SLAVE_DUMMY).cyc = '1' and cnx_master_out(c_WB_SLAVE_DUMMY).stb = '1' and cnx_master_out(c_WB_SLAVE_DUMMY).we = '0' then
-
-        -- if dummy_core_wb_adr(7 downto 0)  = x"00" then
-          -- cnx_master_in(c_WB_SLAVE_DUMMY).dat <= dummy_reg_1;
-        -- elsif dummy_core_wb_adr(7 downto 0)  = x"01" then
-          -- cnx_master_in(c_WB_SLAVE_DUMMY).dat <= wb_tdc_mezz_adr_i;
-        -- else
-          -- cnx_master_in(c_WB_SLAVE_DUMMY).dat <= dummy_core_wb_adr;
-        -- end if;
-
-      -- end if;
-    -- end if;
-  -- end process;
-
-  -- dummy_core_wb_adr                     <= cnx_master_out(c_WB_SLAVE_DUMMY).adr;
-  -- cnx_master_in(c_WB_SLAVE_DUMMY).err   <= '0';
-  -- cnx_master_in(c_WB_SLAVE_DUMMY).rty   <= '0';
-  -- cnx_master_in(c_WB_SLAVE_DUMMY).stall <= '0';
-  -- cnx_master_in(c_WB_SLAVE_DUMMY).int   <= '0';
-
-
-
 ---------------------------------------------------------------------------------------------------
 --                                      DUAL PORT BLOCK RAM                                      --
 ---------------------------------------------------------------------------------------------------
@@ -338,12 +285,12 @@ begin
 
     -- Port B: attached to the GNUM/VME_core unit
     clkb   => clk_i,
-    addrb  => tdc_mem_wb_adr_i(9 downto 0),-- 2^10 = 1024 addresses
-    dinb   => tdc_mem_wb_dat_i,            -- not used
+    addrb  => tdc_mem_wb_adr_i(9 downto 0),  -- 2^10 = 1024 addresses
+    dinb   => tdc_mem_wb_dat_i,              -- not used
     enb    => tdc_mem_wb_cyc_i,
-    web    => tstamp_rd_we,
+    web    => tstamp_rd_we,                  -- not used
    --------------------------------------------------
-    doutb  => tdc_mem_wb_dat_o);           -- 32-bit long words
+    doutb  => tdc_mem_wb_dat_o);             -- 32-bit long words
    --------------------------------------------------
 
     tstamp_wr_we(0) <= tstamp_wr_we_i;
@@ -351,11 +298,22 @@ begin
 
 
 
+---------------------------------------------------------------------------------------------------
+--                                          Dummy reading                                        --
+---------------------------------------------------------------------------------------------------
 
-
-
-
-
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+  -- dummy0_ack_generator: process (clk_i)
+  -- begin
+    -- if rising_edge (clk_i) then
+      -- if tdc_mem_wb_rst_i ='1' then
+        -- tdc_mem_wb_ack_o <= '0';
+      -- else
+        -- tdc_mem_wb_ack_o <= tdc_mem_wb_stb_i and tdc_mem_wb_cyc_i;
+      -- end if;
+    -- end if;
+  -- end process;
+  -- tdc_mem_wb_stall_o <= '0';
 
 
 
diff --git a/hdl/svec/hdl/rtl/data_formatting.vhd b/hdl/svec/hdl/rtl/data_formatting.vhd
index 551dbde2e408b7c088a95b5ca82a5f9198a69463..a1aa79b7c2838ee8e50ff8d0855f736967de028c 100644
--- a/hdl/svec/hdl/rtl/data_formatting.vhd
+++ b/hdl/svec/hdl/rtl/data_formatting.vhd
@@ -19,8 +19,8 @@
 --                                                                                                |
 -- Authors      Gonzalo Penacoba  (Gonzalo.Penacoba@cern.ch)                                      |
 --              Evangelia Gousiou (Evangelia.Gousiou@cern.ch)                                     |
--- Date         04/2012                                                                           |
--- Version      v1                                                                                |
+-- Date         07/2013                                                                           |
+-- Version      v2                                                                                |
 -- Depends on                                                                                     |
 --                                                                                                |
 ----------------                                                                                  |
@@ -29,6 +29,8 @@
 --     04/2012  v0.11 EG  Revamping; Comments added, signals renamed                              |
 --     04/2013  v1    EG  Fixed bug when timestamop comes on the first retrigger after a new      |
 --                        second; fixed bug on rollover that is a bit delayed wrt Acam IrFlag     |
+--     07/2013  v2    EG  Cleaner writing with adition of intermediate DFF on the acam_tstamp     |
+--                        calculations                                                            |
 --                                                                                                |
 ---------------------------------------------------------------------------------------------------
 
@@ -98,6 +100,8 @@ entity data_formatting is
 
 
   -- OUTPUTS
+
+     tdc_led_5_o : out std_logic;
      -- Signals to the circular_buffer unit: WISHBONE classic
      tstamp_wr_wb_cyc_o      : out std_logic;                      -- tstamp writing WISHBONE cycle
      tstamp_wr_wb_stb_o      : out std_logic;                      -- tstamp writing WISHBONE strobe
@@ -121,7 +125,7 @@ end data_formatting;
 --=================================================================================================
 architecture rtl of data_formatting is
 
-  constant c_MULTIPLY_BY_SIXTEEN                              : std_logic_vector(3 downto 0) := x"0";
+  constant c_MULTIPLY_BY_SIXTEEN                              : std_logic_vector(3 downto 0) := "0000";
   -- ACAM timestamp fields
   signal acam_channel                                         : std_logic_vector(2 downto 0);
   signal acam_slope, acam_fifo_ef                             : std_logic;
@@ -135,25 +139,23 @@ architecture rtl of data_formatting is
   -- final timestamp fields
   signal full_timestamp                                       : std_logic_vector(127 downto 0);
   signal metadata, local_utc, coarse_time, fine_time          : std_logic_vector(31 downto 0);
-  signal previous_utc                                         : std_logic_vector(31 downto 0);
   -- circular buffer timestamp writings WISHBONE interface
   signal tstamp_wr_cyc, tstamp_wr_stb, tstamp_wr_we           : std_logic;
   -- circular buffer counters
   signal dacapo_counter                                       : unsigned(19 downto 0);
-  signal wr_index                                             : unsigned(7 downto 0);
+  signal wr_index                                             : unsigned(7 downto 0); 
   -- coarse time calculations
   signal belongs_to_previous_sec, tstamp_on_first_retrig_case1: std_logic;
-  signal tstamp_on_first_retrig_case2, acam_retrig_ending     : std_logic;
+  signal tstamp_on_first_retrig_case2                         : std_logic;
   signal un_previous_clk_i_cycles_offset                      : unsigned(31 downto 0);
   signal un_previous_retrig_nb_offset                         : unsigned(31 downto 0);
   signal un_previous_roll_over_nb                             : unsigned(31 downto 0);
   signal un_current_clk_i_cycles_offset                       : unsigned(31 downto 0);
   signal un_current_retrig_nb_offset, un_current_roll_over_nb : unsigned(31 downto 0);
   signal un_current_retrig_from_roll_over                     : unsigned(31 downto 0);
-
-  signal acam_start_nb1_un, acam_start_nb2_un, acam_fine_time1_un, acam_fine_time2_un : unsigned(31 downto 0);
-  signal acam_start_nb1_un_aux, acam_start_nb2_un_aux, acam_fine_time1_un_aux, acam_fine_time2_un_aux : unsigned(31 downto 0);
-
+  signal un_acam_fine_time :unsigned(31 downto 0);
+  signal previous_utc                                         : std_logic_vector(31 downto 0);
+  signal acam_timestamps : unsigned (31 downto 0);
 
 
 --=================================================================================================
@@ -212,7 +214,7 @@ begin
 
       elsif tstamp_wr_cyc = '1' and tstamp_wr_stb = '1' and tstamp_wr_we = '1' and tstamp_wr_wb_ack_i = '1' then
 
-        if wr_index = c_CIRCULAR_BUFF_SIZE - 1 then
+        if wr_index = c_CIRCULAR_BUFF_SIZE then
           wr_index    <= (others => '0'); -- when memory completed, restart from the beginning
         else
           wr_index    <= wr_index + 1;    -- otherwise write to the next one
@@ -228,8 +230,7 @@ begin
   wr_index_o         <= std_logic_vector(dacapo_counter) & std_logic_vector(wr_index) & c_MULTIPLY_BY_SIXTEEN;
                      -- "& c_MULTIPLY_BY_SIXTEEN" for the convertion to the number of 8-bits-words
                      -- for the configuration of the DMA
-
-
+  
 ---------------------------------------------------------------------------------------------------
 --                                         Da Capo flag                                          --
 ---------------------------------------------------------------------------------------------------     
@@ -242,7 +243,7 @@ begin
         dacapo_counter <= (others => '0');
 
       elsif tstamp_wr_cyc = '1' and tstamp_wr_stb = '1' and tstamp_wr_we = '1' and
-            tstamp_wr_wb_ack_i = '1' and wr_index = c_CIRCULAR_BUFF_SIZE - 1 then
+            tstamp_wr_wb_ack_i = '1' and wr_index = c_CIRCULAR_BUFF_SIZE then
         dacapo_counter <= dacapo_counter + 1;
       end if;
     end if;
@@ -280,93 +281,30 @@ begin
 
 --   [127:96] Metadata for each timestamp: "00..00" & 0 & ef & Slope & Channel
 
-  acam_start_nb1_un_aux  <= (unsigned(acam_tstamp1_i));
-  acam_start_nb1_un      <= (resize(acam_start_nb1_un_aux(25 downto 18),32));
-  acam_start_nb2_un_aux  <= (unsigned(acam_tstamp2_i));
-  acam_start_nb2_un      <= (resize(acam_start_nb2_un_aux(25 downto 18),32));
-
-  acam_fine_time1_un_aux <= (unsigned(acam_tstamp1_i));
-  acam_fine_time1_un     <= (resize(acam_fine_time1_un_aux(16 downto 0),32));
-  acam_fine_time2_un_aux <= (unsigned(acam_tstamp2_i));
-  acam_fine_time2_un     <= (resize(acam_fine_time2_un_aux(16 downto 0),32));
-
-
-  tstamp_formatting: process (clk_i)
+  tstamp_formatting: process (clk_i)   -- ACAM data handling DFF #2 (DFF #1 refers to the registering of the acam_tstamp1/2_ok_p)
   begin   
     if rising_edge (clk_i) then
       if rst_i ='1' then  
         acam_channel        <= (others => '0');
         acam_fifo_ef        <= '0';
-        --acam_fine_timestamp <= (others => '0');
-        fine_time      <= (others => '0');
+        acam_fine_timestamp <= (others => '0');
         acam_slope          <= '0';
         acam_start_nb       <= (others => '0');
-        un_acam_start_nb   <=(others => '0');
 
       elsif acam_tstamp1_ok_p_i = '1' then
         acam_channel        <= "0" & acam_tstamp1_i(27 downto 26);
         acam_fifo_ef        <= acam_tstamp1_i(31);
-        --acam_fine_timestamp <= acam_tstamp1_i(16 downto 0);
-        fine_time      <= x"000" & "000" & acam_tstamp1_i(16 downto 0);
+        acam_fine_timestamp <= acam_tstamp1_i(16 downto 0);
         acam_slope          <= acam_tstamp1_i(17);
         acam_start_nb       <= acam_tstamp1_i(25 downto 18);
-        un_acam_start_nb  <= (x"000000" & unsigned(acam_tstamp1_i(25 downto 18)));
-
-        if acam_start_nb1_un > 191 and roll_over_incr_recent_i = '1' then
-          acam_retrig_ending <= '1';
-        else      
-          acam_retrig_ending <= '0';
-        end if;
-
-        if acam_start_nb1_un = un_current_retrig_nb_offset or
-         (acam_start_nb1_un = un_current_retrig_nb_offset-1 and  acam_fine_time1_un>6318) then
-          belongs_to_previous_sec <= '1';
-        else
-          belongs_to_previous_sec <= '0';
-        end if;        
 
       elsif acam_tstamp2_ok_p_i ='1' then
         acam_channel        <= "1" & acam_tstamp2_i(27 downto 26);
         acam_fifo_ef        <= acam_tstamp2_i(30);
-        --acam_fine_timestamp <= acam_tstamp2_i(16 downto 0);
-        fine_time      <= x"000" & "000" & acam_tstamp2_i(16 downto 0);
+        acam_fine_timestamp <= acam_tstamp2_i(16 downto 0);
         acam_slope          <= acam_tstamp2_i(17);
         acam_start_nb       <= acam_tstamp2_i(25 downto 18);
-        un_acam_start_nb  <= (x"000000" & unsigned(acam_tstamp2_i(25 downto 18)));
-
-        if acam_start_nb2_un > 191 and roll_over_incr_recent_i = '1' then
-          acam_retrig_ending <= '1';
-        else      
-          acam_retrig_ending <= '0';
-        end if;
-
-        if acam_start_nb2_un = un_current_retrig_nb_offset or
-         (acam_start_nb2_un = un_current_retrig_nb_offset-1 and  acam_fine_time2_un>6318) then
-          belongs_to_previous_sec <= '1';
-        else
-          belongs_to_previous_sec <= '0';
-        end if;       
-
-
       end if;
-
-
-  --belongs_to_previous_sec          <= '1' when tstamp_on_first_retrig_case1 = '1' or tstamp_on_first_retrig_case2 = '1' else '0';
-
-  -- the equation below describes the case where: a timestamp came on the same retgigger after a new second
-  -- (un_current_retrig_from_roll_over in principle is 0):
-  --tstamp_on_first_retrig_case1     <= '1' when (un_acam_start_nb = un_current_retrig_nb_offset) else '0';
-
-  -- according to the Acam documentation there is an indeterminacy to whether the fine time refers to the previous retrigger or the current one.
-  -- the equation below describes the case where: a timestamp came on the same retgigger after a new second but the acam assigned
-  -- it to the previous retrigger.
-  -- the un_current_retrig_from_roll_over in principle is 0 and describes that a new second has arrived;
-  -- the "fine_time > 6318" desribes a fine time that is referred to the previous retrigger; 6318 * 81ps = 512ns which is a complete Acam retrigger
-  --tstamp_on_first_retrig_case2     <= '1' when (un_current_retrig_nb_offset = un_acam_start_nb+1) and (unsigned(fine_time) > 6318) else '0';
-
-
-
-
     end if;
   end process;
 
@@ -390,50 +328,98 @@ begin
   end process;
 
 
+ dummy: process (clk_i)
+  begin   
+    if rising_edge (clk_i) then
+      if rst_i ='1' then  
+        acam_timestamps <= (others => '0');
+
+      elsif acam_tstamp1_ok_p_i = '1' or acam_tstamp2_ok_p_i = '1' then
+        acam_timestamps <= acam_timestamps+1;
+      end if;
+    end if;
+  end process;
+
+
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
   -- all the values needed for the calculations have to be converted to unsigned
-  --acam_start_nb_32                 <= x"000000" & acam_start_nb;
-  --un_acam_start_nb                 <= unsigned(acam_start_nb_32);
+  un_acam_fine_time                <= unsigned(fine_time);
+  acam_start_nb_32                 <= x"000000" & acam_start_nb;
+  un_acam_start_nb                 <= unsigned(acam_start_nb_32);
   un_current_clk_i_cycles_offset   <= unsigned(clk_i_cycles_offset_i);
   un_current_retrig_nb_offset      <= unsigned(retrig_nb_offset_i);
   un_current_roll_over_nb          <= unsigned(roll_over_nb_i);
-  un_current_retrig_from_roll_over <= (un_current_roll_over_nb-256) when acam_retrig_ending = '1' else un_current_roll_over_nb;
-  --un_current_retrig_from_roll_over <= shift_left(un_current_roll_over_nb-1, 8) when roll_over_incr_recent_i = '1' and un_acam_start_nb > 192
-  --                                    else shift_left(un_current_roll_over_nb, 8);
+  un_current_retrig_from_roll_over <= shift_left(un_current_roll_over_nb-1, 8) when roll_over_incr_recent_i = '1' and un_acam_start_nb > 192
+                                      else shift_left(un_current_roll_over_nb, 8);
 
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
   full_timestamp(31 downto 0)      <= fine_time;
   full_timestamp(63 downto 32)     <= coarse_time;
   full_timestamp(95 downto 64)     <= local_utc;
-  full_timestamp(127 downto 96)    <= metadata;
+  full_timestamp(127 downto 96)    <= std_logic_vector(acam_timestamps);--metadata;<---------------
   tstamp_wr_dat_o                  <= full_timestamp;
 
+
+  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+  coarse_time_intermed_calcul: process (clk_i)   -- ACAM data handling DFF #3; at the next cycle (#4) the data is written in memory
+  begin   
+    if rising_edge (clk_i) then
+      if rst_i ='1' then
+        un_clk_i_cycles_offset   <= (others => '0');
+        un_retrig_nb_offset      <= (others => '0');
+        un_retrig_from_roll_over <= (others => '0');
+        local_utc                <= (others => '0');
+      else
+        if (un_acam_start_nb+un_current_retrig_from_roll_over =  un_current_retrig_nb_offset) or
+           (un_acam_start_nb =  un_current_retrig_nb_offset-1 and  un_acam_fine_time > 6318 and (un_current_retrig_from_roll_over = 0) ) then
+          un_clk_i_cycles_offset <= un_previous_clk_i_cycles_offset;
+          un_retrig_nb_offset    <= un_previous_retrig_nb_offset;
+          local_utc              <= previous_utc;
+          if roll_over_incr_recent_i = '1' and un_acam_start_nb > 192 then
+            un_retrig_from_roll_over  <= shift_left(un_previous_roll_over_nb-1, 8);
+          else
+            un_retrig_from_roll_over   <= shift_left(un_previous_roll_over_nb, 8);
+          end if;
+        else
+          un_clk_i_cycles_offset <= unsigned(clk_i_cycles_offset_i);
+          un_retrig_nb_offset    <= unsigned(retrig_nb_offset_i);
+          local_utc              <= local_utc_i;
+          if roll_over_incr_recent_i = '1' and un_acam_start_nb > 192 then
+            un_retrig_from_roll_over           <= shift_left(unsigned(roll_over_nb_i)-1, 8);
+          else
+            un_retrig_from_roll_over           <= shift_left(unsigned(roll_over_nb_i), 8);
+          end if;
+        end if;        
+      end if;
+    end if;
+  end process;
+
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  un_clk_i_cycles_offset           <= un_previous_clk_i_cycles_offset when (belongs_to_previous_sec = '1')
-                                      else un_current_clk_i_cycles_offset;
+  -- un_clk_i_cycles_offset           <= un_previous_clk_i_cycles_offset when (belongs_to_previous_sec = '1')
+                                      -- else un_current_clk_i_cycles_offset;
 
-  un_retrig_nb_offset              <= un_previous_retrig_nb_offset when (belongs_to_previous_sec = '1')
-                                      else un_current_retrig_nb_offset;
+  -- un_retrig_nb_offset              <= un_previous_retrig_nb_offset when (belongs_to_previous_sec = '1')
+                                      -- else un_current_retrig_nb_offset;
 
-  un_roll_over                     <= un_previous_roll_over_nb when (belongs_to_previous_sec = '1') 
-                                      else un_current_roll_over_nb;
+  -- un_roll_over                     <= un_previous_roll_over_nb when (belongs_to_previous_sec = '1') 
+                                      -- else un_current_roll_over_nb;
 
-  local_utc                        <= previous_utc when (belongs_to_previous_sec = '1')
-                                      else local_utc_i;
+  -- local_utc                        <= un_previous_utc when (belongs_to_previous_sec = '1')
+                                      -- else local_utc_i;
 
 
   --belongs_to_previous_sec          <= '1' when tstamp_on_first_retrig_case1 = '1' or tstamp_on_first_retrig_case2 = '1' else '0';
 
   -- the equation below describes the case where: a timestamp came on the same retgigger after a new second
   -- (un_current_retrig_from_roll_over in principle is 0):
-  --tstamp_on_first_retrig_case1     <= '1' when (un_acam_start_nb = un_current_retrig_nb_offset) else '0';
+  --tstamp_on_first_retrig_case1     <= '1' when (un_current_retrig_from_roll_over + un_acam_start_nb = un_current_retrig_nb_offset) else '0';
 
   -- according to the Acam documentation there is an indeterminacy to whether the fine time refers to the previous retrigger or the current one.
   -- the equation below describes the case where: a timestamp came on the same retgigger after a new second but the acam assigned
   -- it to the previous retrigger.
-  -- the un_current_retrig_from_roll_over in principle is 0 and describes that a new second has arrived;
+  -- the "un_current_retrig_from_roll_over = 0" describes that a new second has arrived;
   -- the "fine_time > 6318" desribes a fine time that is referred to the previous retrigger; 6318 * 81ps = 512ns which is a complete Acam retrigger
-  --tstamp_on_first_retrig_case2     <= '1' when (un_current_retrig_nb_offset = un_acam_start_nb+1) and (unsigned(fine_time) > 6318) else '0';
+  --tstamp_on_first_retrig_case2     <= '1' when (un_current_retrig_nb_offset = un_acam_start_nb+1) and (unsigned(fine_time) > 6318) and (un_current_retrig_from_roll_over = 0) else '0';
 
 
   -- the number of roll-overs of the ACAM-internal-start-retrigger-counter is converted to a number of internal start retriggers,
@@ -444,14 +430,15 @@ begin
   -- start_nb from the ACAM is close to the upper end (close to 255) and on the moment the timestamp is being treated in the FPGA
   -- the IrFlag has recently been tripped it means that for the formatting of the tstamp the previous value of the roll_over_c
   -- should be considered (before the IrFlag tripping).
-  -- Eva: have to calculate bit better the amount of tstamps that could have been accumulated before the rollover changes;
+  -- Eva: have to calculate better the amount of tstamps that could have been accumulated before the rollover changes;
   -- the current value we put "192" is not well studied for all cases!!
-  un_retrig_from_roll_over         <= (un_roll_over-256) when acam_retrig_ending = '1' else (un_roll_over);
+  --un_retrig_from_roll_over         <= shift_left(un_roll_over-1, 8) when roll_over_incr_recent_i = '1' and un_acam_start_nb > 192
+  --                                    else shift_left(un_roll_over, 8);
 
 
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
   -- fine time: directly provided by ACAM as a number of BINs since the last internal retrigger
-  --fine_time                     <= x"000" & "000" & acam_fine_timestamp;
+  fine_time                     <= x"000" & "000" & acam_fine_timestamp;
 
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
   -- local UTC: updated every second by the one_hz_pulse unit
@@ -474,8 +461,8 @@ begin
 
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  
   -- metadata: information about the timestamp
-  metadata                      <= "000000000000000000000000" &--acam_start_nb & retrig_nb_offset_i(15 downto 0) &         -- for debugging (24 MSbits)
-                                   "000" &--belongs_to_previous_sec & roll_over_incr_recent_i & "0" & -- for debugging (3 bits)
+  metadata                      <= acam_start_nb & retrig_nb_offset_i(15 downto 0) &         -- for debugging (24 MSbits)
+                                   belongs_to_previous_sec & roll_over_incr_recent_i & "0" & -- for debugging (3 bits)
                                    acam_slope & "0" & acam_channel;                          -- 5 LSbits
 
 
diff --git a/hdl/svec/hdl/rtl/fmc_tdc_core.vhd b/hdl/svec/hdl/rtl/fmc_tdc_core.vhd
index fa3fa4643cc42a129d2eca9c1dd55c45527e7ff1..95c1cb56ae1aef546d6d1ca974d84077f6000d8a 100644
--- a/hdl/svec/hdl/rtl/fmc_tdc_core.vhd
+++ b/hdl/svec/hdl/rtl/fmc_tdc_core.vhd
@@ -134,7 +134,7 @@ entity fmc_tdc_core is
      tdc_mem_wb_we_i     : in std_logic;                            -- WISHBONE pipelined write enable
      tdc_mem_wb_cyc_i    : in std_logic;                            -- WISHBONE pipelined cycle
      tdc_mem_wb_ack_o    : out std_logic;                           -- WISHBONE pipelined acknowledge
-     tdc_mem_wb_dat_o    : out std_logic_vector(31 downto 0);       -- WISHBONE classic data out
+     tdc_mem_wb_dat_o    : out std_logic_vector(31 downto 0);       -- WISHBONE pipelined data out
      tdc_mem_wb_stall_o  : out std_logic);                          -- WISHBONE pipelined stall
 end fmc_tdc_core;
 
@@ -175,6 +175,7 @@ architecture rtl of fmc_tdc_core is
   signal circ_buff_class_data_wr, circ_buff_class_data_rd   : std_logic_vector(4*g_width-1 downto 0);
 
 
+
 --=================================================================================================
 --                                       architecture begin
 --=================================================================================================
@@ -502,6 +503,7 @@ begin
      rst_i            => rst_i,
      one_hz_p_i       => one_hz_p,
      acam_inputs_en_i => acam_inputs_en,
+     fordebug_i       => acam_tstamp1_ok_p,
      tdc_led_status_o => tdc_led_status_o,
      tdc_led_trig1_o  => tdc_led_trig1_o,
      tdc_led_trig2_o  => tdc_led_trig2_o,
diff --git a/hdl/svec/hdl/rtl/fmc_tdc_mezzanine.vhd b/hdl/svec/hdl/rtl/fmc_tdc_mezzanine.vhd
index 2c3efeb5bf99d2ec03540afb9de5bb22f8e64e19..8b144e709c022cc66571aec1868b1d7da90fbbb4 100644
--- a/hdl/svec/hdl/rtl/fmc_tdc_mezzanine.vhd
+++ b/hdl/svec/hdl/rtl/fmc_tdc_mezzanine.vhd
@@ -130,10 +130,9 @@ architecture rtl of fmc_tdc_mezzanine is
   constant c_NUM_WB_MASTERS           : integer := 5;
   constant c_WB_SLAVE_TDC_CORE_CONFIG : integer := 0;  -- TDC core configuration registers
   constant c_WB_SLAVE_TDC_ONEWIRE     : integer := 1;  -- TDC mezzanine board UnidueID&Thermometer 1-wire
-  constant c_WB_SLAVE_TSTAMP_MEM      : integer := 2;  -- Access to TDC core timestamps memory
+  constant c_WB_SLAVE_DUMMY           : integer := 2;  -- Dummy for debugging
   constant c_WB_SLAVE_TDC_SYS_I2C     : integer := 3;  -- TDC mezzanine board system EEPROM I2C
-  constant c_WB_SLAVE_DUMMY           : integer := 4;  -- Dummy for debugging
-
+  constant c_WB_SLAVE_TSTAMP_MEM      : integer := 4;  -- Access to TDC core timestamps memory
 
   -- Slave port on the wishbone crossbar
   constant c_NUM_WB_SLAVES            : integer := 1;
@@ -143,11 +142,11 @@ architecture rtl of fmc_tdc_mezzanine is
   constant c_SDB_ADDRESS              : t_wishbone_address := x"00000000";
   -- WISHBONE crossbar layout
   constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(4 downto 0) :=
-    (0 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00001000"),
-     1 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE,    x"00001100"),
-     2 => f_sdb_embed_device(c_TDC_MEM_SDB_DEVICE,    x"00001200"),
-     3 => f_sdb_embed_device(c_I2C_SDB_DEVICE,        x"00001300"),
-     4 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00001400"));
+    (0 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00010000"),
+     1 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE,    x"00011000"),
+     2 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00012000"),
+     3 => f_sdb_embed_device(c_I2C_SDB_DEVICE,        x"00013000"),
+     4 => f_sdb_embed_device(c_TDC_MEM_SDB_DEVICE,    x"00014000"));
 
 ---------------------------------------------------------------------------------------------------
 --                                            Signals                                            --
diff --git a/hdl/svec/hdl/rtl/leds_manager.vhd b/hdl/svec/hdl/rtl/leds_manager.vhd
index bcd2e5378e42217ca4a181aefd494975099e5fe5..6317a1bf60947b0eb9752b9f3d65c409fbde92a0 100644
--- a/hdl/svec/hdl/rtl/leds_manager.vhd
+++ b/hdl/svec/hdl/rtl/leds_manager.vhd
@@ -87,6 +87,8 @@ entity leds_manager is
      acam_inputs_en_i  : in std_logic_vector(g_width-1 downto 0); -- enable for the ACAM channels;
                                         -- activation comes through dedicated reg c_ACAM_INPUTS_EN_ADR
 
+     fordebug_i        : in std_logic;
+
 
   -- OUTPUTS
      -- Signals to the LEDs on the TDC front panel
@@ -105,8 +107,9 @@ end leds_manager;
 --=================================================================================================
 architecture rtl of leds_manager is
 
-  signal tdc_led_blink_done                    : std_logic;
-  signal spec_led_period, visible_blink_length : std_logic_vector(g_width-1 downto 0);
+  signal tdc_led_blink_done, tdc_debug_led_blink_done : std_logic;
+  signal spec_led_period, visible_blink_length        : std_logic_vector(g_width-1 downto 0);
+  signal tdc_debug_led                                : std_logic;
 
 
 begin
@@ -116,7 +119,7 @@ begin
   
 ---------------------------------------------------------------------------------------------------
 
-  tdc_led_blink_counter: decr_counter
+  tdc_status_led_blink_counter: decr_counter
   port map
     (clk_i             => clk_i,
      rst_i             => rst_i,
@@ -126,7 +129,7 @@ begin
      counter_o         => open);
 
 ---------------------------------------------------------------------------------------------------
-  tdc_led: process (clk_i)
+  tdc_status_led_gener: process (clk_i)
   begin
     if rising_edge (clk_i) then
       if rst_i ='1' then
@@ -146,10 +149,38 @@ begin
 --                                    TDC FRONT PANEL LEDs 2-6                                   --
 --------------------------------------------------------------------------------------------------- 
 ---------------------------------------------------------------------------------------------------
+
+  tdc_debug_led_blink_counter: decr_counter
+  port map
+    (clk_i             => clk_i,
+     rst_i             => rst_i,
+     counter_load_i    => fordebug_i,
+     counter_top_i     => visible_blink_length,
+     counter_is_zero_o => tdc_debug_led_blink_done,
+     counter_o         => open);
+
+---------------------------------------------------------------------------------------------------
+  tdc_debug_led_gener: process (clk_i)
+  begin
+    if rising_edge (clk_i) then
+      if rst_i ='1' then
+        tdc_debug_led <= '0';
+      elsif fordebug_i ='1' then
+        tdc_debug_led <= '1';
+      elsif tdc_debug_led_blink_done = '1' then
+        tdc_debug_led <= '0';
+      end if;
+    end if;
+  end process;
+
+  visible_blink_length <= c_BLINK_LGTH_SIM when values_for_simulation else c_BLINK_LGTH_SYN;
+
+
+
   all_outputs: process (clk_i)
   begin
     if rising_edge (clk_i) then
-      tdc_led_trig5_o  <= acam_inputs_en_i(4) and acam_inputs_en_i(7);
+      tdc_led_trig5_o  <= tdc_debug_led;--acam_inputs_en_i(4) and acam_inputs_en_i(7);
       tdc_led_trig4_o  <= acam_inputs_en_i(3) and acam_inputs_en_i(7);
       tdc_led_trig3_o  <= acam_inputs_en_i(2) and acam_inputs_en_i(7);
       tdc_led_trig2_o  <= acam_inputs_en_i(1) and acam_inputs_en_i(7);
diff --git a/hdl/svec/hdl/rtl/one_hz_gen.vhd b/hdl/svec/hdl/rtl/one_hz_gen.vhd
index 4404d4a260f5d75fc3ab7b0710f2e6738706be69..2c2ef9f539b6a941b7b3ccd3d5401812831e12c7 100644
--- a/hdl/svec/hdl/rtl/one_hz_gen.vhd
+++ b/hdl/svec/hdl/rtl/one_hz_gen.vhd
@@ -13,7 +13,7 @@
 -- File         one_hz_gen.vhd                                                                    |
 --                                                                                                |
 -- Description  Generates one pulse every second synchronously with the acam reference clock.     |
---              The phase with the reference clock can be adjusted [eva still don t know why??]   |
+--              The phase with the reference clock can be adjusted. still don t know why??        |
 --              It also keeps track of the UTC time based on the local clock.                     |
 --                                                                                                |
 --                                                                                                |
@@ -66,16 +66,16 @@ entity one_hz_gen is
     (g_width                : integer := 32);
   port
   -- INPUTS
-     -- Signals from the clks_rsts_manager unit
-    (clk_i                  : in std_logic;  -- 125 MHZ clk
-     rst_i                  : in std_logic;  -- global reset, synched to clk_i
-     acam_refclk_r_edge_p_i : in std_logic;  -- rising edge on 31.25MHz ACAM reference clk
-     clk_period_i           : in std_logic_vector(g_width-1 downto 0); -- nb of clk_i periods for 1s
+     -- Signals from the clk_rst_manager unit
+    (clk_i                  : in std_logic;
+     rst_i                  : in std_logic;  
+     acam_refclk_r_edge_p_i : in std_logic;   
+     clk_period_i           : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods for 1s
 
      -- Signals from the reg_ctrl unit
      load_utc_p_i           : in std_logic; -- enables loading of the local UTC time with starting_utc_i value
-     starting_utc_i         : in std_logic_vector(g_width-1 downto 0); -- value coming from the PCIe/VME interface
-     pulse_delay_i          : in std_logic_vector(g_width-1 downto 0); -- nb of clk_i periods phase delay
+     starting_utc_i         : in std_logic_vector(g_width-1 downto 0); -- value coming from the PCIe
+     pulse_delay_i          : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods phase delay
                                                                        -- with respect to reference clock
 
   -- OUTPUTS
@@ -92,7 +92,7 @@ end one_hz_gen;
 --=================================================================================================
 architecture rtl of one_hz_gen is
 
-  constant constant_delay         : unsigned(g_width-1 downto 0) := x"00000004"; --maybe put in package..maybe not needed
+  constant constant_delay         : unsigned(g_width-1 downto 0) := x"00000004"; --maybe put in package--maybe not needed
   signal local_utc                : unsigned(g_width-1 downto 0);
   signal one_hz_p_pre             : std_logic;
   signal one_hz_p_post            : std_logic;
@@ -147,9 +147,9 @@ begin
 --                                         Load UTC time                                         --
 ---------------------------------------------------------------------------------------------------
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
--- utc_counter: generation of a 1-clk-long pulse every second
+-- utc_counter: generation of a 1 clk-long pulse every second
 
-  utc_counter: process (clk_i) -- maybe use an already existing counter???
+  utc_counter: process (clk_i)--maybe use an already existing counter???
   begin   
     if rising_edge (clk_i) then
       if rst_i ='1' then
diff --git a/hdl/svec/hdl/rtl/reg_ctrl.vhd b/hdl/svec/hdl/rtl/reg_ctrl.vhd
index 5588119378c9695946a3b31826537c0cbf9d156c..2c839eac3c72b5a156f1f2c42281db60c2e7826f 100644
--- a/hdl/svec/hdl/rtl/reg_ctrl.vhd
+++ b/hdl/svec/hdl/rtl/reg_ctrl.vhd
@@ -160,7 +160,7 @@ end reg_ctrl;
 architecture rtl of reg_ctrl is
 
   signal acam_config                                  : config_vector;
-  signal reg_adr                                      : std_logic_vector(7 downto 0);
+  signal reg_adr,reg_adr_pipe0                                      : std_logic_vector(7 downto 0);
   signal starting_utc, acam_inputs_en, start_phase    : std_logic_vector(g_width-1 downto 0);
   signal ctrl_reg, one_hz_phase, irq_tstamp_threshold : std_logic_vector(g_width-1 downto 0);
   signal irq_time_threshold                           : std_logic_vector(g_width-1 downto 0);
@@ -168,8 +168,9 @@ architecture rtl of reg_ctrl is
   signal dac_word                                     : std_logic_vector(23 downto 0);
   signal pulse_extender_en                            : std_logic;
   signal pulse_extender_c                             : std_logic_vector(2 downto 0);
-  signal dat_out                                      : std_logic_vector(g_span-1 downto 0);
+  signal dat_out, dat_out_pipe0                                      : std_logic_vector(g_span-1 downto 0);
 
+  signal tdc_config_wb_ack_o_pipe0 : std_logic;
 --=================================================================================================
 --                                       architecture begin
 --=================================================================================================
@@ -189,8 +190,13 @@ begin
     if rising_edge (clk_i) then
       if rst_i = '1' then
         tdc_config_wb_ack_o <= '0';
+        tdc_config_wb_ack_o_pipe0 <= '0';
+      elsif(tdc_config_wb_cyc_i = '0') then
+        tdc_config_wb_ack_o <= '0';
+        tdc_config_wb_ack_o_pipe0 <= '0';
       else
-        tdc_config_wb_ack_o <= tdc_config_wb_stb_i and tdc_config_wb_cyc_i;
+        tdc_config_wb_ack_o <= tdc_config_wb_ack_o_pipe0;
+        tdc_config_wb_ack_o_pipe0 <= tdc_config_wb_stb_i and tdc_config_wb_cyc_i;
       end if;
     end if;
   end process;
@@ -421,17 +427,16 @@ begin
   WISHBONEreads: process (clk_i)
   begin
     if rising_edge (clk_i) then
-      if rst_i = '1' then
-        tdc_config_wb_dat_o <= (others =>'0');
-
-      elsif tdc_config_wb_cyc_i = '1' and tdc_config_wb_stb_i = '1' and tdc_config_wb_we_i = '0' then -- WISHBONE reads
-        tdc_config_wb_dat_o <= dat_out;
-      end if;
+      --if tdc_config_wb_cyc_i = '1' and tdc_config_wb_stb_i = '1' and tdc_config_wb_we_i = '0' then -- WISHBONE reads
+      --  tdc_config_wb_dat_o <= dat_out;
+      reg_adr_pipe0 <= reg_adr;
+      tdc_config_wb_dat_o <= dat_out;
+      --end if;
     end if;
   end process;
 
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  with reg_adr select dat_out <= 
+  with reg_adr_pipe0 select dat_out <= 
     -- regs written by the PCIe/VME interface
     acam_config(0)         when c_ACAM_REG0_ADR,
     acam_config(1)         when c_ACAM_REG1_ADR,
@@ -483,4 +488,4 @@ end architecture rtl;
 --=================================================================================================
 ---------------------------------------------------------------------------------------------------
 --                                      E N D   O F   F I L E
----------------------------------------------------------------------------------------------------
\ No newline at end of file
+---------------------------------------------------------------------------------------------------
diff --git a/hdl/svec/hdl/rtl/start_retrig_ctrl.vhd b/hdl/svec/hdl/rtl/start_retrig_ctrl.vhd
index 36d6148ca608bfc1cd29be3e9f1cfefb74a87858..29ca83b4139a8cfc64f045479bb49ba50e29e6d9 100644
--- a/hdl/svec/hdl/rtl/start_retrig_ctrl.vhd
+++ b/hdl/svec/hdl/rtl/start_retrig_ctrl.vhd
@@ -1,338 +1,314 @@
---_________________________________________________________________________________________________
---                                                                                                |
---                                           |TDC core|                                           |
---                                                                                                |
---                                         CERN,BE/CO-HT                                          |
---________________________________________________________________________________________________|
-
----------------------------------------------------------------------------------------------------
---                                                                                                |
---                                       start_retrig_ctrl                                        |
---                                                                                                |
----------------------------------------------------------------------------------------------------
--- File         start_retrig_ctrl.vhd                                                             |
---                                                                                                |
--- Description  The unit provides the main components for the calculation of the "Coarse time" of |
---              the final timestamps. These components are sent to the data_formatting unit where |
---              the actual Coarse time calculation takes place.                                   |
---                                                                                                |
---              As a reminder, the final timestamp is a 128-bits word divided in four 32-bits     |
---              words with the following structure:                                               |
---                                                                                                |
---                [127:96]  Timestamp Metadata (ex. Channel, Slope)                               |
---                                                                                                |
---                 [95:64]  Local UTC time from the one_hz_generator; each bit represents 1 s     |
---                                                                                                |
---                 [63:32]  Coarse time within the current second; each bit represents 8 ns       |
---                                                                                                |
---                  [31:0]  Fine time to be added to the Coarse time: provided directly by Acam;  |
---                          each bit represents 81.03 ps                                          |
---                                                                                                |
---              In I-Mode the Acam chip provides unlimited measuring range with internal start    |
---              retriggers. Acam is programmed to retrigger every (16*acam_clk_period) =          |
---              (64*clk_i_period) = 512 ns; the StartTimer in Acam Reg 4 is set to 15. It counts  |
---              the number of retriggers after a Start pulse and upon the arrival of a Stop pulse |
---              and it sends this number in the "Start#" field of the timestamp.                  |
---              Unfortunately Acam's counter of the retriggers has only 8 bits and can count up   |
---              to 256 retriggers. Within one second (our UTC time) there can be up to            |
---              1,953,125 retriggers, which is >> 256 and actually corresponds to 7629 overflows  |
---              of the Acam counter. Therefore there is the need to follow Acam and keep track of |
---              the overflows. The Acam Interrupt flag (IrFlag pin 59) has been set to follow the |
---              highest bit of the Start# (through the Acam Reg 12 bit 26) and like this we       |
---              manage to count retriggers synchronously to Acam itself.                          |
---              For simplification, in the following figure we assume that two Stop signals arrive|
---              after less than 256 Acam internal retriggers. Therefore in the timestamps that    |
---              Acam will give the Start# field will represent the exact amount of retriggers     |
---              after the Start pulse.                                                            |
---              Note that the interval between this external Start pulse and the first internal   |
---              retrigger may vary; it is measured by the Acam chip and stored as Start01 in Acam |
---              Reg 10. Moreover, there is the StartOff1 offset added to each Hit time by Acam    |
---              (this does not appear in this figure) made available in Acam Reg 5.               |
---              However, in this TDC core application we are only interested in time differences  |
---              between Stop pulses (ex. Stop2 - Stop1) and not in the precise arrival time of a  |
---              Stop pulse. Since now both Start01 and StartOff1 are stable numbers affecting     |
---              equally all the Stop pulses, they would disappear during the subtraction (which   |
---              takes place at the software side) and therefore thay are used in our calculations.|
---                                                                                                |
--- Start        ____|-|__________________________________________________________________________ |
--- Retriggers   ________________|-|________________|-|________________|-|________________|-|_____ |
--- Stop1        _________________________________________________|-|_____________________________ |
--- Hit1                                            <------------->
--- Stop2        _____________________________________________________________________________|-|_ |
--- Hit2                                                                                   <-->    |
--- Start01          <---------->                                                                  |
---                                                                                                |
---              Coming back now to our timestamp format {UTC second, Coarse time, Fine time}, we  |
---              have to somehow assosiate ACAM retriggers to the UTC time. Actually, Acam has no  |
---              knowledge of the UTC time and the arrival of a new second happens completely      |
---              independently. As the following figure shows the final timestamp of a Stop pulse  |
---              is defined by the current UTC time plus the amount of time between that UTC and   |
---              the Stop pulse: (2)+(3). Part (3) is provided exclusively by the Acam chip in the |
---              Start# and Hit time fields of the timestamp. The sum of (1)+(2) is multiples of   |
---              256 Acam retriggers and can be defined by following the Acam output IrFlag.       |
---              Now Part (1), is the one that associates the arrival of a UTC second with the Acam|
---              time counting and is defined in this unit by following the Acam retriggers.       |
---                                                                                                |
--- IrFlag     ______________|--------------|______________|-------------|... _____________|---    |
---             ___________________________  ___________________________       _____________       |
--- new UTC sec|               _|-|_       ||                           |     |                    |
--- Stop1      |                           ||                           | ... |      _|-|_         |
---            |___________________________||___________________________|     |______________      |
---                    (1)                                                                         |
---            |----------------|                                                                  |
---                                                  (2)                                           |
---                             |---------------------------------------------|                    |
---                                                                              (3)               |
---                                                                           |-------|            |
---                                                                                                |
---              To conclude, the final Coarse time is: (Part(2) + Part(3)_Start#)*Retrigger period|
---              and the  Fine time is : Part(3)_Hit                                               |
---                                                                                                |
---                                                                                                |
--- Authors      Gonzalo Penacoba  (Gonzalo.Penacoba@cern.ch)                                      |
---              Evangelia Gousiou (Evangelia.Gousiou@cern.ch)                                     |
--- Date         04/2012                                                                           |
--- Version      v0.11                                                                             |
--- Depends on                                                                                     |
---                                                                                                |
-----------------                                                                                  |
--- Last changes                                                                                   |
---     07/2011  v0.1  GP  First version                                                           |
---     04/2012  v0.11 EG  Revamping; Comments added, signals renamed                              |
----------------------------------------------------------------------------------------------------
-
----------------------------------------------------------------------------------------------------
---                               GNU LESSER GENERAL PUBLIC LICENSE                                |
---                              ------------------------------------                              |
--- This source file is free software; you can redistribute it and/or modify it under the terms of |
--- the GNU Lesser General Public License as published by the Free Software Foundation; either     |
--- version 2.1 of the License, or (at your option) any later version.                             |
--- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;       |
--- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.      |
--- See the GNU Lesser General Public License for more details.                                    |
--- You should have received a copy of the GNU Lesser General Public License along with this       |
--- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html                     |
----------------------------------------------------------------------------------------------------
-
-
-
---=================================================================================================
---                                       Libraries & Packages
---=================================================================================================
-
--- Standard library
-library IEEE;
-use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
-use IEEE.NUMERIC_STD.all;    -- conversion functions-- Specific library
--- Specific library
-library work;
-use work.tdc_core_pkg.all;   -- definitions of types, constants, entities
-
-
---=================================================================================================
---                            Entity declaration for start_retrig_ctrl
---=================================================================================================
-
-entity start_retrig_ctrl is
-  generic
-    (g_width                 : integer := 32);
-  port
-  -- INPUTS
-     -- Signal from the clks_rsts_manager
-    (clk_i                   : in std_logic; -- 125 MHz clk
-     rst_i                   : in std_logic; -- global reset, synched to clk_i
-
-     -- Signal from the acam_timecontrol_interface
-     acam_intflag_f_edge_p_i : in std_logic;
-
-     -- Signal from the one_hz_generator unit
-     one_hz_p_i              : in std_logic;
-
-
-  -- OUTPUTS
-     -- Signals to the data_formatting unit
-     roll_over_incr_recent_o : out std_logic;
-     clk_i_cycles_offset_o   : out std_logic_vector(g_width-1 downto 0);
-     roll_over_nb_o          : out std_logic_vector(g_width-1 downto 0);
-     retrig_nb_offset_o      : out std_logic_vector(g_width-1 downto 0));
-
-end start_retrig_ctrl;
-
---=================================================================================================
---                                    architecture declaration
---=================================================================================================
-
-architecture rtl of start_retrig_ctrl is
-
-  signal clk_i_cycles_offset : std_logic_vector(g_width-1 downto 0);
-  signal current_cycles      : std_logic_vector(g_width-1 downto 0);
-  signal current_retrig_nb   : std_logic_vector(g_width-1 downto 0);
-  signal retrig_nb_offset    : std_logic_vector(g_width-1 downto 0);
-  signal retrig_p            : std_logic;
-  signal roll_over_c         : unsigned(g_width-1 downto 0);
-  signal acam_rollovers      : unsigned(g_width-1 downto 0);
-
---=================================================================================================
---                                       architecture begin
---=================================================================================================
-begin
-
--- retrigger #      :   0    1          127  128        255  256  257        383  384  385         511  512  513
--- retriggers       :  _|____|____...____|____|____...____|____|____|____...___|____|____|____...____|____|____|___
--- IrFlag           :  __________________|---------------------|____________________|---------------------|________
--- IrFlag_f_edge_p  :  ______________________________________|-|________________________________________|-|________
--- retrig_p         : |-|__|-|__ ... __|-|__|-|__ ... __|-|__|-|__|-|__ ...__|-|__|-|__|-|___ ...__|-|__|-|__|-|___
--- current_retrig_nb:  0    1          127  128         255   0    1         127  128  129         255   0    1
-
--- one_hz_p_i       : _____________________|-|_______________________________________________________________
--- roll_over_c      :                       0                 1                                          2
--- retrig_nb_offset :                      127
--- clk_i_cycles_offs:                      |..| (counts clk_i cycles from the pulse to the end of this retrigger) 
---
--- At the moment that a new second arrives through the one_hz_p_i, we:
---  o keep note of the current_retrig_nb, 127 in this case (stored in retrig_nb_offset)
---  o keep note of the current_cycles, that is the number of clk_i cycles between the one_hz_p_i
---    and the next (128th) retrigger (stored in clk_i_cycles_offset)
---  o reinitialize the roll_over_c counter which starts counting rollovers of the current_retrig_nb
---
---  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
--- In this more macroscopic example we have included a Stop pulse arriving to the ACAM chip.
--- Each one of the n boxes represents 256 ACAM internal retriggers, which through the IrFlag are
--- synchronous with the counters in this unit. The coarse time is the amount of clk_i cycles
--- between the one_hz_p_i pulse and the ACAM Stop pulse. To the coarse time we then have to add the
--- fine time, which is the very precise 81ps resolution time measured by the ACAM. Note that the
--- ACAM can only provide timing information within the last box: the Start# (bits 25:18) indicates
--- the amount of internal retriggers and the Hit (bits 16:0) indicates the fine timing. The time
--- difference between the one_hz_p_i pulse and the last box is calculated through the counters of
--- this unit: roll_over_c, retrig_nb_offset, clk_i_cycles_offset.
-
--- Note that since the counting in the roll_over_c starts from 0, we do not need to subtract 1
--- so as not to consider the last, n-th, box. Similarly, for the retrig_nb_offset and ACAM Start#,
--- to calculate the amount of complete retriggers that have preceded the arrival of the
--- one_hz_p_i and the Stop pulse respectively, we would have to subtract 1, but since counting
--- starts from zero, we don't.
--- Finally, note that the the current_cycles counter is a decreasing counter giving the amount of
--- clk_i cycles between the resing edge of the one_hz_pulse_i and the next retrigger. 
--- Note that in this project we are only interested in time differences between 
-
---                    _______________________________________  _________________________________________       ____________________
--- one_hz_p_i        |                           _|-|_       ||                                         |     |
--- ACAM Stop pulse   |                                       ||                                         |     |       _|-|_
---                   |                                       ||                                         | ... |                    
--- roll_over_c       |                             0         ||1                                        |     |n-1                    
---                   |_______________________________________||_________________________________________|     |____________________
---                                (1)
---                   |----------------------------|
---                                                                             (2)
---                                                |-----------------------------------------------------------|
---                                                                                                                (3)
---                                                                                                            |--------|
-
---                  (1): ((retrig_nb_offset + 1) * retrig_period) - (clk_i_cycles_offset)
---                  (2): (roll_over_c * 256 * retrig_period) - (the amount that (1) represents)
---                  (3): from ACAM tstamps: (Start# * retrig_period) + (Fine time: Hit)
-
---  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
--- These two counters keep a track of the current internal start retrigger
--- of the Acam in parallel with the Acam itself. Counting up to c_ACAM_RETRIG_PERIOD = 64
-
- retrig_period_counter: free_counter  -- retrigger periods
-   generic map
-     (width             => g_width)
-   port map
-     (clk_i             => clk_i,
-      rst_i             => acam_intflag_f_edge_p_i,
-      counter_en_i      => '1',
-      counter_top_i     => c_ACAM_RETRIG_PERIOD,
-     -------------------------------------------
-      counter_is_zero_o => retrig_p,
-      counter_o         => current_cycles);
-     -------------------------------------------
-
-  retrig_nb_counter: incr_counter    -- number of retriggers counting from 0 to 255 and restarting
-    generic map                      -- through the acam_intflag_f_edge_p_i
-      (width             => g_width)
-    port map
-      (clk_i             => clk_i,
-       rst_i             => acam_intflag_f_edge_p_i,  
-       counter_top_i     => x"00000100",
-       counter_incr_en_i => retrig_p,
-       counter_is_full_o => open,
-     -------------------------------------------
-       counter_o         => current_retrig_nb);
-     -------------------------------------------
-
-
---  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  -- This counter keeps track of the number of overflows of the Acam counter within one second
-  --roll_over_counter: incr_counter
-    -- generic map
-      -- (width             => g_width)
-    -- port map
-      -- (clk_i             => clk_i,
-       -- rst_i             => one_hz_p_i,  
-       -- counter_top_i     => x"FFFFFFFF",
-       -- counter_incr_en_i => acam_intflag_f_edge_p_i,
-       -- counter_is_full_o => open,
-       -- counter_o         => roll_over_c);
-
-  roll_over_incr_counter: process (clk_i)
-  begin
-    if rising_edge (clk_i) then
-      if one_hz_p_i = '1' then
-        roll_over_c    <= (others => '0');
-        acam_rollovers <= (others => '0');
-
-      elsif roll_over_c = x"FFFFFFFF" then
-        roll_over_c     <= x"FFFFFFFF";
-        acam_rollovers  <= shift_left(x"FFFFFFFF",8);
-
-      elsif acam_intflag_f_edge_p_i ='1' then
-          roll_over_c    <= roll_over_c + "1";
-          acam_rollovers <= shift_left(roll_over_c + "1",8);
-      end if;
-    end if;
-  end process;
-
-
---  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  -- When a new second starts, all values are captured and stored as offsets.
-  -- when a timestamps arrives, these offset will be subrstracted in order
-  -- to base the final timestamp with respect to the current second.
-  capture_offset: process (clk_i)
-  begin
-    if rising_edge (clk_i) then
-      if rst_i ='1' then
-        clk_i_cycles_offset     <= (others=>'0');
-        retrig_nb_offset        <= (others=>'0');
-        roll_over_incr_recent_o <= '0';
-
-      elsif one_hz_p_i = '1' then
-        clk_i_cycles_offset <= current_cycles;
-        retrig_nb_offset    <= current_retrig_nb;
-        if unsigned(current_retrig_nb) < 64 then
-          roll_over_incr_recent_o <= '1';
-        else
-          roll_over_incr_recent_o <= '0';
-        end if;
-      end if;
-
-    end if;
-  end process;
-
---  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --    
-    
-  -- outputs
-  clk_i_cycles_offset_o   <= clk_i_cycles_offset;
-  retrig_nb_offset_o      <= retrig_nb_offset;
-  roll_over_nb_o          <= std_logic_vector(acam_rollovers);
-  --roll_over_nb_o          <= roll_over_c;
-
-
-end architecture rtl;
---=================================================================================================
---                                        architecture end
---=================================================================================================
----------------------------------------------------------------------------------------------------
---                                      E N D   O F   F I L E
----------------------------------------------------------------------------------------------------
\ No newline at end of file
+--_________________________________________________________________________________________________
+--                                                                                                |
+--                                           |TDC core|                                           |
+--                                                                                                |
+--                                         CERN,BE/CO-HT                                          |
+--________________________________________________________________________________________________|
+
+---------------------------------------------------------------------------------------------------
+--                                                                                                |
+--                                       start_retrig_ctrl                                        |
+--                                                                                                |
+---------------------------------------------------------------------------------------------------
+-- File         start_retrig_ctrl.vhd                                                             |
+--                                                                                                |
+-- Description  The unit provides the main components for the calculation of the "Coarse time" of |
+--              the final timestamps. These components are sent to the data_formatting unit where |
+--              the actual Coarse time calculation takes place.                                   |
+--                                                                                                |
+--              As a reminder, the final timestamp is a 128-bits word divided in four 32-bits     |
+--              words with the following structure:                                               |
+--                                                                                                |
+--                [127:96]  Timestamp Metadata (ex. Channel, Slope)                               |
+--                                                                                                |
+--                 [95:64]  Local UTC time from the one_hz_generator; each bit represents 1 s     |
+--                                                                                                |
+--                 [63:32]  Coarse time within the current second; each bit represents 8 ns       |
+--                                                                                                |
+--                  [31:0]  Fine time to be added to the Coarse time: provided directly by Acam;  |
+--                          each bit represents 81.03 ps                                          |
+--                                                                                                |
+--              In I-Mode the Acam chip provides unlimited measuring range with internal start    |
+--              retriggers. Acam is programmed to retrigger every (16*acam_clk_period) =          |
+--              (64*clk_i_period) = 512 ns; the StartTimer in Acam Reg 4 is set to 15. It counts  |
+--              the number of retriggers after a Start pulse and upon the arrival of a Stop pulse |
+--              and it sends this number in the "Start#" field of the timestamp.                  |
+--              Unfortunately Acam's counter of the retriggers has only 8 bits and can count up   |
+--              to 256 retriggers. Within one second (our UTC time) there can be up to            |
+--              1,953,125 retriggers, which is >> 256 and actually corresponds to 7629 overflows  |
+--              of the Acam counter. Therefore there is the need to follow Acam and keep track of |
+--              the overflows. The Acam Interrupt flag (IrFlag pin 59) has been set to follow the |
+--              highest bit of the Start# (through the Acam Reg 12 bit 26) and like this we       |
+--              manage to count retriggers synchronously to Acam itself.                          |
+--              For simplification, in the following figure we assume that two Stop signals arrive|
+--              after less than 256 Acam internal retriggers. Therefore in the timestamps that    |
+--              Acam will give the Start# field will represent the exact amount of retriggers     |
+--              after the Start pulse.                                                            |
+--              Note that the interval between this external Start pulse and the first internal   |
+--              retrigger may vary; it is measured by the Acam chip and stored as Start01 in Acam |
+--              Reg 10. Moreover, there is the StartOff1 offset added to each Hit time by Acam    |
+--              (this does not appear in this figure) made available in Acam Reg 5.               |
+--              However, in this TDC core application we are only interested in time differences  |
+--              between Stop pulses (ex. Stop2 - Stop1) and not in the precise arrival time of a  |
+--              Stop pulse. Since now both Start01 and StartOff1 are stable numbers affecting     |
+--              equally all the Stop pulses, they would disappear during the subtraction (which   |
+--              takes place at the software side) and therefore thay are used in our calculations.|
+--                                                                                                |
+-- Start        ____|-|__________________________________________________________________________ |
+-- Retriggers   ________________|-|________________|-|________________|-|________________|-|_____ |
+-- Stop1        _________________________________________________|-|_____________________________ |
+-- Hit1                                            <------------->
+-- Stop2        _____________________________________________________________________________|-|_ |
+-- Hit2                                                                                   <-->    |
+-- Start01          <---------->                                                                  |
+--                                                                                                |
+--              Coming back now to our timestamp format {UTC second, Coarse time, Fine time}, we  |
+--              have to somehow assosiate ACAM retriggers to the UTC time. Actually, Acam has no  |
+--              knowledge of the UTC time and the arrival of a new second happens completely      |
+--              independently. As the following figure shows the final timestamp of a Stop pulse  |
+--              is defined by the current UTC time plus the amount of time between that UTC and   |
+--              the Stop pulse: (2)+(3). Part (3) is provided exclusively by the Acam chip in the |
+--              Start# and Hit time fields of the timestamp. The sum of (1)+(2) is multiples of   |
+--              256 Acam retriggers and can be defined by following the Acam output IrFlag.       |
+--              Now Part (1), is the one that associates the arrival of a UTC second with the Acam|
+--              time counting and is defined in this unit by following the Acam retriggers.       |
+--                                                                                                |
+-- IrFlag     ______________|--------------|______________|-------------|... _____________|---    |
+--             ___________________________  ___________________________       _____________       |
+-- new UTC sec|               _|-|_       ||                           |     |                    |
+-- Stop1      |                           ||                           | ... |      _|-|_         |
+--            |___________________________||___________________________|     |______________      |
+--                    (1)                                                                         |
+--            |----------------|                                                                  |
+--                                                  (2)                                           |
+--                             |---------------------------------------------|                    |
+--                                                                              (3)               |
+--                                                                           |-------|            |
+--                                                                                                |
+--              To conclude, the final Coarse time is: (Part(2) + Part(3)_Start#)*Retrigger period|
+--              and the  Fine time is : Part(3)_Hit                                               |
+--                                                                                                |
+--                                                                                                |
+-- Authors      Gonzalo Penacoba  (Gonzalo.Penacoba@cern.ch)                                      |
+--              Evangelia Gousiou (Evangelia.Gousiou@cern.ch)                                     |
+-- Date         04/2012                                                                           |
+-- Version      v0.11                                                                             |
+-- Depends on                                                                                     |
+--                                                                                                |
+----------------                                                                                  |
+-- Last changes                                                                                   |
+--     07/2011  v0.1  GP  First version                                                           |
+--     04/2012  v0.11 EG  Revamping; Comments added, signals renamed                              |
+---------------------------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------------------------------
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                |
+--                              ------------------------------------                              |
+-- This source file is free software; you can redistribute it and/or modify it under the terms of |
+-- the GNU Lesser General Public License as published by the Free Software Foundation; either     |
+-- version 2.1 of the License, or (at your option) any later version.                             |
+-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;       |
+-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.      |
+-- See the GNU Lesser General Public License for more details.                                    |
+-- You should have received a copy of the GNU Lesser General Public License along with this       |
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html                     |
+---------------------------------------------------------------------------------------------------
+
+
+
+--=================================================================================================
+--                                       Libraries & Packages
+--=================================================================================================
+
+-- Standard library
+library IEEE;
+use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
+use IEEE.NUMERIC_STD.all;    -- conversion functions-- Specific library
+-- Specific library
+library work;
+use work.tdc_core_pkg.all;   -- definitions of types, constants, entities
+
+
+--=================================================================================================
+--                            Entity declaration for start_retrig_ctrl
+--=================================================================================================
+
+entity start_retrig_ctrl is
+  generic
+    (g_width                 : integer := 32);
+  port
+  -- INPUTS
+     -- Signal from the clk_rst_manager
+    (clk_i                   : in std_logic;
+     rst_i                   : in std_logic;
+
+     -- Signal from the acam_timecontrol_interface
+     acam_intflag_f_edge_p_i : in std_logic;
+
+     -- Signal from the one_hz_generator unit
+     one_hz_p_i              : in std_logic;
+
+
+  -- OUTPUTS
+     -- Signals to the data_formatting unit
+     roll_over_incr_recent_o : out std_logic;
+     clk_i_cycles_offset_o   : out std_logic_vector(g_width-1 downto 0);
+     roll_over_nb_o          : out std_logic_vector(g_width-1 downto 0);
+     retrig_nb_offset_o      : out std_logic_vector(g_width-1 downto 0));
+
+end start_retrig_ctrl;
+
+--=================================================================================================
+--                                    architecture declaration
+--=================================================================================================
+
+architecture rtl of start_retrig_ctrl is
+
+  signal clk_i_cycles_offset : std_logic_vector(g_width-1 downto 0);
+  signal current_cycles      : std_logic_vector(g_width-1 downto 0);
+  signal current_retrig_nb   : std_logic_vector(g_width-1 downto 0);
+  signal retrig_nb_offset    : std_logic_vector(g_width-1 downto 0);
+  signal retrig_p            : std_logic;
+  signal roll_over_c         : std_logic_vector(g_width-1 downto 0);
+
+--=================================================================================================
+--                                       architecture begin
+--=================================================================================================
+begin
+
+-- retrigger #      :   0    1          127  128        255  256  257        383  384  385         511  512  513
+-- retriggers       :  _|____|____...____|____|____...____|____|____|____...___|____|____|____...____|____|____|___
+-- IrFlag           :  __________________|---------------------|____________________|---------------------|________
+-- IrFlag_f_edge_p  :  ______________________________________|-|________________________________________|-|________
+-- retrig_p         : |-|__|-|__ ... __|-|__|-|__ ... __|-|__|-|__|-|__ ...__|-|__|-|__|-|___ ...__|-|__|-|__|-|___
+-- current_retrig_nb:  0    1          127  128         255   0    1         127  128  129         255   0    1
+
+-- one_hz_p_i       : _____________________|-|_______________________________________________________________
+-- roll_over_c      :                       0                 1                                          2
+-- retrig_nb_offset :                      127
+-- clk_i_cycles_offs:                      |..| (counts clk_i cycles from the pulse to the end of this retrigger) 
+--
+-- At the moment that a new second arrives through the one_hz_p_i, we:
+--  o keep note of the current_retrig_nb, 127 in this case (stored in retrig_nb_offset)
+--  o keep note of the current_cycles, that is the number of clk_i cycles between the one_hz_p_i
+--    and the next (128th) retrigger (stored in clk_i_cycles_offset)
+--  o reinitialize the roll_over_c counter which starts counting rollovers of the current_retrig_nb
+--
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+-- In this more macroscopic example we have included a Stop pulse arriving to the ACAM chip.
+-- Each one of the n boxes represents 256 ACAM internal retriggers, which through the IrFlag are
+-- synchronous with the counters in this unit. The coarse time is the amount of clk_i cycles
+-- between the one_hz_p_i pulse and the ACAM Stop pulse. To the coarse time we then have to add the
+-- fine time, which is the very precise 81ps resolution time measured by the ACAM. Note that the
+-- ACAM can only provide timing information within the last box: the Start# (bits 25:18) indicates
+-- the amount of internal retriggers and the Hit (bits 16:0) indicates the fine timing. The time
+-- difference between the one_hz_p_i pulse and the last box is calculated through the counters of
+-- this unit: roll_over_c, retrig_nb_offset, clk_i_cycles_offset.
+
+-- Note that since the counting in the roll_over_c starts from 0, we do not need to subtract 1
+-- so as not to consider the last, n-th, box. Similarly, for the retrig_nb_offset and ACAM Start#,
+-- to calculate the amount of complete retriggers that have preceded the arrival of the
+-- one_hz_p_i and the Stop pulse respectively, we would have to subtract 1, but since counting
+-- starts from zero, we don't.
+-- Finally, note that the the current_cycles counter is a decreasing counter giving the amount of
+-- clk_i cycles between the resing edge of the one_hz_pulse_i and the next retrigger. 
+-- Note that in this project we are only interested in time differences between 
+
+--                    _______________________________________  _________________________________________       ____________________
+-- one_hz_p_i        |                           _|-|_       ||                                         |     |
+-- ACAM Stop pulse   |                                       ||                                         |     |       _|-|_
+--                   |                                       ||                                         | ... |                    
+-- roll_over_c       |                             0         ||1                                        |     |n-1                    
+--                   |_______________________________________||_________________________________________|     |____________________
+--                                (1)
+--                   |----------------------------|
+--                                                                             (2)
+--                                                |-----------------------------------------------------------|
+--                                                                                                                (3)
+--                                                                                                            |--------|
+
+--                  (1): ((retrig_nb_offset + 1) * retrig_period) - (clk_i_cycles_offset)
+--                  (2): (roll_over_c * 256 * retrig_period) - (the amount that (1) represents)
+--                  (3): from ACAM tstamps: (Start# * retrig_period) + (Fine time: Hit)
+
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+-- These two counters keep a track of the current internal start retrigger
+-- of the Acam in parallel with the Acam itself. Counting up to c_ACAM_RETRIG_PERIOD = 64
+
+ retrig_period_counter: free_counter  -- retrigger periods
+   generic map
+     (width             => g_width)
+   port map
+     (clk_i             => clk_i,
+      rst_i             => acam_intflag_f_edge_p_i,
+      counter_en_i      => '1',
+      counter_top_i     => c_ACAM_RETRIG_PERIOD,
+     -------------------------------------------
+      counter_is_zero_o => retrig_p,
+      counter_o         => current_cycles);
+     -------------------------------------------
+
+  retrig_nb_counter: incr_counter    -- number of retriggers counting from 0 to 255 and restarting
+    generic map                      -- through the acam_intflag_f_edge_p_i
+      (width             => g_width)
+    port map
+      (clk_i             => clk_i,
+       rst_i             => acam_intflag_f_edge_p_i,  
+       counter_top_i     => x"00000100",
+       counter_incr_en_i => retrig_p,
+       counter_is_full_o => open,
+     -------------------------------------------
+       counter_o         => current_retrig_nb);
+     -------------------------------------------
+
+
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+  -- This counter keeps track of the number of overflows of the Acam counter within one second
+  roll_over_counter: incr_counter
+    generic map
+      (width             => g_width)
+    port map
+      (clk_i             => clk_i,
+       rst_i             => one_hz_p_i,  
+       counter_top_i     => x"FFFFFFFF",
+       counter_incr_en_i => acam_intflag_f_edge_p_i,
+       counter_is_full_o => open,
+       counter_o         => roll_over_c);
+
+
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+  -- When a new second starts, all values are captured and stored as offsets.
+  -- when a timestamps arrives, these offset will be subrstracted in order
+  -- to base the final timestamp with respect to the current second.
+  capture_offset: process (clk_i)
+  begin
+    if rising_edge (clk_i) then
+      if rst_i ='1' then
+        clk_i_cycles_offset <= (others=>'0');
+        retrig_nb_offset    <= (others=>'0');
+
+      elsif one_hz_p_i = '1' then
+        clk_i_cycles_offset <= current_cycles;
+        retrig_nb_offset    <= current_retrig_nb;
+      end if;
+
+    end if;
+  end process;
+
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --    
+    
+  -- outputs
+  roll_over_incr_recent_o <= '1' when unsigned(current_retrig_nb) < 64 else '0';
+  clk_i_cycles_offset_o   <= clk_i_cycles_offset;
+  retrig_nb_offset_o      <= retrig_nb_offset;
+  roll_over_nb_o          <= roll_over_c;
+
+
+
+end architecture rtl;
+--=================================================================================================
+--                                        architecture end
+--=================================================================================================
+---------------------------------------------------------------------------------------------------
+--                                      E N D   O F   F I L E
+---------------------------------------------------------------------------------------------------
diff --git a/hdl/svec/hdl/rtl/tdc_core_pkg.vhd b/hdl/svec/hdl/rtl/tdc_core_pkg.vhd
index 9908cb95745d81424d9539016fb6f0d48e9c76fc..712d1e8ce318228928f238d8192fad4ac329492c 100644
--- a/hdl/svec/hdl/rtl/tdc_core_pkg.vhd
+++ b/hdl/svec/hdl/rtl/tdc_core_pkg.vhd
@@ -75,7 +75,7 @@ package tdc_core_pkg is
      wbd_width     => x"4",                  -- 32-bit port granularity
      sdb_component =>
        (addr_first  => x"0000000000000000",
-        addr_last   => x"000000000000007F",
+        addr_last   => x"0000000000000FFF",
         product     =>
           (vendor_id => x"000000000000CE42", -- CERN
            device_id => x"00000601",
@@ -295,7 +295,7 @@ package tdc_core_pkg is
 ---------------------------------------------------------------------------------------------------
 --                            Constants regarding the Circular Buffer                            --
 ---------------------------------------------------------------------------------------------------
-  constant c_CIRCULAR_BUFF_SIZE : unsigned(31 downto 0) := x"00000100";
+  constant c_CIRCULAR_BUFF_SIZE : unsigned(7 downto 0) := "11111111";
 
 
 ---------------------------------------------------------------------------------------------------
@@ -681,6 +681,7 @@ package tdc_core_pkg is
        retrig_nb_offset_i      : in std_logic_vector(31 downto 0);
        one_hz_p_i              : in std_logic;
       ----------------------------------------------------------------------
+       tdc_led_5_o             : out std_logic;
        tstamp_wr_wb_adr_o      : out std_logic_vector(7 downto 0);
        tstamp_wr_wb_cyc_o      : out std_logic;
        tstamp_wr_dat_o         : out std_logic_vector(127 downto 0);
@@ -802,6 +803,7 @@ package tdc_core_pkg is
        rst_i            : in std_logic;
        one_hz_p_i       : in std_logic;
        acam_inputs_en_i : in std_logic_vector(g_width-1 downto 0);
+       fordebug_i       : in std_logic;
       ----------------------------------------------------------------------
        tdc_led_status_o : out std_logic;
        tdc_led_trig1_o  : out std_logic;
diff --git a/hdl/svec/hdl/rtl/top_tdc.vhd b/hdl/svec/hdl/rtl/top_tdc.vhd
index bd8ca77844f1399b62cec924a97bb24d7d291f55..3fffb802719f495c700c22f1c0b50adbbc6e435e 100644
--- a/hdl/svec/hdl/rtl/top_tdc.vhd
+++ b/hdl/svec/hdl/rtl/top_tdc.vhd
@@ -189,13 +189,13 @@ architecture rtl of top_tdc is
   constant c_SLAVE_TDC       : integer := 3;  -- TIMETAG core for time-tagging
 
   constant c_SDB_ADDRESS         : t_wishbone_address := x"00000000";
-  constant c_FMC_TDC_SDB_BRIDGE  : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00002000");
+  constant c_FMC_TDC_SDB_BRIDGE  : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00040000");
                                                                        -- (   size    ,   sdb_addr )
   constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(6 downto 0) :=
-    (0 => f_sdb_embed_device     (c_ONEWIRE_SDB_DEVICE,  x"00001000"),
-     1 => f_sdb_embed_device     (c_SPEC_CSR_SDB_DEVICE, x"00001100"),
-     2 => f_sdb_embed_device     (c_INT_SDB_DEVICE,      x"00001200"),
-     3 => f_sdb_embed_bridge     (c_FMC_TDC_SDB_BRIDGE,  x"00002000"),
+    (0 => f_sdb_embed_device     (c_ONEWIRE_SDB_DEVICE,  x"00010000"),
+     1 => f_sdb_embed_device     (c_SPEC_CSR_SDB_DEVICE, x"00020000"),
+     2 => f_sdb_embed_device     (c_INT_SDB_DEVICE,      x"00030000"),
+     3 => f_sdb_embed_bridge     (c_FMC_TDC_SDB_BRIDGE,  x"00040000"),
      4 => f_sdb_embed_repo_url   (c_SDB_REPO_URL),
      5 => f_sdb_embed_synthesis  (c_SDB_SYNTHESIS),
      6 => f_sdb_embed_integration(c_SDB_INTEGRATION));
diff --git a/hdl/svec/ucf/svec_tdc.ucf b/hdl/svec/ucf/svec_tdc.ucf
index ee592204ca1bec4d751726b45d92a1b800a09820..d5411ec76dea22e99beb760d1353ddd2705657b0 100644
--- a/hdl/svec/ucf/svec_tdc.ucf
+++ b/hdl/svec/ucf/svec_tdc.ucf
@@ -21,6 +21,11 @@ TIMESPEC TS_acam_refclk_p_i = PERIOD "acam_refclk_p_i" 32 ns HIGH 50%;
 NET "acam_refclk_n_i" TNM_NET = acam_refclk_n_i;
 TIMESPEC TS_acam_refclk_n_i = PERIOD "acam_refclk_n_i" 32 ns HIGH 50%;
 
+NET "clk_62m5_pllxilinx" TNM_NET = "clk_62m5_pllxilinx";
+NET "clk_125m" TNM_NET = "clk_125m";
+TIMESPEC ts_ignore_xclock1 = FROM "clk_62m5_pllxilinx" TO "clk_125m" 20ns DATAPATHONLY;
+TIMESPEC ts_ignore_xclock2 = FROM "clk_125m" TO "clk_62m5_pllxilinx" 20ns DATAPATHONLY;
+
 
 #
 # Clock to Clock
@@ -30,6 +35,7 @@ TIMESPEC TS_acam_refclk_n_i = PERIOD "acam_refclk_n_i" 32 ns HIGH 50%;
 # Inputs/Outputs
 #
 
+
 #
 # Registers
 #
diff --git a/hdl/svec/xilinx/top_tdc.bin b/hdl/svec/xilinx/top_tdc.bin
new file mode 100644
index 0000000000000000000000000000000000000000..b5920bb941849df36571ea7b82699cc5f33510b3
Binary files /dev/null and b/hdl/svec/xilinx/top_tdc.bin differ
diff --git a/hdl/svec/xilinx/top_tdc.twr b/hdl/svec/xilinx/top_tdc.twr
index 3bf11d29486a75154e61a69971d16ec375b20456..631419abbff4dcfa665c6a6445315fefb2a8a09e 100644
--- a/hdl/svec/xilinx/top_tdc.twr
+++ b/hdl/svec/xilinx/top_tdc.twr
@@ -34,17 +34,17 @@ For more information, see Period Analysis in the Timing Closure User Guide (UG61
 
  620 paths analyzed, 246 endpoints analyzed, 0 failing endpoints
  0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is   7.101ns.
+ Minimum period is   8.039ns.
 --------------------------------------------------------------------------------
 
-Paths for end point clks_rsts_mgment/pll_cs_n_o (SLICE_X31Y171.SR), 1 path
+Paths for end point clks_rsts_mgment/pll_cs_n_o (SLICE_X31Y189.SR), 1 path
 --------------------------------------------------------------------------------
-Slack (setup path):     42.899ns (requirement - (data path - clock path skew + uncertainty))
+Slack (setup path):     41.961ns (requirement - (data path - clock path skew + uncertainty))
   Source:               clks_rsts_mgment/por_synch_1 (FF)
   Destination:          clks_rsts_mgment/pll_cs_n_o (FF)
   Requirement:          50.000ns
-  Data Path Delay:      7.234ns (Levels of Logic = 0)
-  Clock Path Skew:      0.168ns (0.884 - 0.716)
+  Data Path Delay:      8.233ns (Levels of Logic = 0)
+  Clock Path Skew:      0.229ns (0.943 - 0.714)
   Source Clock:         clk_20m_vcxo rising at 0.000ns
   Destination Clock:    clk_20m_vcxo rising at 50.000ns
   Clock Uncertainty:    0.035ns
@@ -59,25 +59,25 @@ Slack (setup path):     42.899ns (requirement - (data path - clock path skew + u
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X76Y125.BQ     Tcko                  0.447   clks_rsts_mgment/por_synch<1>
+    SLICE_X73Y124.BQ     Tcko                  0.391   clks_rsts_mgment/por_synch<1>
                                                        clks_rsts_mgment/por_synch_1
-    SLICE_X31Y171.SR     net (fanout=17)       6.362   clks_rsts_mgment/por_synch<1>
-    SLICE_X31Y171.CLK    Tsrck                 0.425   clks_rsts_mgment/pll_cs_n_o
+    SLICE_X31Y189.SR     net (fanout=17)       7.441   clks_rsts_mgment/por_synch<1>
+    SLICE_X31Y189.CLK    Tsrck                 0.401   clks_rsts_mgment/pll_cs_n_o
                                                        clks_rsts_mgment/pll_cs_n_o
     -------------------------------------------------  ---------------------------
-    Total                                      7.234ns (0.872ns logic, 6.362ns route)
-                                                       (12.1% logic, 87.9% route)
+    Total                                      8.233ns (0.792ns logic, 7.441ns route)
+                                                       (9.6% logic, 90.4% route)
 
 --------------------------------------------------------------------------------
 
-Paths for end point clks_rsts_mgment/pll_sdi_o (SLICE_X60Y148.B6), 59 paths
+Paths for end point clks_rsts_mgment/pll_sdi_o (SLICE_X49Y156.B6), 59 paths
 --------------------------------------------------------------------------------
-Slack (setup path):     43.423ns (requirement - (data path - clock path skew + uncertainty))
+Slack (setup path):     43.494ns (requirement - (data path - clock path skew + uncertainty))
   Source:               clks_rsts_mgment/dac_bit_index_0 (FF)
   Destination:          clks_rsts_mgment/pll_sdi_o (FF)
   Requirement:          50.000ns
-  Data Path Delay:      6.527ns (Levels of Logic = 4)
-  Clock Path Skew:      -0.015ns (0.241 - 0.256)
+  Data Path Delay:      6.460ns (Levels of Logic = 4)
+  Clock Path Skew:      -0.011ns (0.242 - 0.253)
   Source Clock:         clk_20m_vcxo rising at 0.000ns
   Destination Clock:    clk_20m_vcxo rising at 50.000ns
   Clock Uncertainty:    0.035ns
@@ -92,32 +92,32 @@ Slack (setup path):     43.423ns (requirement - (data path - clock path skew + u
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X63Y147.AQ     Tcko                  0.391   clks_rsts_mgment/dac_bit_index<4>
+    SLICE_X53Y155.AQ     Tcko                  0.391   clks_rsts_mgment/dac_bit_index<4>
                                                        clks_rsts_mgment/dac_bit_index_0
-    SLICE_X82Y139.A3     net (fanout=11)       2.263   clks_rsts_mgment/dac_bit_index<0>
-    SLICE_X82Y139.A      Tilo                  0.205   clks_rsts_mgment/dac_word<11>
-                                                       clks_rsts_mgment/Mmux_dac_bit_being_sent_101
-    SLICE_X85Y140.C3     net (fanout=1)        0.855   clks_rsts_mgment/Mmux_dac_bit_being_sent_101
-    SLICE_X85Y140.C      Tilo                  0.259   clks_rsts_mgment/dac_word<3>
+    SLICE_X75Y150.A1     net (fanout=11)       2.399   clks_rsts_mgment/dac_bit_index<0>
+    SLICE_X75Y150.A      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/dac_word<15>
+                                                       clks_rsts_mgment/Mmux_dac_bit_being_sent_11
+    SLICE_X71Y152.C4     net (fanout=1)        0.762   clks_rsts_mgment/Mmux_dac_bit_being_sent_11
+    SLICE_X71Y152.C      Tilo                  0.259   clks_rsts_mgment/Mmux_dac_bit_being_sent_9
                                                        clks_rsts_mgment/Mmux_bit_being_sent12
-    SLICE_X60Y148.A1     net (fanout=1)        1.944   clks_rsts_mgment/Mmux_bit_being_sent11
-    SLICE_X60Y148.A      Tilo                  0.203   clks_rsts_mgment/pll_sdi_o
+    SLICE_X49Y156.A2     net (fanout=1)        1.691   clks_rsts_mgment/Mmux_bit_being_sent11
+    SLICE_X49Y156.A      Tilo                  0.259   clks_rsts_mgment/pll_sdi_o
                                                        clks_rsts_mgment/Mmux_bit_being_sent15
-    SLICE_X60Y148.B6     net (fanout=1)        0.118   clks_rsts_mgment/Mmux_bit_being_sent14
-    SLICE_X60Y148.CLK    Tas                   0.289   clks_rsts_mgment/pll_sdi_o
+    SLICE_X49Y156.B6     net (fanout=1)        0.118   clks_rsts_mgment/Mmux_bit_being_sent14
+    SLICE_X49Y156.CLK    Tas                   0.322   clks_rsts_mgment/pll_sdi_o
                                                        clks_rsts_mgment/Mmux_bit_being_sent16
                                                        clks_rsts_mgment/pll_sdi_o
     -------------------------------------------------  ---------------------------
-    Total                                      6.527ns (1.347ns logic, 5.180ns route)
-                                                       (20.6% logic, 79.4% route)
+    Total                                      6.460ns (1.490ns logic, 4.970ns route)
+                                                       (23.1% logic, 76.9% route)
 
 --------------------------------------------------------------------------------
-Slack (setup path):     43.693ns (requirement - (data path - clock path skew + uncertainty))
+Slack (setup path):     43.641ns (requirement - (data path - clock path skew + uncertainty))
   Source:               clks_rsts_mgment/dac_bit_index_1 (FF)
   Destination:          clks_rsts_mgment/pll_sdi_o (FF)
   Requirement:          50.000ns
-  Data Path Delay:      6.257ns (Levels of Logic = 4)
-  Clock Path Skew:      -0.015ns (0.241 - 0.256)
+  Data Path Delay:      6.313ns (Levels of Logic = 4)
+  Clock Path Skew:      -0.011ns (0.242 - 0.253)
   Source Clock:         clk_20m_vcxo rising at 0.000ns
   Destination Clock:    clk_20m_vcxo rising at 50.000ns
   Clock Uncertainty:    0.035ns
@@ -132,32 +132,32 @@ Slack (setup path):     43.693ns (requirement - (data path - clock path skew + u
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X63Y147.AMUX   Tshcko                0.461   clks_rsts_mgment/dac_bit_index<4>
+    SLICE_X53Y155.AMUX   Tshcko                0.461   clks_rsts_mgment/dac_bit_index<4>
                                                        clks_rsts_mgment/dac_bit_index_1
-    SLICE_X84Y139.A3     net (fanout=11)       2.084   clks_rsts_mgment/dac_bit_index<1>
-    SLICE_X84Y139.A      Tilo                  0.203   clks_rsts_mgment/dac_word<7>
-                                                       clks_rsts_mgment/Mmux_dac_bit_being_sent_10
-    SLICE_X85Y140.C2     net (fanout=1)        0.696   clks_rsts_mgment/Mmux_dac_bit_being_sent_10
-    SLICE_X85Y140.C      Tilo                  0.259   clks_rsts_mgment/dac_word<3>
+    SLICE_X75Y150.A2     net (fanout=11)       2.182   clks_rsts_mgment/dac_bit_index<1>
+    SLICE_X75Y150.A      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/dac_word<15>
+                                                       clks_rsts_mgment/Mmux_dac_bit_being_sent_11
+    SLICE_X71Y152.C4     net (fanout=1)        0.762   clks_rsts_mgment/Mmux_dac_bit_being_sent_11
+    SLICE_X71Y152.C      Tilo                  0.259   clks_rsts_mgment/Mmux_dac_bit_being_sent_9
                                                        clks_rsts_mgment/Mmux_bit_being_sent12
-    SLICE_X60Y148.A1     net (fanout=1)        1.944   clks_rsts_mgment/Mmux_bit_being_sent11
-    SLICE_X60Y148.A      Tilo                  0.203   clks_rsts_mgment/pll_sdi_o
+    SLICE_X49Y156.A2     net (fanout=1)        1.691   clks_rsts_mgment/Mmux_bit_being_sent11
+    SLICE_X49Y156.A      Tilo                  0.259   clks_rsts_mgment/pll_sdi_o
                                                        clks_rsts_mgment/Mmux_bit_being_sent15
-    SLICE_X60Y148.B6     net (fanout=1)        0.118   clks_rsts_mgment/Mmux_bit_being_sent14
-    SLICE_X60Y148.CLK    Tas                   0.289   clks_rsts_mgment/pll_sdi_o
+    SLICE_X49Y156.B6     net (fanout=1)        0.118   clks_rsts_mgment/Mmux_bit_being_sent14
+    SLICE_X49Y156.CLK    Tas                   0.322   clks_rsts_mgment/pll_sdi_o
                                                        clks_rsts_mgment/Mmux_bit_being_sent16
                                                        clks_rsts_mgment/pll_sdi_o
     -------------------------------------------------  ---------------------------
-    Total                                      6.257ns (1.415ns logic, 4.842ns route)
-                                                       (22.6% logic, 77.4% route)
+    Total                                      6.313ns (1.560ns logic, 4.753ns route)
+                                                       (24.7% logic, 75.3% route)
 
 --------------------------------------------------------------------------------
-Slack (setup path):     43.790ns (requirement - (data path - clock path skew + uncertainty))
+Slack (setup path):     43.929ns (requirement - (data path - clock path skew + uncertainty))
   Source:               clks_rsts_mgment/dac_bit_index_1 (FF)
   Destination:          clks_rsts_mgment/pll_sdi_o (FF)
   Requirement:          50.000ns
-  Data Path Delay:      6.160ns (Levels of Logic = 4)
-  Clock Path Skew:      -0.015ns (0.241 - 0.256)
+  Data Path Delay:      6.025ns (Levels of Logic = 4)
+  Clock Path Skew:      -0.011ns (0.242 - 0.253)
   Source Clock:         clk_20m_vcxo rising at 0.000ns
   Destination Clock:    clk_20m_vcxo rising at 50.000ns
   Clock Uncertainty:    0.035ns
@@ -172,35 +172,35 @@ Slack (setup path):     43.790ns (requirement - (data path - clock path skew + u
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X63Y147.AMUX   Tshcko                0.461   clks_rsts_mgment/dac_bit_index<4>
+    SLICE_X53Y155.AMUX   Tshcko                0.461   clks_rsts_mgment/dac_bit_index<4>
                                                        clks_rsts_mgment/dac_bit_index_1
-    SLICE_X82Y139.A4     net (fanout=11)       1.826   clks_rsts_mgment/dac_bit_index<1>
-    SLICE_X82Y139.A      Tilo                  0.205   clks_rsts_mgment/dac_word<11>
+    SLICE_X69Y150.D2     net (fanout=11)       2.095   clks_rsts_mgment/dac_bit_index<1>
+    SLICE_X69Y150.D      Tilo                  0.259   clks_rsts_mgment/dac_word<11>
                                                        clks_rsts_mgment/Mmux_dac_bit_being_sent_101
-    SLICE_X85Y140.C3     net (fanout=1)        0.855   clks_rsts_mgment/Mmux_dac_bit_being_sent_101
-    SLICE_X85Y140.C      Tilo                  0.259   clks_rsts_mgment/dac_word<3>
+    SLICE_X71Y152.C5     net (fanout=1)        0.561   clks_rsts_mgment/Mmux_dac_bit_being_sent_101
+    SLICE_X71Y152.C      Tilo                  0.259   clks_rsts_mgment/Mmux_dac_bit_being_sent_9
                                                        clks_rsts_mgment/Mmux_bit_being_sent12
-    SLICE_X60Y148.A1     net (fanout=1)        1.944   clks_rsts_mgment/Mmux_bit_being_sent11
-    SLICE_X60Y148.A      Tilo                  0.203   clks_rsts_mgment/pll_sdi_o
+    SLICE_X49Y156.A2     net (fanout=1)        1.691   clks_rsts_mgment/Mmux_bit_being_sent11
+    SLICE_X49Y156.A      Tilo                  0.259   clks_rsts_mgment/pll_sdi_o
                                                        clks_rsts_mgment/Mmux_bit_being_sent15
-    SLICE_X60Y148.B6     net (fanout=1)        0.118   clks_rsts_mgment/Mmux_bit_being_sent14
-    SLICE_X60Y148.CLK    Tas                   0.289   clks_rsts_mgment/pll_sdi_o
+    SLICE_X49Y156.B6     net (fanout=1)        0.118   clks_rsts_mgment/Mmux_bit_being_sent14
+    SLICE_X49Y156.CLK    Tas                   0.322   clks_rsts_mgment/pll_sdi_o
                                                        clks_rsts_mgment/Mmux_bit_being_sent16
                                                        clks_rsts_mgment/pll_sdi_o
     -------------------------------------------------  ---------------------------
-    Total                                      6.160ns (1.417ns logic, 4.743ns route)
-                                                       (23.0% logic, 77.0% route)
+    Total                                      6.025ns (1.560ns logic, 4.465ns route)
+                                                       (25.9% logic, 74.1% route)
 
 --------------------------------------------------------------------------------
 
-Paths for end point clks_rsts_mgment/sclk (SLICE_X54Y154.SR), 1 path
+Paths for end point clks_rsts_mgment/sclk (SLICE_X48Y160.SR), 1 path
 --------------------------------------------------------------------------------
-Slack (setup path):     44.882ns (requirement - (data path - clock path skew + uncertainty))
+Slack (setup path):     44.453ns (requirement - (data path - clock path skew + uncertainty))
   Source:               clks_rsts_mgment/por_synch_1 (FF)
   Destination:          clks_rsts_mgment/sclk (FF)
   Requirement:          50.000ns
-  Data Path Delay:      5.157ns (Levels of Logic = 0)
-  Clock Path Skew:      0.074ns (0.790 - 0.716)
+  Data Path Delay:      5.687ns (Levels of Logic = 0)
+  Clock Path Skew:      0.175ns (0.889 - 0.714)
   Source Clock:         clk_20m_vcxo rising at 0.000ns
   Destination Clock:    clk_20m_vcxo rising at 50.000ns
   Clock Uncertainty:    0.035ns
@@ -215,27 +215,27 @@ Slack (setup path):     44.882ns (requirement - (data path - clock path skew + u
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X76Y125.BQ     Tcko                  0.447   clks_rsts_mgment/por_synch<1>
+    SLICE_X73Y124.BQ     Tcko                  0.391   clks_rsts_mgment/por_synch<1>
                                                        clks_rsts_mgment/por_synch_1
-    SLICE_X54Y154.SR     net (fanout=17)       4.266   clks_rsts_mgment/por_synch<1>
-    SLICE_X54Y154.CLK    Tsrck                 0.444   clks_rsts_mgment/sclk
+    SLICE_X48Y160.SR     net (fanout=17)       4.854   clks_rsts_mgment/por_synch<1>
+    SLICE_X48Y160.CLK    Tsrck                 0.442   clks_rsts_mgment/sclk
                                                        clks_rsts_mgment/sclk
     -------------------------------------------------  ---------------------------
-    Total                                      5.157ns (0.891ns logic, 4.266ns route)
-                                                       (17.3% logic, 82.7% route)
+    Total                                      5.687ns (0.833ns logic, 4.854ns route)
+                                                       (14.6% logic, 85.4% route)
 
 --------------------------------------------------------------------------------
 
 Hold Paths: TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_20m_vcxo_i" 50 ns HIGH 50%;
 --------------------------------------------------------------------------------
 
-Paths for end point clks_rsts_mgment/config_st_FSM_FFd1 (SLICE_X62Y147.CX), 1 path
+Paths for end point clks_rsts_mgment/config_st_FSM_FFd1 (SLICE_X50Y155.CX), 1 path
 --------------------------------------------------------------------------------
-Slack (hold path):      0.415ns (requirement - (clock path skew + uncertainty - data path))
+Slack (hold path):      0.418ns (requirement - (clock path skew + uncertainty - data path))
   Source:               clks_rsts_mgment/config_st_FSM_FFd1 (FF)
   Destination:          clks_rsts_mgment/config_st_FSM_FFd1 (FF)
   Requirement:          0.000ns
-  Data Path Delay:      0.415ns (Levels of Logic = 1)
+  Data Path Delay:      0.418ns (Levels of Logic = 1)
   Clock Path Skew:      0.000ns
   Source Clock:         clk_20m_vcxo rising at 50.000ns
   Destination Clock:    clk_20m_vcxo rising at 50.000ns
@@ -245,71 +245,71 @@ Slack (hold path):      0.415ns (requirement - (clock path skew + uncertainty -
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X62Y147.CQ     Tcko                  0.200   clks_rsts_mgment/config_st_FSM_FFd1
+    SLICE_X50Y155.CQ     Tcko                  0.200   clks_rsts_mgment/config_st_FSM_FFd1
                                                        clks_rsts_mgment/config_st_FSM_FFd1
-    SLICE_X62Y147.CX     net (fanout=20)       0.109   clks_rsts_mgment/config_st_FSM_FFd1
-    SLICE_X62Y147.CLK    Tckdi       (-Th)    -0.106   clks_rsts_mgment/config_st_FSM_FFd1
+    SLICE_X50Y155.CX     net (fanout=20)       0.112   clks_rsts_mgment/config_st_FSM_FFd1
+    SLICE_X50Y155.CLK    Tckdi       (-Th)    -0.106   clks_rsts_mgment/config_st_FSM_FFd1
                                                        clks_rsts_mgment/config_st_FSM_FFd1-In3
                                                        clks_rsts_mgment/config_st_FSM_FFd1
     -------------------------------------------------  ---------------------------
-    Total                                      0.415ns (0.306ns logic, 0.109ns route)
-                                                       (73.7% logic, 26.3% route)
+    Total                                      0.418ns (0.306ns logic, 0.112ns route)
+                                                       (73.2% logic, 26.8% route)
 
 --------------------------------------------------------------------------------
 
-Paths for end point clks_rsts_mgment/sclk (SLICE_X54Y154.A6), 1 path
+Paths for end point clks_rsts_mgment/config_st_FSM_FFd2 (SLICE_X50Y155.A6), 1 path
 --------------------------------------------------------------------------------
-Slack (hold path):      0.424ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               clks_rsts_mgment/sclk (FF)
-  Destination:          clks_rsts_mgment/sclk (FF)
+Slack (hold path):      0.433ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               clks_rsts_mgment/config_st_FSM_FFd2 (FF)
+  Destination:          clks_rsts_mgment/config_st_FSM_FFd2 (FF)
   Requirement:          0.000ns
-  Data Path Delay:      0.424ns (Levels of Logic = 1)
+  Data Path Delay:      0.433ns (Levels of Logic = 1)
   Clock Path Skew:      0.000ns
   Source Clock:         clk_20m_vcxo rising at 50.000ns
   Destination Clock:    clk_20m_vcxo rising at 50.000ns
   Clock Uncertainty:    0.000ns
 
-  Minimum Data Path at Fast Process Corner: clks_rsts_mgment/sclk to clks_rsts_mgment/sclk
+  Minimum Data Path at Fast Process Corner: clks_rsts_mgment/config_st_FSM_FFd2 to clks_rsts_mgment/config_st_FSM_FFd2
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X54Y154.AQ     Tcko                  0.200   clks_rsts_mgment/sclk
-                                                       clks_rsts_mgment/sclk
-    SLICE_X54Y154.A6     net (fanout=10)       0.034   clks_rsts_mgment/sclk
-    SLICE_X54Y154.CLK    Tah         (-Th)    -0.190   clks_rsts_mgment/sclk
-                                                       clks_rsts_mgment/sclk_INV_39_o1_INV_0
-                                                       clks_rsts_mgment/sclk
+    SLICE_X50Y155.AQ     Tcko                  0.200   clks_rsts_mgment/config_st_FSM_FFd1
+                                                       clks_rsts_mgment/config_st_FSM_FFd2
+    SLICE_X50Y155.A6     net (fanout=20)       0.043   clks_rsts_mgment/config_st_FSM_FFd2
+    SLICE_X50Y155.CLK    Tah         (-Th)    -0.190   clks_rsts_mgment/config_st_FSM_FFd1
+                                                       clks_rsts_mgment/config_st_FSM_FFd2-In
+                                                       clks_rsts_mgment/config_st_FSM_FFd2
     -------------------------------------------------  ---------------------------
-    Total                                      0.424ns (0.390ns logic, 0.034ns route)
-                                                       (92.0% logic, 8.0% route)
+    Total                                      0.433ns (0.390ns logic, 0.043ns route)
+                                                       (90.1% logic, 9.9% route)
 
 --------------------------------------------------------------------------------
 
-Paths for end point clks_rsts_mgment/config_st_FSM_FFd2 (SLICE_X62Y147.A6), 1 path
+Paths for end point clks_rsts_mgment/pll_byte_index_0 (SLICE_X49Y154.A6), 1 path
 --------------------------------------------------------------------------------
-Slack (hold path):      0.430ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               clks_rsts_mgment/config_st_FSM_FFd2 (FF)
-  Destination:          clks_rsts_mgment/config_st_FSM_FFd2 (FF)
+Slack (hold path):      0.458ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               clks_rsts_mgment/pll_byte_index_0 (FF)
+  Destination:          clks_rsts_mgment/pll_byte_index_0 (FF)
   Requirement:          0.000ns
-  Data Path Delay:      0.430ns (Levels of Logic = 1)
+  Data Path Delay:      0.458ns (Levels of Logic = 1)
   Clock Path Skew:      0.000ns
   Source Clock:         clk_20m_vcxo rising at 50.000ns
   Destination Clock:    clk_20m_vcxo rising at 50.000ns
   Clock Uncertainty:    0.000ns
 
-  Minimum Data Path at Fast Process Corner: clks_rsts_mgment/config_st_FSM_FFd2 to clks_rsts_mgment/config_st_FSM_FFd2
+  Minimum Data Path at Fast Process Corner: clks_rsts_mgment/pll_byte_index_0 to clks_rsts_mgment/pll_byte_index_0
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X62Y147.AQ     Tcko                  0.200   clks_rsts_mgment/config_st_FSM_FFd1
-                                                       clks_rsts_mgment/config_st_FSM_FFd2
-    SLICE_X62Y147.A6     net (fanout=20)       0.040   clks_rsts_mgment/config_st_FSM_FFd2
-    SLICE_X62Y147.CLK    Tah         (-Th)    -0.190   clks_rsts_mgment/config_st_FSM_FFd1
-                                                       clks_rsts_mgment/config_st_FSM_FFd2-In
-                                                       clks_rsts_mgment/config_st_FSM_FFd2
+    SLICE_X49Y154.AQ     Tcko                  0.198   clks_rsts_mgment/pll_byte_index<3>
+                                                       clks_rsts_mgment/pll_byte_index_0
+    SLICE_X49Y154.A6     net (fanout=20)       0.045   clks_rsts_mgment/pll_byte_index<0>
+    SLICE_X49Y154.CLK    Tah         (-Th)    -0.215   clks_rsts_mgment/pll_byte_index<3>
+                                                       clks_rsts_mgment/Mcount_pll_byte_index_xor<0>11_INV_0
+                                                       clks_rsts_mgment/pll_byte_index_0
     -------------------------------------------------  ---------------------------
-    Total                                      0.430ns (0.390ns logic, 0.040ns route)
-                                                       (90.7% logic, 9.3% route)
+    Total                                      0.458ns (0.413ns logic, 0.045ns route)
+                                                       (90.2% logic, 9.8% route)
 
 --------------------------------------------------------------------------------
 
@@ -326,17 +326,17 @@ Slack: 48.270ns (period - min period limit)
 Slack: 49.570ns (period - min period limit)
   Period: 50.000ns
   Min period limit: 0.430ns (2325.581MHz) (Tcp)
-  Physical resource: clks_rsts_mgment/sclk/CLK
-  Logical resource: clks_rsts_mgment/sclk/CK
-  Location pin: SLICE_X54Y154.CLK
+  Physical resource: clks_rsts_mgment/rst_cnt<3>/CLK
+  Logical resource: clks_rsts_mgment/rst_cnt_0/CK
+  Location pin: SLICE_X66Y125.CLK
   Clock network: clk_20m_vcxo
 --------------------------------------------------------------------------------
 Slack: 49.570ns (period - min period limit)
   Period: 50.000ns
   Min period limit: 0.430ns (2325.581MHz) (Tcp)
-  Physical resource: clks_rsts_mgment/pll_byte_index<6>/CLK
-  Logical resource: clks_rsts_mgment/pll_byte_index_4/CK
-  Location pin: SLICE_X58Y146.CLK
+  Physical resource: clks_rsts_mgment/rst_cnt<3>/CLK
+  Logical resource: clks_rsts_mgment/rst_cnt_1/CK
+  Location pin: SLICE_X66Y125.CLK
   Clock network: clk_20m_vcxo
 --------------------------------------------------------------------------------
 
@@ -375,7 +375,7 @@ Slack: 4.876ns (period - min period limit)
   Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
   Physical resource: tdc_board/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
   Logical resource: tdc_board/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
-  Location pin: RAMB16_X3Y82.CLKA
+  Location pin: RAMB16_X3Y84.CLKA
   Clock network: clk_125m
 --------------------------------------------------------------------------------
 
@@ -384,19 +384,19 @@ Timing constraint: TS_tdc_125m_clk_n_i = PERIOD TIMEGRP "tdc_125m_clk_n_i" 8 ns
 HIGH 50%;
 For more information, see Period Analysis in the Timing Closure User Guide (UG612).
 
- 1041148 paths analyzed, 9798 endpoints analyzed, 65 failing endpoints
- 65 timing errors detected. (65 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is   8.775ns.
+ 553028 paths analyzed, 10593 endpoints analyzed, 0 failing endpoints
+ 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
+ Minimum period is   7.761ns.
 --------------------------------------------------------------------------------
 
-Paths for end point tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_17 (SLICE_X98Y145.C6), 993 paths
+Paths for end point tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_8 (SLICE_X89Y157.A5), 427 paths
 --------------------------------------------------------------------------------
-Slack (setup path):     -0.775ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 (RAM)
-  Destination:          tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_17 (FF)
+Slack (setup path):     0.239ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_2 (FF)
+  Destination:          tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_8 (FF)
   Requirement:          8.000ns
-  Data Path Delay:      8.726ns (Levels of Logic = 8)
-  Clock Path Skew:      -0.014ns (0.244 - 0.258)
+  Data Path Delay:      7.724ns (Levels of Logic = 7)
+  Clock Path Skew:      -0.002ns (0.244 - 0.246)
   Source Clock:         clk_125m rising at 0.000ns
   Destination Clock:    clk_125m rising at 8.000ns
   Clock Uncertainty:    0.035ns
@@ -407,48 +407,45 @@ Slack (setup path):     -0.775ns (requirement - (data path - clock path skew + u
     Discrete Jitter (DJ):       0.000ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_17
+  Maximum Data Path at Slow Process Corner: tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_2 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_8
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    RAMB16_X3Y72.DOB11   Trcko_DOB_REG         1.600   clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-                                                       clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-    SLICE_X96Y150.B4     net (fanout=21)       1.198   cnx_slave_in[0]_adr<9>
-    SLICE_X96Y150.B      Tilo                  0.205   cmp_sdb_crossbar/crossbar/matrix_old_0_3_1
-                                                       tdc_board/tdc_core/reg_control_block/GND_244_o_reg_adr[7]_equal_10_o11
-    SLICE_X99Y149.B1     net (fanout=34)       0.913   tdc_board/tdc_core/reg_control_block/GND_244_o_reg_adr[7]_equal_10_o1
-    SLICE_X99Y149.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_5<28>
-                                                       tdc_board/tdc_core/reg_control_block/GND_244_o_reg_adr[7]_equal_22_o1
-    SLICE_X99Y148.C4     net (fanout=27)       0.535   tdc_board/tdc_core/reg_control_block/GND_244_o_reg_adr[7]_equal_22_o
-    SLICE_X99Y148.C      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/Mmux_dat_out3409
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out10812
-    SLICE_X99Y148.B1     net (fanout=1)        0.731   tdc_board/tdc_core/reg_control_block/Mmux_dat_out10811
-    SLICE_X99Y148.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/Mmux_dat_out3409
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out10813
-    SLICE_X100Y151.B5    net (fanout=1)        0.586   tdc_board/tdc_core/reg_control_block/Mmux_dat_out10812
-    SLICE_X100Y151.B     Tilo                  0.203   tdc_board/tdc_core/reg_control_block/Mmux_dat_out2414
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out10814
-    SLICE_X100Y151.A5    net (fanout=1)        0.222   tdc_board/tdc_core/reg_control_block/Mmux_dat_out10813
-    SLICE_X100Y151.A     Tilo                  0.203   tdc_board/tdc_core/reg_control_block/Mmux_dat_out2414
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out10815
-    SLICE_X98Y145.D6     net (fanout=1)        0.889   tdc_board/tdc_core/reg_control_block/Mmux_dat_out10814
-    SLICE_X98Y145.D      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<17>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out10817_SW0
-    SLICE_X98Y145.C6     net (fanout=1)        0.118   N2615
-    SLICE_X98Y145.CLK    Tas                   0.341   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<17>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out10817
-                                                       tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_17
+    SLICE_X92Y152.CQ     Tcko                  0.408   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<0>
+                                                       tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_2
+    SLICE_X90Y151.B4     net (fanout=40)       1.486   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<2>
+    SLICE_X90Y151.B      Tilo                  0.203   tdc_board/tdc_core/reg_control_block/acam_config_5<10>
+                                                       tdc_board/tdc_core/reg_control_block/_n0524<7>1
+    SLICE_X93Y155.D4     net (fanout=31)       1.387   tdc_board/tdc_core/reg_control_block/_n0524
+    SLICE_X93Y155.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_7<11>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out36411
+    SLICE_X94Y152.D2     net (fanout=1)        1.056   tdc_board/tdc_core/reg_control_block/Mmux_dat_out36410
+    SLICE_X94Y152.D      Tilo                  0.203   tdc_board/tdc_core/reg_control_block/acam_config_3<31>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out36412
+    SLICE_X91Y157.B6     net (fanout=1)        0.945   tdc_board/tdc_core/reg_control_block/Mmux_dat_out36411
+    SLICE_X91Y157.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_2<23>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out36413
+    SLICE_X91Y157.A5     net (fanout=1)        0.187   tdc_board/tdc_core/reg_control_block/Mmux_dat_out36412
+    SLICE_X91Y157.A      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_2<23>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out36414
+    SLICE_X89Y157.B6     net (fanout=1)        0.304   tdc_board/tdc_core/reg_control_block/Mmux_dat_out36413
+    SLICE_X89Y157.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<8>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out36415
+    SLICE_X89Y157.A5     net (fanout=1)        0.187   tdc_board/tdc_core/reg_control_block/Mmux_dat_out36414
+    SLICE_X89Y157.CLK    Tas                   0.322   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<8>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out36416
+                                                       tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_8
     -------------------------------------------------  ---------------------------
-    Total                                      8.726ns (3.534ns logic, 5.192ns route)
-                                                       (40.5% logic, 59.5% route)
+    Total                                      7.724ns (2.172ns logic, 5.552ns route)
+                                                       (28.1% logic, 71.9% route)
 
 --------------------------------------------------------------------------------
-Slack (setup path):     -0.765ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 (RAM)
-  Destination:          tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_17 (FF)
+Slack (setup path):     0.461ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               clks_crossing_125M_62M5/mfifo/ram/Mram_ram1 (RAM)
+  Destination:          tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_8 (FF)
   Requirement:          8.000ns
-  Data Path Delay:      8.716ns (Levels of Logic = 7)
-  Clock Path Skew:      -0.014ns (0.244 - 0.258)
+  Data Path Delay:      7.497ns (Levels of Logic = 6)
+  Clock Path Skew:      -0.007ns (0.244 - 0.251)
   Source Clock:         clk_125m rising at 0.000ns
   Destination Clock:    clk_125m rising at 8.000ns
   Clock Uncertainty:    0.035ns
@@ -459,45 +456,42 @@ Slack (setup path):     -0.765ns (requirement - (data path - clock path skew + u
     Discrete Jitter (DJ):       0.000ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_17
+  Maximum Data Path at Slow Process Corner: clks_crossing_125M_62M5/mfifo/ram/Mram_ram1 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_8
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    RAMB16_X3Y72.DOB4    Trcko_DOB_REG         1.600   clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-                                                       clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-    SLICE_X95Y149.B6     net (fanout=118)      1.016   cnx_slave_in[0]_adr<2>
-    SLICE_X95Y149.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_7<31>
-                                                       tdc_board/cmp_sdb_crossbar/crossbar/master_oe[0]_adr<2>1
-    SLICE_X96Y150.D2     net (fanout=46)       0.888   tdc_board/cnx_master_out[0]_adr<2>
-    SLICE_X96Y150.D      Tilo                  0.205   cmp_sdb_crossbar/crossbar/matrix_old_0_3_1
-                                                       tdc_board/tdc_core/reg_control_block/_n0657<7>1
-    SLICE_X99Y153.B3     net (fanout=4)        0.971   tdc_board/tdc_core/reg_control_block/_n0657
-    SLICE_X99Y153.B      Tilo                  0.259   tdc_board/tdc_core/data_engine_block/acam_config_rdbk_1<31>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out10311
-    SLICE_X99Y156.B5     net (fanout=28)       0.623   tdc_board/tdc_core/reg_control_block/Mmux_dat_out1031
-    SLICE_X99Y156.B      Tilo                  0.259   tdc_board/tdc_core/data_engine_block/acam_config_rdbk_2<15>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out1085
-    SLICE_X100Y151.A2    net (fanout=1)        0.880   tdc_board/tdc_core/reg_control_block/Mmux_dat_out1084
-    SLICE_X100Y151.A     Tilo                  0.203   tdc_board/tdc_core/reg_control_block/Mmux_dat_out2414
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out10815
-    SLICE_X98Y145.D6     net (fanout=1)        0.889   tdc_board/tdc_core/reg_control_block/Mmux_dat_out10814
-    SLICE_X98Y145.D      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<17>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out10817_SW0
-    SLICE_X98Y145.C6     net (fanout=1)        0.118   N2615
-    SLICE_X98Y145.CLK    Tas                   0.341   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<17>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out10817
-                                                       tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_17
+    RAMB8_X3Y74.DOADO12  Trcko_DOA             1.850   clks_crossing_125M_62M5/mfifo/ram/Mram_ram1
+                                                       clks_crossing_125M_62M5/mfifo/ram/Mram_ram1
+    SLICE_X88Y148.B4     net (fanout=9)        1.495   cnx_slave_in[0]_adr<10>
+    SLICE_X88Y148.B      Tilo                  0.205   N1357
+                                                       cmp_sdb_crossbar/crossbar/master_oe[3]_adr<10>1
+    SLICE_X94Y152.D6     net (fanout=3)        1.022   cnx_master_out[3]_adr<10>
+    SLICE_X94Y152.D      Tilo                  0.203   tdc_board/tdc_core/reg_control_block/acam_config_3<31>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out36412
+    SLICE_X91Y157.B6     net (fanout=1)        0.945   tdc_board/tdc_core/reg_control_block/Mmux_dat_out36411
+    SLICE_X91Y157.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_2<23>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out36413
+    SLICE_X91Y157.A5     net (fanout=1)        0.187   tdc_board/tdc_core/reg_control_block/Mmux_dat_out36412
+    SLICE_X91Y157.A      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_2<23>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out36414
+    SLICE_X89Y157.B6     net (fanout=1)        0.304   tdc_board/tdc_core/reg_control_block/Mmux_dat_out36413
+    SLICE_X89Y157.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<8>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out36415
+    SLICE_X89Y157.A5     net (fanout=1)        0.187   tdc_board/tdc_core/reg_control_block/Mmux_dat_out36414
+    SLICE_X89Y157.CLK    Tas                   0.322   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<8>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out36416
+                                                       tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_8
     -------------------------------------------------  ---------------------------
-    Total                                      8.716ns (3.331ns logic, 5.385ns route)
-                                                       (38.2% logic, 61.8% route)
+    Total                                      7.497ns (3.357ns logic, 4.140ns route)
+                                                       (44.8% logic, 55.2% route)
 
 --------------------------------------------------------------------------------
-Slack (setup path):     -0.759ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 (RAM)
-  Destination:          tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_17 (FF)
+Slack (setup path):     0.491ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_5 (FF)
+  Destination:          tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_8 (FF)
   Requirement:          8.000ns
-  Data Path Delay:      8.710ns (Levels of Logic = 8)
-  Clock Path Skew:      -0.014ns (0.244 - 0.258)
+  Data Path Delay:      7.470ns (Levels of Logic = 8)
+  Clock Path Skew:      -0.004ns (0.244 - 0.248)
   Source Clock:         clk_125m rising at 0.000ns
   Destination Clock:    clk_125m rising at 8.000ns
   Clock Uncertainty:    0.035ns
@@ -508,51 +502,51 @@ Slack (setup path):     -0.759ns (requirement - (data path - clock path skew + u
     Discrete Jitter (DJ):       0.000ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_17
+  Maximum Data Path at Slow Process Corner: tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_5 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_8
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    RAMB16_X3Y72.DOB4    Trcko_DOB_REG         1.600   clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-                                                       clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-    SLICE_X95Y149.B6     net (fanout=118)      1.016   cnx_slave_in[0]_adr<2>
-    SLICE_X95Y149.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_7<31>
-                                                       tdc_board/cmp_sdb_crossbar/crossbar/master_oe[0]_adr<2>1
-    SLICE_X99Y149.B2     net (fanout=46)       1.025   tdc_board/cnx_master_out[0]_adr<2>
-    SLICE_X99Y149.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_5<28>
-                                                       tdc_board/tdc_core/reg_control_block/GND_244_o_reg_adr[7]_equal_22_o1
-    SLICE_X99Y148.C4     net (fanout=27)       0.535   tdc_board/tdc_core/reg_control_block/GND_244_o_reg_adr[7]_equal_22_o
-    SLICE_X99Y148.C      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/Mmux_dat_out3409
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out10812
-    SLICE_X99Y148.B1     net (fanout=1)        0.731   tdc_board/tdc_core/reg_control_block/Mmux_dat_out10811
-    SLICE_X99Y148.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/Mmux_dat_out3409
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out10813
-    SLICE_X100Y151.B5    net (fanout=1)        0.586   tdc_board/tdc_core/reg_control_block/Mmux_dat_out10812
-    SLICE_X100Y151.B     Tilo                  0.203   tdc_board/tdc_core/reg_control_block/Mmux_dat_out2414
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out10814
-    SLICE_X100Y151.A5    net (fanout=1)        0.222   tdc_board/tdc_core/reg_control_block/Mmux_dat_out10813
-    SLICE_X100Y151.A     Tilo                  0.203   tdc_board/tdc_core/reg_control_block/Mmux_dat_out2414
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out10815
-    SLICE_X98Y145.D6     net (fanout=1)        0.889   tdc_board/tdc_core/reg_control_block/Mmux_dat_out10814
-    SLICE_X98Y145.D      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<17>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out10817_SW0
-    SLICE_X98Y145.C6     net (fanout=1)        0.118   N2615
-    SLICE_X98Y145.CLK    Tas                   0.341   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<17>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out10817
-                                                       tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_17
+    SLICE_X90Y150.BQ     Tcko                  0.447   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<6>
+                                                       tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_5
+    SLICE_X92Y150.B4     net (fanout=12)       0.521   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<5>
+    SLICE_X92Y150.B      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<3>
+                                                       tdc_board/tdc_core/reg_control_block/_n0517<7>11
+    SLICE_X90Y151.B5     net (fanout=35)       0.467   tdc_board/tdc_core/reg_control_block/_n0517<7>1
+    SLICE_X90Y151.B      Tilo                  0.203   tdc_board/tdc_core/reg_control_block/acam_config_5<10>
+                                                       tdc_board/tdc_core/reg_control_block/_n0524<7>1
+    SLICE_X93Y155.D4     net (fanout=31)       1.387   tdc_board/tdc_core/reg_control_block/_n0524
+    SLICE_X93Y155.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_7<11>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out36411
+    SLICE_X94Y152.D2     net (fanout=1)        1.056   tdc_board/tdc_core/reg_control_block/Mmux_dat_out36410
+    SLICE_X94Y152.D      Tilo                  0.203   tdc_board/tdc_core/reg_control_block/acam_config_3<31>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out36412
+    SLICE_X91Y157.B6     net (fanout=1)        0.945   tdc_board/tdc_core/reg_control_block/Mmux_dat_out36411
+    SLICE_X91Y157.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_2<23>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out36413
+    SLICE_X91Y157.A5     net (fanout=1)        0.187   tdc_board/tdc_core/reg_control_block/Mmux_dat_out36412
+    SLICE_X91Y157.A      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_2<23>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out36414
+    SLICE_X89Y157.B6     net (fanout=1)        0.304   tdc_board/tdc_core/reg_control_block/Mmux_dat_out36413
+    SLICE_X89Y157.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<8>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out36415
+    SLICE_X89Y157.A5     net (fanout=1)        0.187   tdc_board/tdc_core/reg_control_block/Mmux_dat_out36414
+    SLICE_X89Y157.CLK    Tas                   0.322   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<8>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out36416
+                                                       tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_8
     -------------------------------------------------  ---------------------------
-    Total                                      8.710ns (3.588ns logic, 5.122ns route)
-                                                       (41.2% logic, 58.8% route)
+    Total                                      7.470ns (2.416ns logic, 5.054ns route)
+                                                       (32.3% logic, 67.7% route)
 
 --------------------------------------------------------------------------------
 
-Paths for end point tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_31 (SLICE_X91Y147.C6), 852 paths
+Paths for end point tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_27 (SLICE_X84Y153.C6), 670 paths
 --------------------------------------------------------------------------------
-Slack (setup path):     -0.773ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 (RAM)
-  Destination:          tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_31 (FF)
+Slack (setup path):     0.260ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_5 (FF)
+  Destination:          tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_27 (FF)
   Requirement:          8.000ns
-  Data Path Delay:      8.721ns (Levels of Logic = 10)
-  Clock Path Skew:      -0.017ns (0.241 - 0.258)
+  Data Path Delay:      7.693ns (Levels of Logic = 9)
+  Clock Path Skew:      -0.012ns (0.236 - 0.248)
   Source Clock:         clk_125m rising at 0.000ns
   Destination Clock:    clk_125m rising at 8.000ns
   Clock Uncertainty:    0.035ns
@@ -563,54 +557,51 @@ Slack (setup path):     -0.773ns (requirement - (data path - clock path skew + u
     Discrete Jitter (DJ):       0.000ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_31
+  Maximum Data Path at Slow Process Corner: tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_5 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_27
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    RAMB16_X3Y72.DOB5    Trcko_DOB_REG         1.600   clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-                                                       clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-    SLICE_X97Y146.D6     net (fanout=74)       0.997   cnx_slave_in[0]_adr<3>
-    SLICE_X97Y146.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_4<31>
-                                                       tdc_board/cmp_sdb_crossbar/crossbar/master_oe[0]_adr<3>1_1
-    SLICE_X98Y148.A2     net (fanout=12)       1.047   tdc_board/cmp_sdb_crossbar/crossbar/master_oe[0]_adr<3>1
-    SLICE_X98Y148.A      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/acam_config_1<19>
-                                                       tdc_board/tdc_core/reg_control_block/GND_244_o_reg_adr[7]_equal_4_o1_1
-    SLICE_X98Y147.B3     net (fanout=2)        0.553   tdc_board/tdc_core/reg_control_block/GND_244_o_reg_adr[7]_equal_4_o1
-    SLICE_X98Y147.B      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/GND_244_o_reg_adr[7]_equal_8_o
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29210
-    SLICE_X95Y147.A6     net (fanout=1)        0.579   tdc_board/tdc_core/reg_control_block/Mmux_dat_out2929
-    SLICE_X95Y147.A      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/Mmux_dat_out10810
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29212
-    SLICE_X92Y148.B6     net (fanout=1)        0.328   tdc_board/tdc_core/reg_control_block/Mmux_dat_out29211
-    SLICE_X92Y148.B      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/Mmux_dat_out15610
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29216_SW2
-    SLICE_X92Y148.A5     net (fanout=1)        0.169   N2625
-    SLICE_X92Y148.A      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/Mmux_dat_out15610
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29216
-    SLICE_X91Y148.C6     net (fanout=1)        0.405   tdc_board/tdc_core/reg_control_block/Mmux_dat_out29215
-    SLICE_X91Y148.C      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_10<7>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29221_SW0_SW0
-    SLICE_X91Y148.D5     net (fanout=1)        0.209   N2671
-    SLICE_X91Y148.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_10<7>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29221_SW0
-    SLICE_X91Y147.D6     net (fanout=1)        0.279   N2569
-    SLICE_X91Y147.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29221_SW1
-    SLICE_X91Y147.C6     net (fanout=1)        0.118   N2673
-    SLICE_X91Y147.CLK    Tas                   0.322   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29221
-                                                       tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_31
+    SLICE_X90Y150.BQ     Tcko                  0.447   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<6>
+                                                       tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_5
+    SLICE_X93Y150.B6     net (fanout=12)       0.528   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<5>
+    SLICE_X93Y150.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_2<31>
+                                                       tdc_board/tdc_core/reg_control_block/_n0517<7>11_1
+    SLICE_X97Y149.C3     net (fanout=6)        0.716   tdc_board/tdc_core/reg_control_block/_n0517<7>11
+    SLICE_X97Y149.C      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_4<31>
+                                                       tdc_board/tdc_core/reg_control_block/_n0550<7>1
+    SLICE_X97Y151.A6     net (fanout=30)       0.548   tdc_board/tdc_core/reg_control_block/_n0550
+    SLICE_X97Y151.A      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_8<30>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23610
+    SLICE_X89Y151.D6     net (fanout=1)        1.377   tdc_board/tdc_core/reg_control_block/Mmux_dat_out2369
+    SLICE_X89Y151.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_6<27>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23612
+    SLICE_X89Y151.C6     net (fanout=1)        0.118   tdc_board/tdc_core/reg_control_block/Mmux_dat_out23611
+    SLICE_X89Y151.C      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_6<27>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23613_SW0
+    SLICE_X86Y152.A4     net (fanout=1)        0.788   N1407
+    SLICE_X86Y152.A      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23613
+    SLICE_X86Y152.B4     net (fanout=1)        0.379   tdc_board/tdc_core/reg_control_block/Mmux_dat_out23612
+    SLICE_X86Y152.B      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23615
+    SLICE_X84Y153.D4     net (fanout=1)        0.477   tdc_board/tdc_core/reg_control_block/Mmux_dat_out23614
+    SLICE_X84Y153.D      Tilo                  0.203   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<27>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23617_SW0
+    SLICE_X84Y153.C6     net (fanout=1)        0.118   N1299
+    SLICE_X84Y153.CLK    Tas                   0.289   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<27>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23617
+                                                       tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_27
     -------------------------------------------------  ---------------------------
-    Total                                      8.721ns (4.037ns logic, 4.684ns route)
-                                                       (46.3% logic, 53.7% route)
+    Total                                      7.693ns (2.644ns logic, 5.049ns route)
+                                                       (34.4% logic, 65.6% route)
 
 --------------------------------------------------------------------------------
-Slack (setup path):     -0.721ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 (RAM)
-  Destination:          tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_31 (FF)
+Slack (setup path):     0.261ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_7 (FF)
+  Destination:          tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_27 (FF)
   Requirement:          8.000ns
-  Data Path Delay:      8.669ns (Levels of Logic = 10)
-  Clock Path Skew:      -0.017ns (0.241 - 0.258)
+  Data Path Delay:      7.692ns (Levels of Logic = 9)
+  Clock Path Skew:      -0.012ns (0.236 - 0.248)
   Source Clock:         clk_125m rising at 0.000ns
   Destination Clock:    clk_125m rising at 8.000ns
   Clock Uncertainty:    0.035ns
@@ -621,54 +612,51 @@ Slack (setup path):     -0.721ns (requirement - (data path - clock path skew + u
     Discrete Jitter (DJ):       0.000ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_31
+  Maximum Data Path at Slow Process Corner: tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_7 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_27
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    RAMB16_X3Y72.DOB10   Trcko_DOB_REG         1.600   clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-                                                       clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-    SLICE_X99Y147.D3     net (fanout=20)       1.267   cnx_slave_in[0]_adr<8>
-    SLICE_X99Y147.D      Tilo                  0.259   tdc_board/tdc_core/data_engine_block/acam_start01_o<23>
-                                                       tdc_board/tdc_core/reg_control_block/GND_244_o_reg_adr[7]_equal_10_o11_1
-    SLICE_X97Y148.B1     net (fanout=7)        0.689   tdc_board/tdc_core/reg_control_block/GND_244_o_reg_adr[7]_equal_10_o11
-    SLICE_X97Y148.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_0<31>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out27111_1
-    SLICE_X98Y147.B6     net (fanout=2)        0.535   tdc_board/tdc_core/reg_control_block/Mmux_dat_out27111
-    SLICE_X98Y147.B      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/GND_244_o_reg_adr[7]_equal_8_o
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29210
-    SLICE_X95Y147.A6     net (fanout=1)        0.579   tdc_board/tdc_core/reg_control_block/Mmux_dat_out2929
-    SLICE_X95Y147.A      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/Mmux_dat_out10810
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29212
-    SLICE_X92Y148.B6     net (fanout=1)        0.328   tdc_board/tdc_core/reg_control_block/Mmux_dat_out29211
-    SLICE_X92Y148.B      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/Mmux_dat_out15610
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29216_SW2
-    SLICE_X92Y148.A5     net (fanout=1)        0.169   N2625
-    SLICE_X92Y148.A      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/Mmux_dat_out15610
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29216
-    SLICE_X91Y148.C6     net (fanout=1)        0.405   tdc_board/tdc_core/reg_control_block/Mmux_dat_out29215
-    SLICE_X91Y148.C      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_10<7>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29221_SW0_SW0
-    SLICE_X91Y148.D5     net (fanout=1)        0.209   N2671
-    SLICE_X91Y148.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_10<7>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29221_SW0
-    SLICE_X91Y147.D6     net (fanout=1)        0.279   N2569
-    SLICE_X91Y147.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29221_SW1
-    SLICE_X91Y147.C6     net (fanout=1)        0.118   N2673
-    SLICE_X91Y147.CLK    Tas                   0.322   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29221
-                                                       tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_31
+    SLICE_X90Y150.CQ     Tcko                  0.447   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<6>
+                                                       tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_7
+    SLICE_X93Y150.B3     net (fanout=12)       0.527   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<7>
+    SLICE_X93Y150.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_2<31>
+                                                       tdc_board/tdc_core/reg_control_block/_n0517<7>11_1
+    SLICE_X97Y149.C3     net (fanout=6)        0.716   tdc_board/tdc_core/reg_control_block/_n0517<7>11
+    SLICE_X97Y149.C      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_4<31>
+                                                       tdc_board/tdc_core/reg_control_block/_n0550<7>1
+    SLICE_X97Y151.A6     net (fanout=30)       0.548   tdc_board/tdc_core/reg_control_block/_n0550
+    SLICE_X97Y151.A      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_8<30>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23610
+    SLICE_X89Y151.D6     net (fanout=1)        1.377   tdc_board/tdc_core/reg_control_block/Mmux_dat_out2369
+    SLICE_X89Y151.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_6<27>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23612
+    SLICE_X89Y151.C6     net (fanout=1)        0.118   tdc_board/tdc_core/reg_control_block/Mmux_dat_out23611
+    SLICE_X89Y151.C      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_6<27>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23613_SW0
+    SLICE_X86Y152.A4     net (fanout=1)        0.788   N1407
+    SLICE_X86Y152.A      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23613
+    SLICE_X86Y152.B4     net (fanout=1)        0.379   tdc_board/tdc_core/reg_control_block/Mmux_dat_out23612
+    SLICE_X86Y152.B      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23615
+    SLICE_X84Y153.D4     net (fanout=1)        0.477   tdc_board/tdc_core/reg_control_block/Mmux_dat_out23614
+    SLICE_X84Y153.D      Tilo                  0.203   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<27>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23617_SW0
+    SLICE_X84Y153.C6     net (fanout=1)        0.118   N1299
+    SLICE_X84Y153.CLK    Tas                   0.289   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<27>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23617
+                                                       tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_27
     -------------------------------------------------  ---------------------------
-    Total                                      8.669ns (4.091ns logic, 4.578ns route)
-                                                       (47.2% logic, 52.8% route)
+    Total                                      7.692ns (2.644ns logic, 5.048ns route)
+                                                       (34.4% logic, 65.6% route)
 
 --------------------------------------------------------------------------------
-Slack (setup path):     -0.656ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 (RAM)
-  Destination:          tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_31 (FF)
+Slack (setup path):     0.332ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_5 (FF)
+  Destination:          tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_27 (FF)
   Requirement:          8.000ns
-  Data Path Delay:      8.604ns (Levels of Logic = 10)
-  Clock Path Skew:      -0.017ns (0.241 - 0.258)
+  Data Path Delay:      7.621ns (Levels of Logic = 9)
+  Clock Path Skew:      -0.012ns (0.236 - 0.248)
   Source Clock:         clk_125m rising at 0.000ns
   Destination Clock:    clk_125m rising at 8.000ns
   Clock Uncertainty:    0.035ns
@@ -679,57 +667,54 @@ Slack (setup path):     -0.656ns (requirement - (data path - clock path skew + u
     Discrete Jitter (DJ):       0.000ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_31
+  Maximum Data Path at Slow Process Corner: tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_5 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_27
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    RAMB16_X3Y72.DOB6    Trcko_DOB_REG         1.600   clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-                                                       clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-    SLICE_X97Y147.C6     net (fanout=25)       1.014   cnx_slave_in[0]_adr<4>
-    SLICE_X97Y147.C      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_3<31>
-                                                       tdc_board/cmp_sdb_crossbar/crossbar/master_oe[0]_adr<4>1_1
-    SLICE_X100Y148.A3    net (fanout=10)       0.972   tdc_board/cmp_sdb_crossbar/crossbar/master_oe[0]_adr<4>1
-    SLICE_X100Y148.A     Tilo                  0.203   tdc_board/tdc_core/reg_control_block/acam_config_0<19>
-                                                       tdc_board/tdc_core/reg_control_block/GND_244_o_reg_adr[7]_equal_12_o1
-    SLICE_X95Y147.B6     net (fanout=33)       0.834   tdc_board/tdc_core/reg_control_block/GND_244_o_reg_adr[7]_equal_12_o
-    SLICE_X95Y147.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/Mmux_dat_out10810
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29211_SW1
-    SLICE_X95Y147.A5     net (fanout=1)        0.187   N526
-    SLICE_X95Y147.A      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/Mmux_dat_out10810
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29212
-    SLICE_X92Y148.B6     net (fanout=1)        0.328   tdc_board/tdc_core/reg_control_block/Mmux_dat_out29211
-    SLICE_X92Y148.B      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/Mmux_dat_out15610
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29216_SW2
-    SLICE_X92Y148.A5     net (fanout=1)        0.169   N2625
-    SLICE_X92Y148.A      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/Mmux_dat_out15610
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29216
-    SLICE_X91Y148.C6     net (fanout=1)        0.405   tdc_board/tdc_core/reg_control_block/Mmux_dat_out29215
-    SLICE_X91Y148.C      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_10<7>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29221_SW0_SW0
-    SLICE_X91Y148.D5     net (fanout=1)        0.209   N2671
-    SLICE_X91Y148.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_10<7>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29221_SW0
-    SLICE_X91Y147.D6     net (fanout=1)        0.279   N2569
-    SLICE_X91Y147.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29221_SW1
-    SLICE_X91Y147.C6     net (fanout=1)        0.118   N2673
-    SLICE_X91Y147.CLK    Tas                   0.322   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out29221
-                                                       tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_31
+    SLICE_X90Y150.BQ     Tcko                  0.447   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<6>
+                                                       tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_5
+    SLICE_X92Y150.B4     net (fanout=12)       0.521   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<5>
+    SLICE_X92Y150.B      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<3>
+                                                       tdc_board/tdc_core/reg_control_block/_n0517<7>11
+    SLICE_X97Y151.B6     net (fanout=35)       0.740   tdc_board/tdc_core/reg_control_block/_n0517<7>1
+    SLICE_X97Y151.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_8<30>
+                                                       tdc_board/tdc_core/reg_control_block/_n0559<7>1
+    SLICE_X97Y151.A4     net (fanout=30)       0.513   tdc_board/tdc_core/reg_control_block/_n0559
+    SLICE_X97Y151.A      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_8<30>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23610
+    SLICE_X89Y151.D6     net (fanout=1)        1.377   tdc_board/tdc_core/reg_control_block/Mmux_dat_out2369
+    SLICE_X89Y151.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_6<27>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23612
+    SLICE_X89Y151.C6     net (fanout=1)        0.118   tdc_board/tdc_core/reg_control_block/Mmux_dat_out23611
+    SLICE_X89Y151.C      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_6<27>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23613_SW0
+    SLICE_X86Y152.A4     net (fanout=1)        0.788   N1407
+    SLICE_X86Y152.A      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23613
+    SLICE_X86Y152.B4     net (fanout=1)        0.379   tdc_board/tdc_core/reg_control_block/Mmux_dat_out23612
+    SLICE_X86Y152.B      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<31>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23615
+    SLICE_X84Y153.D4     net (fanout=1)        0.477   tdc_board/tdc_core/reg_control_block/Mmux_dat_out23614
+    SLICE_X84Y153.D      Tilo                  0.203   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<27>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23617_SW0
+    SLICE_X84Y153.C6     net (fanout=1)        0.118   N1299
+    SLICE_X84Y153.CLK    Tas                   0.289   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<27>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out23617
+                                                       tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_27
     -------------------------------------------------  ---------------------------
-    Total                                      8.604ns (4.089ns logic, 4.515ns route)
-                                                       (47.5% logic, 52.5% route)
+    Total                                      7.621ns (2.590ns logic, 5.031ns route)
+                                                       (34.0% logic, 66.0% route)
 
 --------------------------------------------------------------------------------
 
-Paths for end point tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_25 (SLICE_X89Y149.C6), 1661 paths
+Paths for end point tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_25 (SLICE_X87Y151.C6), 670 paths
 --------------------------------------------------------------------------------
-Slack (setup path):     -0.746ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 (RAM)
+Slack (setup path):     0.261ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_4 (FF)
   Destination:          tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_25 (FF)
   Requirement:          8.000ns
-  Data Path Delay:      8.690ns (Levels of Logic = 7)
-  Clock Path Skew:      -0.021ns (0.237 - 0.258)
+  Data Path Delay:      7.690ns (Levels of Logic = 6)
+  Clock Path Skew:      -0.014ns (0.234 - 0.248)
   Source Clock:         clk_125m rising at 0.000ns
   Destination Clock:    clk_125m rising at 8.000ns
   Clock Uncertainty:    0.035ns
@@ -740,46 +725,42 @@ Slack (setup path):     -0.746ns (requirement - (data path - clock path skew + u
     Discrete Jitter (DJ):       0.000ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_25
+  Maximum Data Path at Slow Process Corner: tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_4 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_25
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    RAMB16_X3Y72.DOB8    Trcko_DOB_REG         1.600   clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-                                                       clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-    SLICE_X97Y149.B5     net (fanout=29)       1.100   cnx_slave_in[0]_adr<6>
-    SLICE_X97Y149.BMUX   Tilo                  0.313   tdc_board/tdc_core/data_engine_block/acam_config_rdbk_3<31>
-                                                       tdc_board/cmp_sdb_crossbar/crossbar/master_oe[0]_adr<6>1
-    SLICE_X99Y154.D1     net (fanout=26)       1.225   tdc_board/cnx_master_out[0]_adr<6>
-    SLICE_X99Y154.D      Tilo                  0.259   tdc_board/tdc_core/data_engine_block/acam_config_rdbk_2<27>
-                                                       tdc_board/tdc_core/reg_control_block/_n0606<7>2
-    SLICE_X98Y155.A3     net (fanout=30)       0.547   tdc_board/tdc_core/reg_control_block/_n0606
-    SLICE_X98Y155.A      Tilo                  0.205   tdc_board/tdc_core/data_engine_block/acam_config_rdbk_1<23>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out2147
-    SLICE_X96Y152.C4     net (fanout=3)        0.796   tdc_board/tdc_core/reg_control_block/Mmux_dat_out2146
-    SLICE_X96Y152.CMUX   Tilo                  0.343   N1057
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out21412_SW1_G
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out21412_SW1
-    SLICE_X96Y152.A4     net (fanout=1)        0.650   N1058
-    SLICE_X96Y152.A      Tilo                  0.205   N1057
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out21413
-    SLICE_X89Y149.D6     net (fanout=1)        0.748   tdc_board/tdc_core/reg_control_block/Mmux_dat_out21412
-    SLICE_X89Y149.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
+    SLICE_X90Y150.AQ     Tcko                  0.447   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<6>
+                                                       tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_4
+    SLICE_X93Y156.C3     net (fanout=37)       2.125   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<4>
+    SLICE_X93Y156.C      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_1<23>
+                                                       tdc_board/tdc_core/reg_control_block/_n0669<7>1
+    SLICE_X94Y159.B3     net (fanout=31)       1.024   tdc_board/tdc_core/reg_control_block/_n0669
+    SLICE_X94Y159.B      Tilo                  0.203   tdc_board/tdc_core/data_engine_block/acam_config_rdbk_3<27>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out2145
+    SLICE_X89Y157.C2     net (fanout=3)        1.159   tdc_board/tdc_core/reg_control_block/Mmux_dat_out2144
+    SLICE_X89Y157.C      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<8>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out21414_SW0
+    SLICE_X88Y151.B4     net (fanout=1)        0.708   N715
+    SLICE_X88Y151.B      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/acam_config_5<6>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out21415
+    SLICE_X87Y151.D4     net (fanout=1)        0.602   tdc_board/tdc_core/reg_control_block/Mmux_dat_out21414
+    SLICE_X87Y151.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
                                                        tdc_board/tdc_core/reg_control_block/Mmux_dat_out21417_SW0
-    SLICE_X89Y149.C6     net (fanout=1)        0.118   N2621
-    SLICE_X89Y149.CLK    Tas                   0.322   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
+    SLICE_X87Y151.C6     net (fanout=1)        0.118   N1303
+    SLICE_X87Y151.CLK    Tas                   0.322   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
                                                        tdc_board/tdc_core/reg_control_block/Mmux_dat_out21417
                                                        tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_25
     -------------------------------------------------  ---------------------------
-    Total                                      8.690ns (3.506ns logic, 5.184ns route)
-                                                       (40.3% logic, 59.7% route)
+    Total                                      7.690ns (1.954ns logic, 5.736ns route)
+                                                       (25.4% logic, 74.6% route)
 
 --------------------------------------------------------------------------------
-Slack (setup path):     -0.681ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 (RAM)
+Slack (setup path):     0.428ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_5 (FF)
   Destination:          tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_25 (FF)
   Requirement:          8.000ns
-  Data Path Delay:      8.625ns (Levels of Logic = 7)
-  Clock Path Skew:      -0.021ns (0.237 - 0.258)
+  Data Path Delay:      7.523ns (Levels of Logic = 7)
+  Clock Path Skew:      -0.014ns (0.234 - 0.248)
   Source Clock:         clk_125m rising at 0.000ns
   Destination Clock:    clk_125m rising at 8.000ns
   Clock Uncertainty:    0.035ns
@@ -790,46 +771,45 @@ Slack (setup path):     -0.681ns (requirement - (data path - clock path skew + u
     Discrete Jitter (DJ):       0.000ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_25
+  Maximum Data Path at Slow Process Corner: tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_5 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_25
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    RAMB16_X3Y72.DOB7    Trcko_DOB_REG         1.600   clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-                                                       clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-    SLICE_X97Y149.B4     net (fanout=31)       1.247   cnx_slave_in[0]_adr<5>
-    SLICE_X97Y149.B      Tilo                  0.259   tdc_board/tdc_core/data_engine_block/acam_config_rdbk_3<31>
-                                                       tdc_board/cmp_sdb_crossbar/crossbar/master_oe[0]_adr<5>1
-    SLICE_X99Y154.B1     net (fanout=50)       1.186   tdc_board/cnx_master_out[0]_adr<5>
-    SLICE_X99Y154.B      Tilo                  0.259   tdc_board/tdc_core/data_engine_block/acam_config_rdbk_2<27>
-                                                       tdc_board/tdc_core/reg_control_block/GND_244_o_reg_adr[7]_equal_20_o1
-    SLICE_X98Y155.A5     net (fanout=32)       0.428   tdc_board/tdc_core/reg_control_block/GND_244_o_reg_adr[7]_equal_20_o
-    SLICE_X98Y155.A      Tilo                  0.205   tdc_board/tdc_core/data_engine_block/acam_config_rdbk_1<23>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out2147
-    SLICE_X96Y152.C4     net (fanout=3)        0.796   tdc_board/tdc_core/reg_control_block/Mmux_dat_out2146
-    SLICE_X96Y152.CMUX   Tilo                  0.343   N1057
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out21412_SW1_G
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out21412_SW1
-    SLICE_X96Y152.A4     net (fanout=1)        0.650   N1058
-    SLICE_X96Y152.A      Tilo                  0.205   N1057
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out21413
-    SLICE_X89Y149.D6     net (fanout=1)        0.748   tdc_board/tdc_core/reg_control_block/Mmux_dat_out21412
-    SLICE_X89Y149.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
+    SLICE_X90Y150.BQ     Tcko                  0.447   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<6>
+                                                       tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_5
+    SLICE_X92Y150.B4     net (fanout=12)       0.521   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<5>
+    SLICE_X92Y150.B      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<3>
+                                                       tdc_board/tdc_core/reg_control_block/_n0517<7>11
+    SLICE_X93Y156.C6     net (fanout=35)       1.232   tdc_board/tdc_core/reg_control_block/_n0517<7>1
+    SLICE_X93Y156.C      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_1<23>
+                                                       tdc_board/tdc_core/reg_control_block/_n0669<7>1
+    SLICE_X94Y159.B3     net (fanout=31)       1.024   tdc_board/tdc_core/reg_control_block/_n0669
+    SLICE_X94Y159.B      Tilo                  0.203   tdc_board/tdc_core/data_engine_block/acam_config_rdbk_3<27>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out2145
+    SLICE_X89Y157.C2     net (fanout=3)        1.159   tdc_board/tdc_core/reg_control_block/Mmux_dat_out2144
+    SLICE_X89Y157.C      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<8>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out21414_SW0
+    SLICE_X88Y151.B4     net (fanout=1)        0.708   N715
+    SLICE_X88Y151.B      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/acam_config_5<6>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out21415
+    SLICE_X87Y151.D4     net (fanout=1)        0.602   tdc_board/tdc_core/reg_control_block/Mmux_dat_out21414
+    SLICE_X87Y151.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
                                                        tdc_board/tdc_core/reg_control_block/Mmux_dat_out21417_SW0
-    SLICE_X89Y149.C6     net (fanout=1)        0.118   N2621
-    SLICE_X89Y149.CLK    Tas                   0.322   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
+    SLICE_X87Y151.C6     net (fanout=1)        0.118   N1303
+    SLICE_X87Y151.CLK    Tas                   0.322   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
                                                        tdc_board/tdc_core/reg_control_block/Mmux_dat_out21417
                                                        tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_25
     -------------------------------------------------  ---------------------------
-    Total                                      8.625ns (3.452ns logic, 5.173ns route)
-                                                       (40.0% logic, 60.0% route)
+    Total                                      7.523ns (2.159ns logic, 5.364ns route)
+                                                       (28.7% logic, 71.3% route)
 
 --------------------------------------------------------------------------------
-Slack (setup path):     -0.631ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 (RAM)
+Slack (setup path):     0.510ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_2 (FF)
   Destination:          tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_25 (FF)
   Requirement:          8.000ns
-  Data Path Delay:      8.575ns (Levels of Logic = 7)
-  Clock Path Skew:      -0.021ns (0.237 - 0.258)
+  Data Path Delay:      7.443ns (Levels of Logic = 8)
+  Clock Path Skew:      -0.012ns (0.234 - 0.246)
   Source Clock:         clk_125m rising at 0.000ns
   Destination Clock:    clk_125m rising at 8.000ns
   Clock Uncertainty:    0.035ns
@@ -840,122 +820,126 @@ Slack (setup path):     -0.631ns (requirement - (data path - clock path skew + u
     Discrete Jitter (DJ):       0.000ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_25
+  Maximum Data Path at Slow Process Corner: tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_2 to tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_25
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    RAMB16_X3Y72.DOB8    Trcko_DOB_REG         1.600   clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-                                                       clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1
-    SLICE_X97Y149.B5     net (fanout=29)       1.100   cnx_slave_in[0]_adr<6>
-    SLICE_X97Y149.BMUX   Tilo                  0.313   tdc_board/tdc_core/data_engine_block/acam_config_rdbk_3<31>
-                                                       tdc_board/cmp_sdb_crossbar/crossbar/master_oe[0]_adr<6>1
-    SLICE_X98Y154.A1     net (fanout=26)       1.214   tdc_board/cnx_master_out[0]_adr<6>
-    SLICE_X98Y154.A      Tilo                  0.205   tdc_board/tdc_core/data_engine_block/acam_config_rdbk_1<27>
-                                                       tdc_board/tdc_core/reg_control_block/_n0620<7>2
-    SLICE_X97Y154.A3     net (fanout=30)       0.723   tdc_board/tdc_core/reg_control_block/_n0620
-    SLICE_X97Y154.A      Tilo                  0.259   tdc_board/tdc_core/data_engine_block/acam_config_rdbk_6<23>
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out2146
-    SLICE_X96Y152.C3     net (fanout=3)        0.516   tdc_board/tdc_core/reg_control_block/Mmux_dat_out2145
-    SLICE_X96Y152.CMUX   Tilo                  0.343   N1057
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out21412_SW1_G
-                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out21412_SW1
-    SLICE_X96Y152.A4     net (fanout=1)        0.650   N1058
-    SLICE_X96Y152.A      Tilo                  0.205   N1057
+    SLICE_X92Y152.CQ     Tcko                  0.408   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<0>
+                                                       tdc_board/tdc_core/reg_control_block/reg_adr_pipe0_2
+    SLICE_X90Y151.D2     net (fanout=40)       1.648   tdc_board/tdc_core/reg_control_block/reg_adr_pipe0<2>
+    SLICE_X90Y151.D      Tilo                  0.203   tdc_board/tdc_core/reg_control_block/acam_config_5<10>
+                                                       tdc_board/tdc_core/reg_control_block/_n0533<7>1
+    SLICE_X90Y151.A3     net (fanout=31)       0.388   tdc_board/tdc_core/reg_control_block/_n0533
+    SLICE_X90Y151.A      Tilo                  0.203   tdc_board/tdc_core/reg_control_block/acam_config_5<10>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out11001
+    SLICE_X91Y149.B4     net (fanout=30)       0.747   tdc_board/tdc_core/reg_control_block/Mmux_dat_out1100
+    SLICE_X91Y149.B      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_4<27>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out21412
+    SLICE_X91Y149.A5     net (fanout=1)        0.187   tdc_board/tdc_core/reg_control_block/Mmux_dat_out21411
+    SLICE_X91Y149.A      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/acam_config_4<27>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out21413_SW0
+    SLICE_X88Y151.A6     net (fanout=1)        0.493   N1411
+    SLICE_X88Y151.A      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/acam_config_5<6>
                                                        tdc_board/tdc_core/reg_control_block/Mmux_dat_out21413
-    SLICE_X89Y149.D6     net (fanout=1)        0.748   tdc_board/tdc_core/reg_control_block/Mmux_dat_out21412
-    SLICE_X89Y149.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
+    SLICE_X88Y151.B2     net (fanout=1)        0.937   tdc_board/tdc_core/reg_control_block/Mmux_dat_out21412
+    SLICE_X88Y151.B      Tilo                  0.205   tdc_board/tdc_core/reg_control_block/acam_config_5<6>
+                                                       tdc_board/tdc_core/reg_control_block/Mmux_dat_out21415
+    SLICE_X87Y151.D4     net (fanout=1)        0.602   tdc_board/tdc_core/reg_control_block/Mmux_dat_out21414
+    SLICE_X87Y151.D      Tilo                  0.259   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
                                                        tdc_board/tdc_core/reg_control_block/Mmux_dat_out21417_SW0
-    SLICE_X89Y149.C6     net (fanout=1)        0.118   N2621
-    SLICE_X89Y149.CLK    Tas                   0.322   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
+    SLICE_X87Y151.C6     net (fanout=1)        0.118   N1303
+    SLICE_X87Y151.CLK    Tas                   0.322   tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
                                                        tdc_board/tdc_core/reg_control_block/Mmux_dat_out21417
                                                        tdc_board/tdc_core/reg_control_block/tdc_config_wb_dat_o_25
     -------------------------------------------------  ---------------------------
-    Total                                      8.575ns (3.506ns logic, 5.069ns route)
-                                                       (40.9% logic, 59.1% route)
+    Total                                      7.443ns (2.323ns logic, 5.120ns route)
+                                                       (31.2% logic, 68.8% route)
 
 --------------------------------------------------------------------------------
 
 Hold Paths: TS_tdc_125m_clk_n_i = PERIOD TIMEGRP "tdc_125m_clk_n_i" 8 ns HIGH 50%;
 --------------------------------------------------------------------------------
 
-Paths for end point tdc_board/tdc_core/data_formatting_block/previous_utc_7 (SLICE_X80Y140.CE), 1 path
+Paths for end point tdc_board/tdc_core/data_formatting_block/previous_utc_16 (SLICE_X79Y161.AX), 1 path
 --------------------------------------------------------------------------------
-Slack (hold path):      0.334ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               tdc_board/tdc_core/one_second_block/pulse_delayer_counter/counter_is_zero_o (FF)
-  Destination:          tdc_board/tdc_core/data_formatting_block/previous_utc_7 (FF)
+Slack (hold path):      0.395ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               tdc_board/tdc_core/one_second_block/local_utc_16 (FF)
+  Destination:          tdc_board/tdc_core/data_formatting_block/previous_utc_16 (FF)
   Requirement:          0.000ns
-  Data Path Delay:      0.333ns (Levels of Logic = 0)
-  Clock Path Skew:      -0.001ns (0.042 - 0.043)
+  Data Path Delay:      0.485ns (Levels of Logic = 0)
+  Clock Path Skew:      0.090ns (0.438 - 0.348)
   Source Clock:         clk_125m rising at 8.000ns
   Destination Clock:    clk_125m rising at 8.000ns
   Clock Uncertainty:    0.000ns
 
-  Minimum Data Path at Fast Process Corner: tdc_board/tdc_core/one_second_block/pulse_delayer_counter/counter_is_zero_o to tdc_board/tdc_core/data_formatting_block/previous_utc_7
+  Minimum Data Path at Fast Process Corner: tdc_board/tdc_core/one_second_block/local_utc_16 to tdc_board/tdc_core/data_formatting_block/previous_utc_16
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X81Y142.DQ     Tcko                  0.198   tdc_board/tdc_core/one_second_block/pulse_delayer_counter/counter_is_zero_o
-                                                       tdc_board/tdc_core/one_second_block/pulse_delayer_counter/counter_is_zero_o
-    SLICE_X80Y140.CE     net (fanout=69)       0.243   tdc_board/tdc_core/one_second_block/pulse_delayer_counter/counter_is_zero_o
-    SLICE_X80Y140.CLK    Tckce       (-Th)     0.108   tdc_board/tdc_core/data_formatting_block/previous_utc<7>
-                                                       tdc_board/tdc_core/data_formatting_block/previous_utc_7
+    SLICE_X78Y159.AQ     Tcko                  0.200   tdc_board/tdc_core/one_second_block/local_utc<19>
+                                                       tdc_board/tdc_core/one_second_block/local_utc_16
+    SLICE_X79Y161.AX     net (fanout=4)        0.226   tdc_board/tdc_core/one_second_block/local_utc<16>
+    SLICE_X79Y161.CLK    Tckdi       (-Th)    -0.059   tdc_board/tdc_core/data_formatting_block/previous_utc<19>
+                                                       tdc_board/tdc_core/data_formatting_block/previous_utc_16
     -------------------------------------------------  ---------------------------
-    Total                                      0.333ns (0.090ns logic, 0.243ns route)
-                                                       (27.0% logic, 73.0% route)
+    Total                                      0.485ns (0.259ns logic, 0.226ns route)
+                                                       (53.4% logic, 46.6% route)
 
 --------------------------------------------------------------------------------
 
-Paths for end point tdc_board/tdc_core/data_formatting_block/previous_utc_6 (SLICE_X80Y140.CE), 1 path
+Paths for end point tdc_board/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_2 (SLICE_X88Y138.B5), 1 path
 --------------------------------------------------------------------------------
-Slack (hold path):      0.338ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               tdc_board/tdc_core/one_second_block/pulse_delayer_counter/counter_is_zero_o (FF)
-  Destination:          tdc_board/tdc_core/data_formatting_block/previous_utc_6 (FF)
+Slack (hold path):      0.395ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               tdc_board/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_1 (FF)
+  Destination:          tdc_board/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_2 (FF)
   Requirement:          0.000ns
-  Data Path Delay:      0.337ns (Levels of Logic = 0)
-  Clock Path Skew:      -0.001ns (0.042 - 0.043)
+  Data Path Delay:      0.395ns (Levels of Logic = 1)
+  Clock Path Skew:      0.000ns
   Source Clock:         clk_125m rising at 8.000ns
   Destination Clock:    clk_125m rising at 8.000ns
   Clock Uncertainty:    0.000ns
 
-  Minimum Data Path at Fast Process Corner: tdc_board/tdc_core/one_second_block/pulse_delayer_counter/counter_is_zero_o to tdc_board/tdc_core/data_formatting_block/previous_utc_6
+  Minimum Data Path at Fast Process Corner: tdc_board/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_1 to tdc_board/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_2
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X81Y142.DQ     Tcko                  0.198   tdc_board/tdc_core/one_second_block/pulse_delayer_counter/counter_is_zero_o
-                                                       tdc_board/tdc_core/one_second_block/pulse_delayer_counter/counter_is_zero_o
-    SLICE_X80Y140.CE     net (fanout=69)       0.243   tdc_board/tdc_core/one_second_block/pulse_delayer_counter/counter_is_zero_o
-    SLICE_X80Y140.CLK    Tckce       (-Th)     0.104   tdc_board/tdc_core/data_formatting_block/previous_utc<7>
-                                                       tdc_board/tdc_core/data_formatting_block/previous_utc_6
+    SLICE_X88Y138.BQ     Tcko                  0.200   tdc_board/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt<1>
+                                                       tdc_board/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_1
+    SLICE_X88Y138.B5     net (fanout=5)        0.074   tdc_board/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt<1>
+    SLICE_X88Y138.CLK    Tah         (-Th)    -0.121   tdc_board/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt<1>
+                                                       tdc_board/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/Mmux_dcnt[2]_GND_336_o_mux_8_OUT31
+                                                       tdc_board/mezzanine_I2C_master_EEPROM/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_2
     -------------------------------------------------  ---------------------------
-    Total                                      0.337ns (0.094ns logic, 0.243ns route)
-                                                       (27.9% logic, 72.1% route)
+    Total                                      0.395ns (0.321ns logic, 0.074ns route)
+                                                       (81.3% logic, 18.7% route)
 
 --------------------------------------------------------------------------------
 
-Paths for end point tdc_board/tdc_core/data_formatting_block/previous_utc_5 (SLICE_X80Y140.CE), 1 path
+Paths for end point tdc_board/tdc_core/data_formatting_block/un_retrig_nb_offset_24 (SLICE_X88Y172.B6), 1 path
 --------------------------------------------------------------------------------
-Slack (hold path):      0.340ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               tdc_board/tdc_core/one_second_block/pulse_delayer_counter/counter_is_zero_o (FF)
-  Destination:          tdc_board/tdc_core/data_formatting_block/previous_utc_5 (FF)
+Slack (hold path):      0.403ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               tdc_board/tdc_core/data_formatting_block/un_previous_retrig_nb_offset_24 (FF)
+  Destination:          tdc_board/tdc_core/data_formatting_block/un_retrig_nb_offset_24 (FF)
   Requirement:          0.000ns
-  Data Path Delay:      0.339ns (Levels of Logic = 0)
-  Clock Path Skew:      -0.001ns (0.042 - 0.043)
+  Data Path Delay:      0.405ns (Levels of Logic = 1)
+  Clock Path Skew:      0.002ns (0.040 - 0.038)
   Source Clock:         clk_125m rising at 8.000ns
   Destination Clock:    clk_125m rising at 8.000ns
   Clock Uncertainty:    0.000ns
 
-  Minimum Data Path at Fast Process Corner: tdc_board/tdc_core/one_second_block/pulse_delayer_counter/counter_is_zero_o to tdc_board/tdc_core/data_formatting_block/previous_utc_5
+  Minimum Data Path at Fast Process Corner: tdc_board/tdc_core/data_formatting_block/un_previous_retrig_nb_offset_24 to tdc_board/tdc_core/data_formatting_block/un_retrig_nb_offset_24
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X81Y142.DQ     Tcko                  0.198   tdc_board/tdc_core/one_second_block/pulse_delayer_counter/counter_is_zero_o
-                                                       tdc_board/tdc_core/one_second_block/pulse_delayer_counter/counter_is_zero_o
-    SLICE_X80Y140.CE     net (fanout=69)       0.243   tdc_board/tdc_core/one_second_block/pulse_delayer_counter/counter_is_zero_o
-    SLICE_X80Y140.CLK    Tckce       (-Th)     0.102   tdc_board/tdc_core/data_formatting_block/previous_utc<7>
-                                                       tdc_board/tdc_core/data_formatting_block/previous_utc_5
+    SLICE_X89Y172.AQ     Tcko                  0.198   tdc_board/tdc_core/data_formatting_block/un_previous_retrig_nb_offset<25>
+                                                       tdc_board/tdc_core/data_formatting_block/un_previous_retrig_nb_offset_24
+    SLICE_X88Y172.B6     net (fanout=1)        0.017   tdc_board/tdc_core/data_formatting_block/un_previous_retrig_nb_offset<24>
+    SLICE_X88Y172.CLK    Tah         (-Th)    -0.190   tdc_board/tdc_core/data_formatting_block/un_retrig_nb_offset<25>
+                                                       tdc_board/tdc_core/data_formatting_block/Mmux_retrig_nb_offset_i[31]_un_previous_retrig_nb_offset[31]_mux_68_OUT171
+                                                       tdc_board/tdc_core/data_formatting_block/un_retrig_nb_offset_24
     -------------------------------------------------  ---------------------------
-    Total                                      0.339ns (0.096ns logic, 0.243ns route)
-                                                       (28.3% logic, 71.7% route)
+    Total                                      0.405ns (0.388ns logic, 0.017ns route)
+                                                       (95.8% logic, 4.2% route)
 
 --------------------------------------------------------------------------------
 
@@ -984,7 +968,7 @@ Slack: 4.876ns (period - min period limit)
   Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
   Physical resource: tdc_board/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
   Logical resource: tdc_board/tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
-  Location pin: RAMB16_X3Y82.CLKA
+  Location pin: RAMB16_X3Y84.CLKA
   Clock network: clk_125m
 --------------------------------------------------------------------------------
 
@@ -995,17 +979,17 @@ For more information, see Period Analysis in the Timing Closure User Guide (UG61
 
  0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
  0 timing errors detected. (0 component switching limit errors)
- Minimum period is   0.394ns.
+ Minimum period is   0.430ns.
 --------------------------------------------------------------------------------
 
 Component Switching Limit Checks: TS_acam_refclk_p_i = PERIOD TIMEGRP "acam_refclk_p_i" 32 ns HIGH 50%;
 --------------------------------------------------------------------------------
-Slack: 31.606ns (period - min period limit)
+Slack: 31.570ns (period - min period limit)
   Period: 32.000ns
-  Min period limit: 0.394ns (2538.071MHz) (Tcp)
+  Min period limit: 0.430ns (2325.581MHz) (Tcp)
   Physical resource: clks_rsts_mgment/acam_refclk_synch<2>/CLK
   Logical resource: clks_rsts_mgment/acam_refclk_synch_0/CK
-  Location pin: SLICE_X67Y189.CLK
+  Location pin: SLICE_X66Y189.CLK
   Clock network: clk_125m
 --------------------------------------------------------------------------------
 
@@ -1016,17 +1000,17 @@ For more information, see Period Analysis in the Timing Closure User Guide (UG61
 
  1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
  0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is   3.949ns.
+ Minimum period is   3.599ns.
 --------------------------------------------------------------------------------
 
-Paths for end point clks_rsts_mgment/acam_refclk_synch_0 (SLICE_X67Y189.SR), 1 path
+Paths for end point clks_rsts_mgment/acam_refclk_synch_0 (SLICE_X66Y189.SR), 1 path
 --------------------------------------------------------------------------------
-Slack (setup path):     28.051ns (requirement - (data path - clock path skew + uncertainty))
+Slack (setup path):     28.401ns (requirement - (data path - clock path skew + uncertainty))
   Source:               clks_rsts_mgment/internal_rst_synch_1 (FF)
   Destination:          clks_rsts_mgment/acam_refclk_synch_0 (FF)
   Requirement:          32.000ns
-  Data Path Delay:      4.135ns (Levels of Logic = 0)
-  Clock Path Skew:      0.221ns (0.944 - 0.723)
+  Data Path Delay:      3.689ns (Levels of Logic = 0)
+  Clock Path Skew:      0.125ns (0.944 - 0.819)
   Source Clock:         clk_125m rising at 0.000ns
   Destination Clock:    clk_125m rising at 32.000ns
   Clock Uncertainty:    0.035ns
@@ -1041,28 +1025,28 @@ Slack (setup path):     28.051ns (requirement - (data path - clock path skew + u
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X90Y162.DQ     Tcko                  0.447   clks_rsts_mgment/internal_rst_synch<1>
+    SLICE_X60Y156.DQ     Tcko                  0.447   clks_rsts_mgment/internal_rst_synch<1>
                                                        clks_rsts_mgment/internal_rst_synch_1
-    SLICE_X67Y189.SR     net (fanout=659)      3.286   clks_rsts_mgment/internal_rst_synch<1>
-    SLICE_X67Y189.CLK    Tsrck                 0.402   clks_rsts_mgment/acam_refclk_synch<2>
+    SLICE_X66Y189.SR     net (fanout=683)      2.798   clks_rsts_mgment/internal_rst_synch<1>
+    SLICE_X66Y189.CLK    Tsrck                 0.444   clks_rsts_mgment/acam_refclk_synch<2>
                                                        clks_rsts_mgment/acam_refclk_synch_0
     -------------------------------------------------  ---------------------------
-    Total                                      4.135ns (0.849ns logic, 3.286ns route)
-                                                       (20.5% logic, 79.5% route)
+    Total                                      3.689ns (0.891ns logic, 2.798ns route)
+                                                       (24.2% logic, 75.8% route)
 
 --------------------------------------------------------------------------------
 
 Hold Paths: TS_acam_refclk_n_i = PERIOD TIMEGRP "acam_refclk_n_i" 32 ns HIGH 50%;
 --------------------------------------------------------------------------------
 
-Paths for end point clks_rsts_mgment/acam_refclk_synch_0 (SLICE_X67Y189.SR), 1 path
+Paths for end point clks_rsts_mgment/acam_refclk_synch_0 (SLICE_X66Y189.SR), 1 path
 --------------------------------------------------------------------------------
-Slack (hold path):      1.926ns (requirement - (clock path skew + uncertainty - data path))
+Slack (hold path):      1.784ns (requirement - (clock path skew + uncertainty - data path))
   Source:               clks_rsts_mgment/internal_rst_synch_1 (FF)
   Destination:          clks_rsts_mgment/acam_refclk_synch_0 (FF)
   Requirement:          0.000ns
-  Data Path Delay:      2.181ns (Levels of Logic = 0)
-  Clock Path Skew:      0.255ns (0.680 - 0.425)
+  Data Path Delay:      1.943ns (Levels of Logic = 0)
+  Clock Path Skew:      0.159ns (0.680 - 0.521)
   Source Clock:         clk_125m rising at 32.000ns
   Destination Clock:    clk_125m rising at 32.000ns
   Clock Uncertainty:    0.000ns
@@ -1071,28 +1055,370 @@ Slack (hold path):      1.926ns (requirement - (clock path skew + uncertainty -
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X90Y162.DQ     Tcko                  0.234   clks_rsts_mgment/internal_rst_synch<1>
+    SLICE_X60Y156.DQ     Tcko                  0.234   clks_rsts_mgment/internal_rst_synch<1>
                                                        clks_rsts_mgment/internal_rst_synch_1
-    SLICE_X67Y189.SR     net (fanout=659)      2.075   clks_rsts_mgment/internal_rst_synch<1>
-    SLICE_X67Y189.CLK    Tcksr       (-Th)     0.128   clks_rsts_mgment/acam_refclk_synch<2>
+    SLICE_X66Y189.SR     net (fanout=683)      1.684   clks_rsts_mgment/internal_rst_synch<1>
+    SLICE_X66Y189.CLK    Tcksr       (-Th)    -0.025   clks_rsts_mgment/acam_refclk_synch<2>
                                                        clks_rsts_mgment/acam_refclk_synch_0
     -------------------------------------------------  ---------------------------
-    Total                                      2.181ns (0.106ns logic, 2.075ns route)
-                                                       (4.9% logic, 95.1% route)
+    Total                                      1.943ns (0.259ns logic, 1.684ns route)
+                                                       (13.3% logic, 86.7% route)
 
 --------------------------------------------------------------------------------
 
 Component Switching Limit Checks: TS_acam_refclk_n_i = PERIOD TIMEGRP "acam_refclk_n_i" 32 ns HIGH 50%;
 --------------------------------------------------------------------------------
-Slack: 31.606ns (period - min period limit)
+Slack: 31.570ns (period - min period limit)
   Period: 32.000ns
-  Min period limit: 0.394ns (2538.071MHz) (Tcp)
+  Min period limit: 0.430ns (2325.581MHz) (Tcp)
   Physical resource: clks_rsts_mgment/acam_refclk_synch<2>/CLK
   Logical resource: clks_rsts_mgment/acam_refclk_synch_0/CK
-  Location pin: SLICE_X67Y189.CLK
+  Location pin: SLICE_X66Y189.CLK
   Clock network: clk_125m
 --------------------------------------------------------------------------------
 
+================================================================================
+Timing constraint: ts_ignore_xclock1 = MAXDELAY FROM TIMEGRP 
+"clk_62m5_pllxilinx" TO TIMEGRP         "clk_125m" 20 ns DATAPATHONLY;
+For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).
+
+ 5 paths analyzed, 5 endpoints analyzed, 0 failing endpoints
+ 0 timing errors detected. (0 setup errors, 0 hold errors)
+ Maximum delay is   1.994ns.
+--------------------------------------------------------------------------------
+
+Paths for end point clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_0 (SLICE_X90Y137.AX), 1 path
+--------------------------------------------------------------------------------
+Slack (setup paths):    18.006ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               clks_crossing_125M_62M5/mfifo/w_idx_gray_0 (FF)
+  Destination:          clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_0 (FF)
+  Requirement:          20.000ns
+  Data Path Delay:      1.994ns (Levels of Logic = 0)
+  Clock Path Skew:      0.000ns
+  Source Clock:         clk_62m5_pllxilinx rising at 0.000ns
+  Destination Clock:    clk_125m rising at 8.000ns
+  Clock Uncertainty:    0.000ns
+
+  Maximum Data Path at Slow Process Corner: clks_crossing_125M_62M5/mfifo/w_idx_gray_0 to clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_0
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X71Y137.CMUX   Tshcko                0.461   clks_crossing_125M_62M5/mfifo/w_idx_bnry<3>
+                                                       clks_crossing_125M_62M5/mfifo/w_idx_gray_0
+    SLICE_X90Y137.AX     net (fanout=2)        1.593   clks_crossing_125M_62M5/mfifo/w_idx_gray<0>
+    SLICE_X90Y137.CLK    Tds                  -0.060   clks_crossing_125M_62M5/mfifo/w_idx_shift_r_3<1>
+                                                       clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_0
+    -------------------------------------------------  ---------------------------
+    Total                                      1.994ns (0.401ns logic, 1.593ns route)
+                                                       (20.1% logic, 79.9% route)
+
+--------------------------------------------------------------------------------
+
+Paths for end point clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_3 (SLICE_X90Y137.CI), 1 path
+--------------------------------------------------------------------------------
+Slack (setup paths):    18.243ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               clks_crossing_125M_62M5/mfifo/w_idx_gray_3 (FF)
+  Destination:          clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_3 (FF)
+  Requirement:          20.000ns
+  Data Path Delay:      1.757ns (Levels of Logic = 0)
+  Clock Path Skew:      0.000ns
+  Source Clock:         clk_62m5_pllxilinx rising at 0.000ns
+  Destination Clock:    clk_125m rising at 8.000ns
+  Clock Uncertainty:    0.000ns
+
+  Maximum Data Path at Slow Process Corner: clks_crossing_125M_62M5/mfifo/w_idx_gray_3 to clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_3
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X71Y137.BMUX   Tshcko                0.461   clks_crossing_125M_62M5/mfifo/w_idx_bnry<3>
+                                                       clks_crossing_125M_62M5/mfifo/w_idx_gray_3
+    SLICE_X90Y137.CI     net (fanout=2)        1.231   clks_crossing_125M_62M5/mfifo/w_idx_gray<3>
+    SLICE_X90Y137.CLK    Tds                   0.065   clks_crossing_125M_62M5/mfifo/w_idx_shift_r_3<1>
+                                                       clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_3
+    -------------------------------------------------  ---------------------------
+    Total                                      1.757ns (0.526ns logic, 1.231ns route)
+                                                       (29.9% logic, 70.1% route)
+
+--------------------------------------------------------------------------------
+
+Paths for end point clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_4 (SLICE_X90Y137.BI), 1 path
+--------------------------------------------------------------------------------
+Slack (setup paths):    18.257ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               clks_crossing_125M_62M5/mfifo/w_idx_bnry_4 (FF)
+  Destination:          clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_4 (FF)
+  Requirement:          20.000ns
+  Data Path Delay:      1.743ns (Levels of Logic = 0)
+  Clock Path Skew:      0.000ns
+  Source Clock:         clk_62m5_pllxilinx rising at 0.000ns
+  Destination Clock:    clk_125m rising at 8.000ns
+  Clock Uncertainty:    0.000ns
+
+  Maximum Data Path at Slow Process Corner: clks_crossing_125M_62M5/mfifo/w_idx_bnry_4 to clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_4
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X71Y137.BQ     Tcko                  0.391   clks_crossing_125M_62M5/mfifo/w_idx_bnry<3>
+                                                       clks_crossing_125M_62M5/mfifo/w_idx_bnry_4
+    SLICE_X90Y137.BI     net (fanout=3)        1.322   clks_crossing_125M_62M5/mfifo/w_idx_bnry<4>
+    SLICE_X90Y137.CLK    Tds                   0.030   clks_crossing_125M_62M5/mfifo/w_idx_shift_r_3<1>
+                                                       clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_4
+    -------------------------------------------------  ---------------------------
+    Total                                      1.743ns (0.421ns logic, 1.322ns route)
+                                                       (24.2% logic, 75.8% route)
+
+--------------------------------------------------------------------------------
+Hold Paths: ts_ignore_xclock1 = MAXDELAY FROM TIMEGRP "clk_62m5_pllxilinx" TO TIMEGRP         "clk_125m" 20 ns DATAPATHONLY;
+--------------------------------------------------------------------------------
+
+Paths for end point clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_1 (SLICE_X90Y137.DI), 1 path
+--------------------------------------------------------------------------------
+Slack (hold path):      0.895ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               clks_crossing_125M_62M5/mfifo/w_idx_gray_1 (FF)
+  Destination:          clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_1 (FF)
+  Requirement:          0.000ns
+  Data Path Delay:      0.895ns (Levels of Logic = 0)
+  Positive Clock Path Skew: 0.000ns
+  Source Clock:         clk_62m5_pllxilinx rising at 0.000ns
+  Destination Clock:    clk_125m rising at 0.000ns
+  Clock Uncertainty:    0.000ns
+
+  Minimum Data Path at Fast Process Corner: clks_crossing_125M_62M5/mfifo/w_idx_gray_1 to clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_1
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X70Y137.AQ     Tcko                  0.200   clks_crossing_125M_62M5/mfifo/w_idx_gray<2>
+                                                       clks_crossing_125M_62M5/mfifo/w_idx_gray_1
+    SLICE_X90Y137.DI     net (fanout=2)        0.662   clks_crossing_125M_62M5/mfifo/w_idx_gray<1>
+    SLICE_X90Y137.CLK    Tdh         (-Th)    -0.033   clks_crossing_125M_62M5/mfifo/w_idx_shift_r_3<1>
+                                                       clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_1
+    -------------------------------------------------  ---------------------------
+    Total                                      0.895ns (0.233ns logic, 0.662ns route)
+                                                       (26.0% logic, 74.0% route)
+--------------------------------------------------------------------------------
+
+Paths for end point clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_2 (SLICE_X90Y137.AI), 1 path
+--------------------------------------------------------------------------------
+Slack (hold path):      0.957ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               clks_crossing_125M_62M5/mfifo/w_idx_gray_2 (FF)
+  Destination:          clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_2 (FF)
+  Requirement:          0.000ns
+  Data Path Delay:      0.957ns (Levels of Logic = 0)
+  Positive Clock Path Skew: 0.000ns
+  Source Clock:         clk_62m5_pllxilinx rising at 0.000ns
+  Destination Clock:    clk_125m rising at 0.000ns
+  Clock Uncertainty:    0.000ns
+
+  Minimum Data Path at Fast Process Corner: clks_crossing_125M_62M5/mfifo/w_idx_gray_2 to clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_2
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X70Y137.BQ     Tcko                  0.200   clks_crossing_125M_62M5/mfifo/w_idx_gray<2>
+                                                       clks_crossing_125M_62M5/mfifo/w_idx_gray_2
+    SLICE_X90Y137.AI     net (fanout=2)        0.727   clks_crossing_125M_62M5/mfifo/w_idx_gray<2>
+    SLICE_X90Y137.CLK    Tdh         (-Th)    -0.030   clks_crossing_125M_62M5/mfifo/w_idx_shift_r_3<1>
+                                                       clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_2
+    -------------------------------------------------  ---------------------------
+    Total                                      0.957ns (0.230ns logic, 0.727ns route)
+                                                       (24.0% logic, 76.0% route)
+--------------------------------------------------------------------------------
+
+Paths for end point clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_4 (SLICE_X90Y137.BI), 1 path
+--------------------------------------------------------------------------------
+Slack (hold path):      1.005ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               clks_crossing_125M_62M5/mfifo/w_idx_bnry_4 (FF)
+  Destination:          clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_4 (FF)
+  Requirement:          0.000ns
+  Data Path Delay:      1.005ns (Levels of Logic = 0)
+  Positive Clock Path Skew: 0.000ns
+  Source Clock:         clk_62m5_pllxilinx rising at 0.000ns
+  Destination Clock:    clk_125m rising at 0.000ns
+  Clock Uncertainty:    0.000ns
+
+  Minimum Data Path at Fast Process Corner: clks_crossing_125M_62M5/mfifo/w_idx_bnry_4 to clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_4
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X71Y137.BQ     Tcko                  0.198   clks_crossing_125M_62M5/mfifo/w_idx_bnry<3>
+                                                       clks_crossing_125M_62M5/mfifo/w_idx_bnry_4
+    SLICE_X90Y137.BI     net (fanout=3)        0.778   clks_crossing_125M_62M5/mfifo/w_idx_bnry<4>
+    SLICE_X90Y137.CLK    Tdh         (-Th)    -0.029   clks_crossing_125M_62M5/mfifo/w_idx_shift_r_3<1>
+                                                       clks_crossing_125M_62M5/mfifo/Mshreg_w_idx_shift_r_3_4
+    -------------------------------------------------  ---------------------------
+    Total                                      1.005ns (0.227ns logic, 0.778ns route)
+                                                       (22.6% logic, 77.4% route)
+--------------------------------------------------------------------------------
+
+================================================================================
+Timing constraint: ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP "clk_125m" TO 
+TIMEGRP         "clk_62m5_pllxilinx" 20 ns DATAPATHONLY;
+For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).
+
+ 12 paths analyzed, 12 endpoints analyzed, 0 failing endpoints
+ 0 timing errors detected. (0 setup errors, 0 hold errors)
+ Maximum delay is   4.080ns.
+--------------------------------------------------------------------------------
+
+Paths for end point clks_crossing_125M_62M5/sfifo/Mshreg_w_idx_shift_r_3_3 (SLICE_X36Y80.CI), 1 path
+--------------------------------------------------------------------------------
+Slack (setup paths):    15.920ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               clks_crossing_125M_62M5/sfifo/w_idx_gray_3 (FF)
+  Destination:          clks_crossing_125M_62M5/sfifo/Mshreg_w_idx_shift_r_3_3 (FF)
+  Requirement:          20.000ns
+  Data Path Delay:      4.080ns (Levels of Logic = 0)
+  Clock Path Skew:      0.000ns
+  Source Clock:         clk_125m rising at 8.000ns
+  Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
+  Clock Uncertainty:    0.000ns
+
+  Maximum Data Path at Slow Process Corner: clks_crossing_125M_62M5/sfifo/w_idx_gray_3 to clks_crossing_125M_62M5/sfifo/Mshreg_w_idx_shift_r_3_3
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X53Y128.BMUX   Tshcko                0.461   clks_crossing_125M_62M5/sfifo/w_idx_bnry<4>
+                                                       clks_crossing_125M_62M5/sfifo/w_idx_gray_3
+    SLICE_X36Y80.CI      net (fanout=1)        3.554   clks_crossing_125M_62M5/sfifo/w_idx_gray<3>
+    SLICE_X36Y80.CLK     Tds                   0.065   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_errorflag
+                                                       clks_crossing_125M_62M5/sfifo/Mshreg_w_idx_shift_r_3_3
+    -------------------------------------------------  ---------------------------
+    Total                                      4.080ns (0.526ns logic, 3.554ns route)
+                                                       (12.9% logic, 87.1% route)
+
+--------------------------------------------------------------------------------
+
+Paths for end point clks_crossing_125M_62M5/mfifo/Mshreg_r_idx_shift_w_3_0 (SLICE_X60Y124.AX), 1 path
+--------------------------------------------------------------------------------
+Slack (setup paths):    17.126ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               clks_crossing_125M_62M5/mfifo/r_idx_gray_0 (FF)
+  Destination:          clks_crossing_125M_62M5/mfifo/Mshreg_r_idx_shift_w_3_0 (FF)
+  Requirement:          20.000ns
+  Data Path Delay:      2.874ns (Levels of Logic = 0)
+  Clock Path Skew:      0.000ns
+  Source Clock:         clk_125m rising at 8.000ns
+  Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
+  Clock Uncertainty:    0.000ns
+
+  Maximum Data Path at Slow Process Corner: clks_crossing_125M_62M5/mfifo/r_idx_gray_0 to clks_crossing_125M_62M5/mfifo/Mshreg_r_idx_shift_w_3_0
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X88Y137.BMUX   Tshcko                0.455   clks_crossing_125M_62M5/mfifo/r_idx_bnry<3>
+                                                       clks_crossing_125M_62M5/mfifo/r_idx_gray_0
+    SLICE_X60Y124.AX     net (fanout=2)        2.479   clks_crossing_125M_62M5/mfifo/r_idx_gray<0>
+    SLICE_X60Y124.CLK    Tds                  -0.060   clks_crossing_125M_62M5/mfifo/r_idx_shift_w_3<4>
+                                                       clks_crossing_125M_62M5/mfifo/Mshreg_r_idx_shift_w_3_0
+    -------------------------------------------------  ---------------------------
+    Total                                      2.874ns (0.395ns logic, 2.479ns route)
+                                                       (13.7% logic, 86.3% route)
+
+--------------------------------------------------------------------------------
+
+Paths for end point clks_crossing_125M_62M5/mfifo/Mshreg_r_idx_shift_w_3_3 (SLICE_X60Y124.CI), 1 path
+--------------------------------------------------------------------------------
+Slack (setup paths):    17.126ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               clks_crossing_125M_62M5/mfifo/r_idx_gray_3 (FF)
+  Destination:          clks_crossing_125M_62M5/mfifo/Mshreg_r_idx_shift_w_3_3 (FF)
+  Requirement:          20.000ns
+  Data Path Delay:      2.874ns (Levels of Logic = 0)
+  Clock Path Skew:      0.000ns
+  Source Clock:         clk_125m rising at 8.000ns
+  Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
+  Clock Uncertainty:    0.000ns
+
+  Maximum Data Path at Slow Process Corner: clks_crossing_125M_62M5/mfifo/r_idx_gray_3 to clks_crossing_125M_62M5/mfifo/Mshreg_r_idx_shift_w_3_3
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X92Y137.BMUX   Tshcko                0.455   clks_crossing_125M_62M5/mfifo/r_idx_bnry<4>
+                                                       clks_crossing_125M_62M5/mfifo/r_idx_gray_3
+    SLICE_X60Y124.CI     net (fanout=2)        2.354   clks_crossing_125M_62M5/mfifo/r_idx_gray<3>
+    SLICE_X60Y124.CLK    Tds                   0.065   clks_crossing_125M_62M5/mfifo/r_idx_shift_w_3<4>
+                                                       clks_crossing_125M_62M5/mfifo/Mshreg_r_idx_shift_w_3_3
+    -------------------------------------------------  ---------------------------
+    Total                                      2.874ns (0.520ns logic, 2.354ns route)
+                                                       (18.1% logic, 81.9% route)
+
+--------------------------------------------------------------------------------
+Hold Paths: ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP "clk_125m" TO TIMEGRP         "clk_62m5_pllxilinx" 20 ns DATAPATHONLY;
+--------------------------------------------------------------------------------
+
+Paths for end point clks_crossing_125M_62M5/sfifo/Mshreg_w_idx_shift_r_3_4 (SLICE_X48Y122.BX), 1 path
+--------------------------------------------------------------------------------
+Slack (hold path):      0.639ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               clks_crossing_125M_62M5/sfifo/w_idx_bnry_4 (FF)
+  Destination:          clks_crossing_125M_62M5/sfifo/Mshreg_w_idx_shift_r_3_4 (FF)
+  Requirement:          0.000ns
+  Data Path Delay:      0.639ns (Levels of Logic = 0)
+  Positive Clock Path Skew: 0.000ns
+  Source Clock:         clk_125m rising at 16.000ns
+  Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
+  Clock Uncertainty:    0.000ns
+
+  Minimum Data Path at Fast Process Corner: clks_crossing_125M_62M5/sfifo/w_idx_bnry_4 to clks_crossing_125M_62M5/sfifo/Mshreg_w_idx_shift_r_3_4
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X53Y128.BQ     Tcko                  0.198   clks_crossing_125M_62M5/sfifo/w_idx_bnry<4>
+                                                       clks_crossing_125M_62M5/sfifo/w_idx_bnry_4
+    SLICE_X48Y122.BX     net (fanout=2)        0.521   clks_crossing_125M_62M5/sfifo/w_idx_bnry<4>
+    SLICE_X48Y122.CLK    Tdh         (-Th)     0.080   clks_crossing_125M_62M5/sfifo/r_idx_shift_a_3<0>
+                                                       clks_crossing_125M_62M5/sfifo/Mshreg_w_idx_shift_r_3_4
+    -------------------------------------------------  ---------------------------
+    Total                                      0.639ns (0.118ns logic, 0.521ns route)
+                                                       (18.5% logic, 81.5% route)
+--------------------------------------------------------------------------------
+
+Paths for end point clks_crossing_125M_62M5/sfifo/Mshreg_w_idx_shift_r_3_0 (SLICE_X48Y122.DX), 1 path
+--------------------------------------------------------------------------------
+Slack (hold path):      0.718ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               clks_crossing_125M_62M5/sfifo/w_idx_gray_0 (FF)
+  Destination:          clks_crossing_125M_62M5/sfifo/Mshreg_w_idx_shift_r_3_0 (FF)
+  Requirement:          0.000ns
+  Data Path Delay:      0.718ns (Levels of Logic = 0)
+  Positive Clock Path Skew: 0.000ns
+  Source Clock:         clk_125m rising at 16.000ns
+  Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
+  Clock Uncertainty:    0.000ns
+
+  Minimum Data Path at Fast Process Corner: clks_crossing_125M_62M5/sfifo/w_idx_gray_0 to clks_crossing_125M_62M5/sfifo/Mshreg_w_idx_shift_r_3_0
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X52Y128.AQ     Tcko                  0.234   clks_crossing_125M_62M5/sfifo/w_idx_gray<2>
+                                                       clks_crossing_125M_62M5/sfifo/w_idx_gray_0
+    SLICE_X48Y122.DX     net (fanout=1)        0.584   clks_crossing_125M_62M5/sfifo/w_idx_gray<0>
+    SLICE_X48Y122.CLK    Tdh         (-Th)     0.100   clks_crossing_125M_62M5/sfifo/r_idx_shift_a_3<0>
+                                                       clks_crossing_125M_62M5/sfifo/Mshreg_w_idx_shift_r_3_0
+    -------------------------------------------------  ---------------------------
+    Total                                      0.718ns (0.134ns logic, 0.584ns route)
+                                                       (18.7% logic, 81.3% route)
+--------------------------------------------------------------------------------
+
+Paths for end point clks_crossing_125M_62M5/sfifo/Mshreg_w_idx_shift_r_3_2 (SLICE_X48Y122.AX), 1 path
+--------------------------------------------------------------------------------
+Slack (hold path):      0.731ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               clks_crossing_125M_62M5/sfifo/w_idx_gray_2 (FF)
+  Destination:          clks_crossing_125M_62M5/sfifo/Mshreg_w_idx_shift_r_3_2 (FF)
+  Requirement:          0.000ns
+  Data Path Delay:      0.731ns (Levels of Logic = 0)
+  Positive Clock Path Skew: 0.000ns
+  Source Clock:         clk_125m rising at 16.000ns
+  Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
+  Clock Uncertainty:    0.000ns
+
+  Minimum Data Path at Fast Process Corner: clks_crossing_125M_62M5/sfifo/w_idx_gray_2 to clks_crossing_125M_62M5/sfifo/Mshreg_w_idx_shift_r_3_2
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X52Y128.DQ     Tcko                  0.234   clks_crossing_125M_62M5/sfifo/w_idx_gray<2>
+                                                       clks_crossing_125M_62M5/sfifo/w_idx_gray_2
+    SLICE_X48Y122.AX     net (fanout=1)        0.567   clks_crossing_125M_62M5/sfifo/w_idx_gray<2>
+    SLICE_X48Y122.CLK    Tdh         (-Th)     0.070   clks_crossing_125M_62M5/sfifo/r_idx_shift_a_3<0>
+                                                       clks_crossing_125M_62M5/sfifo/Mshreg_w_idx_shift_r_3_2
+    -------------------------------------------------  ---------------------------
+    Total                                      0.731ns (0.164ns logic, 0.567ns route)
+                                                       (22.4% logic, 77.6% route)
+--------------------------------------------------------------------------------
+
 ================================================================================
 Timing constraint: TS_pllxilinx_62m5_clk_buf = PERIOD TIMEGRP 
 "pllxilinx_62m5_clk_buf"         TS_tdc_125m_clk_p_i / 0.5 HIGH 50%;
@@ -1108,26 +1434,26 @@ Component Switching Limit Checks: TS_pllxilinx_62m5_clk_buf = PERIOD TIMEGRP "pl
 --------------------------------------------------------------------------------
 Slack: 12.876ns (period - min period limit)
   Period: 16.000ns
-  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
-  Physical resource: clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1/CLKA
-  Logical resource: clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1/CLKA
-  Location pin: RAMB16_X3Y72.CLKA
+  Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
+  Physical resource: clks_crossing_125M_62M5/sfifo/ram/Mram_ram/CLKBRDCLK
+  Logical resource: clks_crossing_125M_62M5/sfifo/ram/Mram_ram/CLKBRDCLK
+  Location pin: RAMB8_X3Y70.CLKBRDCLK
   Clock network: clk_62m5_pllxilinx
 --------------------------------------------------------------------------------
 Slack: 12.876ns (period - min period limit)
   Period: 16.000ns
   Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
-  Physical resource: clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram2/CLKA
-  Logical resource: clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram2/CLKA
-  Location pin: RAMB16_X3Y66.CLKA
+  Physical resource: U_VME_Core/U_Wrapped_VME_Inst_VME_CR_CSR_Space/Mram_CR_addr[11]_s_CR_Space[4095][7]_wide_mux_4097_OUT1/CLKA
+  Logical resource: U_VME_Core/U_Wrapped_VME_Inst_VME_CR_CSR_Space/Mram_CR_addr[11]_s_CR_Space[4095][7]_wide_mux_4097_OUT1/CLKA
+  Location pin: RAMB16_X3Y28.CLKA
   Clock network: clk_62m5_pllxilinx
 --------------------------------------------------------------------------------
 Slack: 12.876ns (period - min period limit)
   Period: 16.000ns
   Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
-  Physical resource: U_VME_Core/U_Wrapped_VME_Inst_VME_CR_CSR_Space/Mram_CR_addr[11]_s_CR_Space[4095][7]_wide_mux_4097_OUT1/CLKA
-  Logical resource: U_VME_Core/U_Wrapped_VME_Inst_VME_CR_CSR_Space/Mram_CR_addr[11]_s_CR_Space[4095][7]_wide_mux_4097_OUT1/CLKA
-  Location pin: RAMB16_X2Y30.CLKA
+  Physical resource: U_VME_Core/U_Wrapped_VME_Inst_VME_CR_CSR_Space/Mram_CR_addr[11]_s_CR_Space[4095][7]_wide_mux_4097_OUT2/CLKA
+  Logical resource: U_VME_Core/U_Wrapped_VME_Inst_VME_CR_CSR_Space/Mram_CR_addr[11]_s_CR_Space[4095][7]_wide_mux_4097_OUT2/CLKA
+  Location pin: RAMB16_X4Y28.CLKA
   Clock network: clk_62m5_pllxilinx
 --------------------------------------------------------------------------------
 
@@ -1136,19 +1462,19 @@ Timing constraint: TS_pllxilinx_62m5_clk_buf_0 = PERIOD TIMEGRP
 "pllxilinx_62m5_clk_buf_0"         TS_tdc_125m_clk_n_i / 0.5 HIGH 50%;
 For more information, see Period Analysis in the Timing Closure User Guide (UG612).
 
- 1917881 paths analyzed, 10463 endpoints analyzed, 0 failing endpoints
+ 1811123 paths analyzed, 10720 endpoints analyzed, 0 failing endpoints
  0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is  14.557ns.
+ Minimum period is  12.835ns.
 --------------------------------------------------------------------------------
 
-Paths for end point U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_21 (SLICE_X0Y48.B4), 87 paths
+Paths for end point U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_20 (SLICE_X37Y69.B1), 6992 paths
 --------------------------------------------------------------------------------
-Slack (setup path):     1.443ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_4 (FF)
-  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_21 (FF)
+Slack (setup path):     3.165ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_5_1 (FF)
+  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_20 (FF)
   Requirement:          16.000ns
-  Data Path Delay:      14.449ns (Levels of Logic = 6)
-  Clock Path Skew:      -0.007ns (0.251 - 0.258)
+  Data Path Delay:      12.783ns (Levels of Logic = 6)
+  Clock Path Skew:      0.049ns (0.863 - 0.814)
   Source Clock:         clk_62m5_pllxilinx rising at 0.000ns
   Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
   Clock Uncertainty:    0.101ns
@@ -1158,42 +1484,43 @@ Slack (setup path):     1.443ns (requirement - (data path - clock path skew + un
     Discrete Jitter (DJ):       0.188ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_4 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_21
+  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_5_1 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_20
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X52Y62.AQ      Tcko                  0.447   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<7>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_4
-    SLICE_X45Y61.B3      net (fanout=17)       0.995   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<4>
-    SLICE_X45Y61.B       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress1
-    SLICE_X45Y61.D2      net (fanout=13)       0.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress
-    SLICE_X45Y61.D       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress2
-    SLICE_X47Y79.C5      net (fanout=17)       1.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_initInProgress
-    SLICE_X47Y79.C       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Mmux_s_CRaddr91
-    SLICE_X46Y58.BX      net (fanout=3)        2.272   U_VME_Core/U_Wrapped_VME/s_CRaddr<1>
-    SLICE_X46Y58.CMUX    Taxc                  0.317   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-    SLICE_X34Y28.B3      net (fanout=13)       3.281   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_CRadd_offset<2>
-    SLICE_X34Y28.B       Tilo                  0.205   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_7<10>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.B4       net (fanout=512)      3.906   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.CLK      Tas                   0.341   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3<23>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Mmux_s_FUNC_AMCAP[3][21]_CRdata_i[5]_MUX_3490_o11
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_21
+    SLICE_X21Y60.AQ      Tcko                  0.391   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_5_1
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_5_1
+    SLICE_X37Y79.C3      net (fanout=4)        2.193   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_5_1
+    SLICE_X37Y79.C       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<30>
+                                                       U_VME_Core/U_Wrapped_VME_Inst_VME_bus/Mram_s_addressingType21
+    SLICE_X24Y56.A3      net (fanout=129)      2.649   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_addressingType<2>
+    SLICE_X24Y56.AMUX    Topaa                 0.382   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[3][31]_s_FUNC_ADEM[3][31]_and_112_OUT<17>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT121721_SW1_lut
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT121721_SW1_cy
+    SLICE_X47Y67.B3      net (fanout=5)        2.439   N579
+    SLICE_X47Y67.B       Tilo                  0.259   N1234
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2471_SW1
+    SLICE_X28Y64.C3      net (fanout=1)        1.365   N1234
+    SLICE_X28Y64.C       Tilo                  0.205   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT48
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2471
+    SLICE_X26Y66.A4      net (fanout=8)        0.897   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT247
+    SLICE_X26Y66.A       Tilo                  0.203   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT39
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT391
+    SLICE_X37Y69.B1      net (fanout=1)        1.219   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT39
+    SLICE_X37Y69.CLK     Tas                   0.322   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr<21>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT394
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_20
     -------------------------------------------------  ---------------------------
-    Total                                     14.449ns (2.087ns logic, 12.362ns route)
-                                                       (14.4% logic, 85.6% route)
+    Total                                     12.783ns (2.021ns logic, 10.762ns route)
+                                                       (15.8% logic, 84.2% route)
 
 --------------------------------------------------------------------------------
-Slack (setup path):     1.465ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_2 (FF)
-  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_21 (FF)
+Slack (setup path):     3.177ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26 (FF)
+  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_20 (FF)
   Requirement:          16.000ns
-  Data Path Delay:      14.428ns (Levels of Logic = 6)
-  Clock Path Skew:      -0.006ns (0.251 - 0.257)
+  Data Path Delay:      12.643ns (Levels of Logic = 7)
+  Clock Path Skew:      -0.079ns (0.863 - 0.942)
   Source Clock:         clk_62m5_pllxilinx rising at 0.000ns
   Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
   Clock Uncertainty:    0.101ns
@@ -1203,42 +1530,47 @@ Slack (setup path):     1.465ns (requirement - (data path - clock path skew + un
     Discrete Jitter (DJ):       0.188ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_2 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_21
+  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_20
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X52Y61.CQ      Tcko                  0.447   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_2
-    SLICE_X45Y61.B2      net (fanout=14)       0.974   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<2>
-    SLICE_X45Y61.B       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress1
-    SLICE_X45Y61.D2      net (fanout=13)       0.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress
-    SLICE_X45Y61.D       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress2
-    SLICE_X47Y79.C5      net (fanout=17)       1.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_initInProgress
-    SLICE_X47Y79.C       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Mmux_s_CRaddr91
-    SLICE_X46Y58.BX      net (fanout=3)        2.272   U_VME_Core/U_Wrapped_VME/s_CRaddr<1>
-    SLICE_X46Y58.CMUX    Taxc                  0.317   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-    SLICE_X34Y28.B3      net (fanout=13)       3.281   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_CRadd_offset<2>
-    SLICE_X34Y28.B       Tilo                  0.205   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_7<10>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.B4       net (fanout=512)      3.906   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.CLK      Tas                   0.341   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3<23>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Mmux_s_FUNC_AMCAP[3][21]_CRdata_i[5]_MUX_3490_o11
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_21
+    SLICE_X32Y84.CQ      Tcko                  0.408   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<27>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26
+    SLICE_X51Y64.D3      net (fanout=8)        4.452   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<26>
+    SLICE_X51Y64.DMUX    Tilo                  0.313   U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/s_CSRarray_220<3>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[0][31]_and_191_OUT<18>1
+    SLICE_X50Y63.C5      net (fanout=2)        0.361   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[0][31]_and_191_OUT<18>
+    SLICE_X50Y63.COUT    Topcyc                0.295   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o_lut<6>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o_cy<7>
+    SLICE_X46Y66.B4      net (fanout=9)        1.103   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o
+    SLICE_X46Y66.BMUX    Topbb                 0.440   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT121
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT1211_lut1
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT1211_cy1
+    SLICE_X31Y66.A2      net (fanout=14)       1.355   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT121
+    SLICE_X31Y66.A       Tilo                  0.259   N1235
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2471_SW2
+    SLICE_X28Y64.C1      net (fanout=1)        0.811   N1235
+    SLICE_X28Y64.C       Tilo                  0.205   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT48
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2471
+    SLICE_X26Y66.A4      net (fanout=8)        0.897   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT247
+    SLICE_X26Y66.A       Tilo                  0.203   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT39
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT391
+    SLICE_X37Y69.B1      net (fanout=1)        1.219   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT39
+    SLICE_X37Y69.CLK     Tas                   0.322   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr<21>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT394
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_20
     -------------------------------------------------  ---------------------------
-    Total                                     14.428ns (2.087ns logic, 12.341ns route)
-                                                       (14.5% logic, 85.5% route)
+    Total                                     12.643ns (2.445ns logic, 10.198ns route)
+                                                       (19.3% logic, 80.7% route)
 
 --------------------------------------------------------------------------------
-Slack (setup path):     1.480ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_5 (FF)
-  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_21 (FF)
+Slack (setup path):     3.257ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26 (FF)
+  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_20 (FF)
   Requirement:          16.000ns
-  Data Path Delay:      14.412ns (Levels of Logic = 6)
-  Clock Path Skew:      -0.007ns (0.251 - 0.258)
+  Data Path Delay:      12.563ns (Levels of Logic = 7)
+  Clock Path Skew:      -0.079ns (0.863 - 0.942)
   Source Clock:         clk_62m5_pllxilinx rising at 0.000ns
   Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
   Clock Uncertainty:    0.101ns
@@ -1248,45 +1580,50 @@ Slack (setup path):     1.480ns (requirement - (data path - clock path skew + un
     Discrete Jitter (DJ):       0.188ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_5 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_21
+  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_20
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X52Y62.BQ      Tcko                  0.447   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<7>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_5
-    SLICE_X45Y61.B4      net (fanout=11)       0.958   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<5>
-    SLICE_X45Y61.B       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress1
-    SLICE_X45Y61.D2      net (fanout=13)       0.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress
-    SLICE_X45Y61.D       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress2
-    SLICE_X47Y79.C5      net (fanout=17)       1.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_initInProgress
-    SLICE_X47Y79.C       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Mmux_s_CRaddr91
-    SLICE_X46Y58.BX      net (fanout=3)        2.272   U_VME_Core/U_Wrapped_VME/s_CRaddr<1>
-    SLICE_X46Y58.CMUX    Taxc                  0.317   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-    SLICE_X34Y28.B3      net (fanout=13)       3.281   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_CRadd_offset<2>
-    SLICE_X34Y28.B       Tilo                  0.205   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_7<10>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.B4       net (fanout=512)      3.906   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.CLK      Tas                   0.341   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3<23>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Mmux_s_FUNC_AMCAP[3][21]_CRdata_i[5]_MUX_3490_o11
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_21
+    SLICE_X32Y84.CQ      Tcko                  0.408   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<27>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26
+    SLICE_X51Y64.D3      net (fanout=8)        4.452   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<26>
+    SLICE_X51Y64.DMUX    Tilo                  0.313   U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/s_CSRarray_220<3>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[0][31]_and_191_OUT<18>1
+    SLICE_X50Y63.C5      net (fanout=2)        0.361   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[0][31]_and_191_OUT<18>
+    SLICE_X50Y63.COUT    Topcyc                0.295   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o_lut<6>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o_cy<7>
+    SLICE_X46Y66.A5      net (fanout=9)        0.994   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o
+    SLICE_X46Y66.BMUX    Topab                 0.469   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT121
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT1211_lut
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT1211_cy1
+    SLICE_X31Y66.A2      net (fanout=14)       1.355   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT121
+    SLICE_X31Y66.A       Tilo                  0.259   N1235
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2471_SW2
+    SLICE_X28Y64.C1      net (fanout=1)        0.811   N1235
+    SLICE_X28Y64.C       Tilo                  0.205   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT48
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2471
+    SLICE_X26Y66.A4      net (fanout=8)        0.897   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT247
+    SLICE_X26Y66.A       Tilo                  0.203   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT39
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT391
+    SLICE_X37Y69.B1      net (fanout=1)        1.219   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT39
+    SLICE_X37Y69.CLK     Tas                   0.322   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr<21>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT394
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_20
     -------------------------------------------------  ---------------------------
-    Total                                     14.412ns (2.087ns logic, 12.325ns route)
-                                                       (14.5% logic, 85.5% route)
+    Total                                     12.563ns (2.474ns logic, 10.089ns route)
+                                                       (19.7% logic, 80.3% route)
 
 --------------------------------------------------------------------------------
 
-Paths for end point U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_23 (SLICE_X0Y48.D5), 87 paths
+Paths for end point U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_18 (SLICE_X30Y68.B1), 6992 paths
 --------------------------------------------------------------------------------
-Slack (setup path):     1.517ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_4 (FF)
-  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_23 (FF)
+Slack (setup path):     3.210ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_5_1 (FF)
+  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_18 (FF)
   Requirement:          16.000ns
-  Data Path Delay:      14.375ns (Levels of Logic = 6)
-  Clock Path Skew:      -0.007ns (0.251 - 0.258)
+  Data Path Delay:      12.740ns (Levels of Logic = 6)
+  Clock Path Skew:      0.051ns (0.865 - 0.814)
   Source Clock:         clk_62m5_pllxilinx rising at 0.000ns
   Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
   Clock Uncertainty:    0.101ns
@@ -1296,42 +1633,43 @@ Slack (setup path):     1.517ns (requirement - (data path - clock path skew + un
     Discrete Jitter (DJ):       0.188ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_4 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_23
+  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_5_1 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_18
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X52Y62.AQ      Tcko                  0.447   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<7>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_4
-    SLICE_X45Y61.B3      net (fanout=17)       0.995   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<4>
-    SLICE_X45Y61.B       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress1
-    SLICE_X45Y61.D2      net (fanout=13)       0.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress
-    SLICE_X45Y61.D       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress2
-    SLICE_X47Y79.C5      net (fanout=17)       1.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_initInProgress
-    SLICE_X47Y79.C       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Mmux_s_CRaddr91
-    SLICE_X46Y58.BX      net (fanout=3)        2.272   U_VME_Core/U_Wrapped_VME/s_CRaddr<1>
-    SLICE_X46Y58.CMUX    Taxc                  0.317   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-    SLICE_X34Y28.B3      net (fanout=13)       3.281   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_CRadd_offset<2>
-    SLICE_X34Y28.B       Tilo                  0.205   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_7<10>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.D5       net (fanout=512)      3.832   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.CLK      Tas                   0.341   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3<23>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Mmux_s_FUNC_AMCAP[3][23]_CRdata_i[7]_MUX_3488_o11
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_23
+    SLICE_X21Y60.AQ      Tcko                  0.391   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_5_1
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_5_1
+    SLICE_X37Y79.C3      net (fanout=4)        2.193   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_5_1
+    SLICE_X37Y79.C       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<30>
+                                                       U_VME_Core/U_Wrapped_VME_Inst_VME_bus/Mram_s_addressingType21
+    SLICE_X24Y56.A3      net (fanout=129)      2.649   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_addressingType<2>
+    SLICE_X24Y56.AMUX    Topaa                 0.382   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[3][31]_s_FUNC_ADEM[3][31]_and_112_OUT<17>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT121721_SW1_lut
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT121721_SW1_cy
+    SLICE_X47Y67.B3      net (fanout=5)        2.439   N579
+    SLICE_X47Y67.B       Tilo                  0.259   N1234
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2471_SW1
+    SLICE_X28Y64.C3      net (fanout=1)        1.365   N1234
+    SLICE_X28Y64.C       Tilo                  0.205   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT48
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2471
+    SLICE_X37Y64.C1      net (fanout=8)        0.918   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT247
+    SLICE_X37Y64.C       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT24
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT301
+    SLICE_X30Y68.B1      net (fanout=1)        1.132   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT30
+    SLICE_X30Y68.CLK     Tas                   0.289   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr<19>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT304
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_18
     -------------------------------------------------  ---------------------------
-    Total                                     14.375ns (2.087ns logic, 12.288ns route)
-                                                       (14.5% logic, 85.5% route)
+    Total                                     12.740ns (2.044ns logic, 10.696ns route)
+                                                       (16.0% logic, 84.0% route)
 
 --------------------------------------------------------------------------------
-Slack (setup path):     1.539ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_2 (FF)
-  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_23 (FF)
+Slack (setup path):     3.222ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26 (FF)
+  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_18 (FF)
   Requirement:          16.000ns
-  Data Path Delay:      14.354ns (Levels of Logic = 6)
-  Clock Path Skew:      -0.006ns (0.251 - 0.257)
+  Data Path Delay:      12.600ns (Levels of Logic = 7)
+  Clock Path Skew:      -0.077ns (0.865 - 0.942)
   Source Clock:         clk_62m5_pllxilinx rising at 0.000ns
   Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
   Clock Uncertainty:    0.101ns
@@ -1341,42 +1679,47 @@ Slack (setup path):     1.539ns (requirement - (data path - clock path skew + un
     Discrete Jitter (DJ):       0.188ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_2 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_23
+  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_18
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X52Y61.CQ      Tcko                  0.447   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_2
-    SLICE_X45Y61.B2      net (fanout=14)       0.974   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<2>
-    SLICE_X45Y61.B       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress1
-    SLICE_X45Y61.D2      net (fanout=13)       0.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress
-    SLICE_X45Y61.D       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress2
-    SLICE_X47Y79.C5      net (fanout=17)       1.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_initInProgress
-    SLICE_X47Y79.C       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Mmux_s_CRaddr91
-    SLICE_X46Y58.BX      net (fanout=3)        2.272   U_VME_Core/U_Wrapped_VME/s_CRaddr<1>
-    SLICE_X46Y58.CMUX    Taxc                  0.317   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-    SLICE_X34Y28.B3      net (fanout=13)       3.281   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_CRadd_offset<2>
-    SLICE_X34Y28.B       Tilo                  0.205   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_7<10>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.D5       net (fanout=512)      3.832   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.CLK      Tas                   0.341   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3<23>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Mmux_s_FUNC_AMCAP[3][23]_CRdata_i[7]_MUX_3488_o11
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_23
+    SLICE_X32Y84.CQ      Tcko                  0.408   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<27>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26
+    SLICE_X51Y64.D3      net (fanout=8)        4.452   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<26>
+    SLICE_X51Y64.DMUX    Tilo                  0.313   U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/s_CSRarray_220<3>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[0][31]_and_191_OUT<18>1
+    SLICE_X50Y63.C5      net (fanout=2)        0.361   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[0][31]_and_191_OUT<18>
+    SLICE_X50Y63.COUT    Topcyc                0.295   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o_lut<6>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o_cy<7>
+    SLICE_X46Y66.B4      net (fanout=9)        1.103   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o
+    SLICE_X46Y66.BMUX    Topbb                 0.440   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT121
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT1211_lut1
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT1211_cy1
+    SLICE_X31Y66.A2      net (fanout=14)       1.355   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT121
+    SLICE_X31Y66.A       Tilo                  0.259   N1235
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2471_SW2
+    SLICE_X28Y64.C1      net (fanout=1)        0.811   N1235
+    SLICE_X28Y64.C       Tilo                  0.205   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT48
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2471
+    SLICE_X37Y64.C1      net (fanout=8)        0.918   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT247
+    SLICE_X37Y64.C       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT24
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT301
+    SLICE_X30Y68.B1      net (fanout=1)        1.132   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT30
+    SLICE_X30Y68.CLK     Tas                   0.289   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr<19>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT304
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_18
     -------------------------------------------------  ---------------------------
-    Total                                     14.354ns (2.087ns logic, 12.267ns route)
-                                                       (14.5% logic, 85.5% route)
+    Total                                     12.600ns (2.468ns logic, 10.132ns route)
+                                                       (19.6% logic, 80.4% route)
 
 --------------------------------------------------------------------------------
-Slack (setup path):     1.554ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_5 (FF)
-  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_23 (FF)
+Slack (setup path):     3.302ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26 (FF)
+  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_18 (FF)
   Requirement:          16.000ns
-  Data Path Delay:      14.338ns (Levels of Logic = 6)
-  Clock Path Skew:      -0.007ns (0.251 - 0.258)
+  Data Path Delay:      12.520ns (Levels of Logic = 7)
+  Clock Path Skew:      -0.077ns (0.865 - 0.942)
   Source Clock:         clk_62m5_pllxilinx rising at 0.000ns
   Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
   Clock Uncertainty:    0.101ns
@@ -1386,45 +1729,50 @@ Slack (setup path):     1.554ns (requirement - (data path - clock path skew + un
     Discrete Jitter (DJ):       0.188ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_5 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_23
+  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_18
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X52Y62.BQ      Tcko                  0.447   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<7>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_5
-    SLICE_X45Y61.B4      net (fanout=11)       0.958   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<5>
-    SLICE_X45Y61.B       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress1
-    SLICE_X45Y61.D2      net (fanout=13)       0.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress
-    SLICE_X45Y61.D       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress2
-    SLICE_X47Y79.C5      net (fanout=17)       1.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_initInProgress
-    SLICE_X47Y79.C       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Mmux_s_CRaddr91
-    SLICE_X46Y58.BX      net (fanout=3)        2.272   U_VME_Core/U_Wrapped_VME/s_CRaddr<1>
-    SLICE_X46Y58.CMUX    Taxc                  0.317   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-    SLICE_X34Y28.B3      net (fanout=13)       3.281   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_CRadd_offset<2>
-    SLICE_X34Y28.B       Tilo                  0.205   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_7<10>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.D5       net (fanout=512)      3.832   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.CLK      Tas                   0.341   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3<23>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Mmux_s_FUNC_AMCAP[3][23]_CRdata_i[7]_MUX_3488_o11
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_23
+    SLICE_X32Y84.CQ      Tcko                  0.408   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<27>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26
+    SLICE_X51Y64.D3      net (fanout=8)        4.452   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<26>
+    SLICE_X51Y64.DMUX    Tilo                  0.313   U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/s_CSRarray_220<3>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[0][31]_and_191_OUT<18>1
+    SLICE_X50Y63.C5      net (fanout=2)        0.361   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[0][31]_and_191_OUT<18>
+    SLICE_X50Y63.COUT    Topcyc                0.295   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o_lut<6>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o_cy<7>
+    SLICE_X46Y66.A5      net (fanout=9)        0.994   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o
+    SLICE_X46Y66.BMUX    Topab                 0.469   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT121
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT1211_lut
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT1211_cy1
+    SLICE_X31Y66.A2      net (fanout=14)       1.355   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT121
+    SLICE_X31Y66.A       Tilo                  0.259   N1235
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2471_SW2
+    SLICE_X28Y64.C1      net (fanout=1)        0.811   N1235
+    SLICE_X28Y64.C       Tilo                  0.205   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT48
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2471
+    SLICE_X37Y64.C1      net (fanout=8)        0.918   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT247
+    SLICE_X37Y64.C       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT24
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT301
+    SLICE_X30Y68.B1      net (fanout=1)        1.132   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT30
+    SLICE_X30Y68.CLK     Tas                   0.289   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr<19>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT304
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_18
     -------------------------------------------------  ---------------------------
-    Total                                     14.338ns (2.087ns logic, 12.251ns route)
-                                                       (14.6% logic, 85.4% route)
+    Total                                     12.520ns (2.497ns logic, 10.023ns route)
+                                                       (19.9% logic, 80.1% route)
 
 --------------------------------------------------------------------------------
 
-Paths for end point U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_22 (SLICE_X0Y48.C5), 87 paths
+Paths for end point U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22 (SLICE_X37Y67.B2), 3457 paths
 --------------------------------------------------------------------------------
-Slack (setup path):     1.533ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_4 (FF)
-  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_22 (FF)
+Slack (setup path):     3.320ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26 (FF)
+  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22 (FF)
   Requirement:          16.000ns
-  Data Path Delay:      14.359ns (Levels of Logic = 6)
-  Clock Path Skew:      -0.007ns (0.251 - 0.258)
+  Data Path Delay:      12.504ns (Levels of Logic = 7)
+  Clock Path Skew:      -0.075ns (0.867 - 0.942)
   Source Clock:         clk_62m5_pllxilinx rising at 0.000ns
   Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
   Clock Uncertainty:    0.101ns
@@ -1434,42 +1782,47 @@ Slack (setup path):     1.533ns (requirement - (data path - clock path skew + un
     Discrete Jitter (DJ):       0.188ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_4 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_22
+  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X52Y62.AQ      Tcko                  0.447   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<7>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_4
-    SLICE_X45Y61.B3      net (fanout=17)       0.995   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<4>
-    SLICE_X45Y61.B       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress1
-    SLICE_X45Y61.D2      net (fanout=13)       0.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress
-    SLICE_X45Y61.D       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress2
-    SLICE_X47Y79.C5      net (fanout=17)       1.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_initInProgress
-    SLICE_X47Y79.C       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Mmux_s_CRaddr91
-    SLICE_X46Y58.BX      net (fanout=3)        2.272   U_VME_Core/U_Wrapped_VME/s_CRaddr<1>
-    SLICE_X46Y58.CMUX    Taxc                  0.317   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-    SLICE_X34Y28.B3      net (fanout=13)       3.281   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_CRadd_offset<2>
-    SLICE_X34Y28.B       Tilo                  0.205   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_7<10>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.C5       net (fanout=512)      3.816   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.CLK      Tas                   0.341   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3<23>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Mmux_s_FUNC_AMCAP[3][22]_CRdata_i[6]_MUX_3489_o11
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_22
+    SLICE_X32Y84.CQ      Tcko                  0.408   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<27>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26
+    SLICE_X51Y64.D3      net (fanout=8)        4.452   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<26>
+    SLICE_X51Y64.DMUX    Tilo                  0.313   U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/s_CSRarray_220<3>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[0][31]_and_191_OUT<18>1
+    SLICE_X50Y63.C5      net (fanout=2)        0.361   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[0][31]_and_191_OUT<18>
+    SLICE_X50Y63.COUT    Topcyc                0.295   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o_lut<6>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o_cy<7>
+    SLICE_X46Y66.B4      net (fanout=9)        1.103   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o
+    SLICE_X46Y66.BMUX    Topbb                 0.440   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT121
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT1211_lut1
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT1211_cy1
+    SLICE_X35Y64.A1      net (fanout=14)       1.246   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT121
+    SLICE_X35Y64.A       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT244
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT51311
+    SLICE_X35Y64.D3      net (fanout=10)       0.332   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT5131
+    SLICE_X35Y64.D       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT244
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2441
+    SLICE_X47Y63.B3      net (fanout=8)        1.099   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT244
+    SLICE_X47Y63.B       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT451
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT452
+    SLICE_X37Y67.B2      net (fanout=1)        1.356   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT451
+    SLICE_X37Y67.CLK     Tas                   0.322   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr<23>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT454
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22
     -------------------------------------------------  ---------------------------
-    Total                                     14.359ns (2.087ns logic, 12.272ns route)
-                                                       (14.5% logic, 85.5% route)
+    Total                                     12.504ns (2.555ns logic, 9.949ns route)
+                                                       (20.4% logic, 79.6% route)
 
 --------------------------------------------------------------------------------
-Slack (setup path):     1.555ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_2 (FF)
-  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_22 (FF)
+Slack (setup path):     3.400ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26 (FF)
+  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22 (FF)
   Requirement:          16.000ns
-  Data Path Delay:      14.338ns (Levels of Logic = 6)
-  Clock Path Skew:      -0.006ns (0.251 - 0.257)
+  Data Path Delay:      12.424ns (Levels of Logic = 7)
+  Clock Path Skew:      -0.075ns (0.867 - 0.942)
   Source Clock:         clk_62m5_pllxilinx rising at 0.000ns
   Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
   Clock Uncertainty:    0.101ns
@@ -1479,42 +1832,47 @@ Slack (setup path):     1.555ns (requirement - (data path - clock path skew + un
     Discrete Jitter (DJ):       0.188ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_2 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_22
+  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X52Y61.CQ      Tcko                  0.447   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_2
-    SLICE_X45Y61.B2      net (fanout=14)       0.974   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<2>
-    SLICE_X45Y61.B       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress1
-    SLICE_X45Y61.D2      net (fanout=13)       0.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress
-    SLICE_X45Y61.D       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress2
-    SLICE_X47Y79.C5      net (fanout=17)       1.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_initInProgress
-    SLICE_X47Y79.C       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Mmux_s_CRaddr91
-    SLICE_X46Y58.BX      net (fanout=3)        2.272   U_VME_Core/U_Wrapped_VME/s_CRaddr<1>
-    SLICE_X46Y58.CMUX    Taxc                  0.317   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-    SLICE_X34Y28.B3      net (fanout=13)       3.281   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_CRadd_offset<2>
-    SLICE_X34Y28.B       Tilo                  0.205   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_7<10>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.C5       net (fanout=512)      3.816   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.CLK      Tas                   0.341   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3<23>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Mmux_s_FUNC_AMCAP[3][22]_CRdata_i[6]_MUX_3489_o11
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_22
+    SLICE_X32Y84.CQ      Tcko                  0.408   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<27>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_26
+    SLICE_X51Y64.D3      net (fanout=8)        4.452   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<26>
+    SLICE_X51Y64.DMUX    Tilo                  0.313   U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/s_CSRarray_220<3>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[0][31]_and_191_OUT<18>1
+    SLICE_X50Y63.C5      net (fanout=2)        0.361   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[0][31]_and_191_OUT<18>
+    SLICE_X50Y63.COUT    Topcyc                0.295   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o_lut<6>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o_cy<7>
+    SLICE_X46Y66.A5      net (fanout=9)        0.994   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[0][31]_s_locAddr[31]_equal_193_o
+    SLICE_X46Y66.BMUX    Topab                 0.469   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT121
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT1211_lut
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT1211_cy1
+    SLICE_X35Y64.A1      net (fanout=14)       1.246   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT121
+    SLICE_X35Y64.A       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT244
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT51311
+    SLICE_X35Y64.D3      net (fanout=10)       0.332   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT5131
+    SLICE_X35Y64.D       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT244
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2441
+    SLICE_X47Y63.B3      net (fanout=8)        1.099   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT244
+    SLICE_X47Y63.B       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT451
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT452
+    SLICE_X37Y67.B2      net (fanout=1)        1.356   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT451
+    SLICE_X37Y67.CLK     Tas                   0.322   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr<23>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT454
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22
     -------------------------------------------------  ---------------------------
-    Total                                     14.338ns (2.087ns logic, 12.251ns route)
-                                                       (14.6% logic, 85.4% route)
+    Total                                     12.424ns (2.584ns logic, 9.840ns route)
+                                                       (20.8% logic, 79.2% route)
 
 --------------------------------------------------------------------------------
-Slack (setup path):     1.570ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_5 (FF)
-  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_22 (FF)
+Slack (setup path):     3.986ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_19 (FF)
+  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22 (FF)
   Requirement:          16.000ns
-  Data Path Delay:      14.322ns (Levels of Logic = 6)
-  Clock Path Skew:      -0.007ns (0.251 - 0.258)
+  Data Path Delay:      11.835ns (Levels of Logic = 8)
+  Clock Path Skew:      -0.078ns (0.867 - 0.945)
   Source Clock:         clk_62m5_pllxilinx rising at 0.000ns
   Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
   Clock Uncertainty:    0.101ns
@@ -1524,34 +1882,42 @@ Slack (setup path):     1.570ns (requirement - (data path - clock path skew + un
     Discrete Jitter (DJ):       0.188ns
     Phase Error (PE):           0.000ns
 
-  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_5 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_22
+  Maximum Data Path at Slow Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_19 to U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X52Y62.BQ      Tcko                  0.447   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<7>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_5
-    SLICE_X45Y61.B4      net (fanout=11)       0.958   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter<5>
-    SLICE_X45Y61.B       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress1
-    SLICE_X45Y61.D2      net (fanout=13)       0.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress
-    SLICE_X45Y61.D       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initReadCounter_3_1
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_initInProgress2
-    SLICE_X47Y79.C5      net (fanout=17)       1.454   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_initInProgress
-    SLICE_X47Y79.C       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Mmux_s_CRaddr91
-    SLICE_X46Y58.BX      net (fanout=3)        2.272   U_VME_Core/U_Wrapped_VME/s_CRaddr<1>
-    SLICE_X46Y58.CMUX    Taxc                  0.317   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_cy<3>
-    SLICE_X34Y28.B3      net (fanout=13)       3.281   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_CRadd_offset<2>
-    SLICE_X34Y28.B       Tilo                  0.205   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_7<10>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.C5       net (fanout=512)      3.816   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Msub_s_CRadd_offset_xor<2>_1
-    SLICE_X0Y48.CLK      Tas                   0.341   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3<23>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/Mmux_s_FUNC_AMCAP[3][22]_CRdata_i[6]_MUX_3489_o11
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_VME_Init/s_FUNC_AMCAP_3_22
+    SLICE_X36Y82.DQ      Tcko                  0.447   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<19>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_19
+    SLICE_X25Y54.C1      net (fanout=9)        3.263   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<19>
+    SLICE_X25Y54.CMUX    Tilo                  0.313   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[3][23]_s_FUNC_ADEM[3][23]_and_118_OUT<11>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[23]_s_FUNC_ADEM[3][23]_and_119_OUT<11>1
+    SLICE_X24Y54.D4      net (fanout=3)        0.799   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[23]_s_FUNC_ADEM[3][23]_and_119_OUT<11>
+    SLICE_X24Y54.COUT    Topcyd                0.260   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[3][31]_s_locAddr[31]_equal_115_o_cy<3>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[3][31]_s_locAddr[31]_equal_115_o_lut<3>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[3][31]_s_locAddr[31]_equal_115_o_cy<3>
+    SLICE_X24Y55.CIN     net (fanout=1)        0.003   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[3][31]_s_locAddr[31]_equal_115_o_cy<3>
+    SLICE_X24Y55.COUT    Tbyp                  0.076   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[3][31]_s_locAddr[31]_equal_115_o
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[3][31]_s_locAddr[31]_equal_115_o_cy<7>
+    SLICE_X32Y54.A3      net (fanout=9)        1.098   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[3][31]_s_locAddr[31]_equal_115_o
+    SLICE_X32Y54.BMUX    Topab                 0.469   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADEM[3][31]_s_isprev_func64[3]_AND_993_o11
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADEM[3][31]_s_isprev_func64[3]_AND_993_o111_lut
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADEM[3][31]_s_isprev_func64[3]_AND_993_o111_cy1
+    SLICE_X35Y64.A3      net (fanout=3)        1.221   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADEM[3][31]_s_isprev_func64[3]_AND_993_o11
+    SLICE_X35Y64.A       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT244
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT51311
+    SLICE_X35Y64.D3      net (fanout=10)       0.332   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT5131
+    SLICE_X35Y64.D       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT244
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2441
+    SLICE_X47Y63.B3      net (fanout=8)        1.099   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT244
+    SLICE_X47Y63.B       Tilo                  0.259   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT451
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT452
+    SLICE_X37Y67.B2      net (fanout=1)        1.356   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT451
+    SLICE_X37Y67.CLK     Tas                   0.322   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr<23>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT454
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22
     -------------------------------------------------  ---------------------------
-    Total                                     14.322ns (2.087ns logic, 12.235ns route)
-                                                       (14.6% logic, 85.4% route)
+    Total                                     11.835ns (2.664ns logic, 9.171ns route)
+                                                       (22.5% logic, 77.5% route)
 
 --------------------------------------------------------------------------------
 
@@ -1559,84 +1925,85 @@ Hold Paths: TS_pllxilinx_62m5_clk_buf_0 = PERIOD TIMEGRP "pllxilinx_62m5_clk_buf
         TS_tdc_125m_clk_n_i / 0.5 HIGH 50%;
 --------------------------------------------------------------------------------
 
-Paths for end point U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM (RAMB8_X2Y41.DIADI4), 1 path
+Paths for end point clks_crossing_125M_62M5/sfifo/Mshreg_r_idx_shift_a_3_0 (SLICE_X48Y122.DI), 1 path
 --------------------------------------------------------------------------------
-Slack (hold path):      0.265ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o_4 (FF)
-  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM (RAM)
+Slack (hold path):      0.394ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               clks_crossing_125M_62M5/sfifo/r_idx_gray_0 (FF)
+  Destination:          clks_crossing_125M_62M5/sfifo/Mshreg_r_idx_shift_a_3_0 (FF)
   Requirement:          0.000ns
-  Data Path Delay:      0.268ns (Levels of Logic = 0)
-  Clock Path Skew:      0.003ns (0.075 - 0.072)
+  Data Path Delay:      0.398ns (Levels of Logic = 0)
+  Clock Path Skew:      0.004ns (0.071 - 0.067)
   Source Clock:         clk_62m5_pllxilinx rising at 16.000ns
   Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
   Clock Uncertainty:    0.000ns
 
-  Minimum Data Path at Fast Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o_4 to U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM
+  Minimum Data Path at Fast Process Corner: clks_crossing_125M_62M5/sfifo/r_idx_gray_0 to clks_crossing_125M_62M5/sfifo/Mshreg_r_idx_shift_a_3_0
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X43Y82.AQ      Tcko                  0.198   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o<7>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o_4
-    RAMB8_X2Y41.DIADI4   net (fanout=1)        0.123   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o<4>
-    RAMB8_X2Y41.CLKAWRCLKTrckd_DIA   (-Th)     0.053   U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM
+    SLICE_X50Y122.CMUX   Tshcko                0.238   clks_crossing_125M_62M5/sfifo/r_idx_bnry<3>
+                                                       clks_crossing_125M_62M5/sfifo/r_idx_gray_0
+    SLICE_X48Y122.DI     net (fanout=2)        0.127   clks_crossing_125M_62M5/sfifo/r_idx_gray<0>
+    SLICE_X48Y122.CLK    Tdh         (-Th)    -0.033   clks_crossing_125M_62M5/sfifo/r_idx_shift_a_3<0>
+                                                       clks_crossing_125M_62M5/sfifo/Mshreg_r_idx_shift_a_3_0
     -------------------------------------------------  ---------------------------
-    Total                                      0.268ns (0.145ns logic, 0.123ns route)
-                                                       (54.1% logic, 45.9% route)
+    Total                                      0.398ns (0.271ns logic, 0.127ns route)
+                                                       (68.1% logic, 31.9% route)
 
 --------------------------------------------------------------------------------
 
-Paths for end point U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM (RAMB8_X2Y41.DIADI6), 1 path
+Paths for end point clks_crossing_125M_62M5/sfifo/r_idx_gray_0 (SLICE_X50Y122.C5), 1 path
 --------------------------------------------------------------------------------
-Slack (hold path):      0.265ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o_6 (FF)
-  Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM (RAM)
+Slack (hold path):      0.401ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               clks_crossing_125M_62M5/sfifo/r_idx_bnry_1 (FF)
+  Destination:          clks_crossing_125M_62M5/sfifo/r_idx_gray_0 (FF)
   Requirement:          0.000ns
-  Data Path Delay:      0.268ns (Levels of Logic = 0)
-  Clock Path Skew:      0.003ns (0.075 - 0.072)
+  Data Path Delay:      0.401ns (Levels of Logic = 1)
+  Clock Path Skew:      0.000ns
   Source Clock:         clk_62m5_pllxilinx rising at 16.000ns
   Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
   Clock Uncertainty:    0.000ns
 
-  Minimum Data Path at Fast Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o_6 to U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM
+  Minimum Data Path at Fast Process Corner: clks_crossing_125M_62M5/sfifo/r_idx_bnry_1 to clks_crossing_125M_62M5/sfifo/r_idx_gray_0
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X43Y82.CQ      Tcko                  0.198   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o<7>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o_6
-    RAMB8_X2Y41.DIADI6   net (fanout=1)        0.123   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o<6>
-    RAMB8_X2Y41.CLKAWRCLKTrckd_DIA   (-Th)     0.053   U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM
+    SLICE_X50Y122.CQ     Tcko                  0.200   clks_crossing_125M_62M5/sfifo/r_idx_bnry<3>
+                                                       clks_crossing_125M_62M5/sfifo/r_idx_bnry_1
+    SLICE_X50Y122.C5     net (fanout=6)        0.080   clks_crossing_125M_62M5/sfifo/r_idx_bnry<1>
+    SLICE_X50Y122.CLK    Tah         (-Th)    -0.121   clks_crossing_125M_62M5/sfifo/r_idx_bnry<3>
+                                                       clks_crossing_125M_62M5/sfifo/Mxor_n0064_1_xo<0>1
+                                                       clks_crossing_125M_62M5/sfifo/r_idx_gray_0
     -------------------------------------------------  ---------------------------
-    Total                                      0.268ns (0.145ns logic, 0.123ns route)
-                                                       (54.1% logic, 45.9% route)
+    Total                                      0.401ns (0.321ns logic, 0.080ns route)
+                                                       (80.0% logic, 20.0% route)
 
 --------------------------------------------------------------------------------
 
-Paths for end point U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM (RAMB8_X2Y41.DIADI1), 1 path
+Paths for end point U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM (RAMB8_X4Y36.DIADI3), 1 path
 --------------------------------------------------------------------------------
-Slack (hold path):      0.267ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o_1 (FF)
+Slack (hold path):      0.402ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o_3 (FF)
   Destination:          U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM (RAM)
   Requirement:          0.000ns
-  Data Path Delay:      0.270ns (Levels of Logic = 0)
-  Clock Path Skew:      0.003ns (0.075 - 0.072)
+  Data Path Delay:      0.409ns (Levels of Logic = 0)
+  Clock Path Skew:      0.007ns (0.067 - 0.060)
   Source Clock:         clk_62m5_pllxilinx rising at 16.000ns
   Destination Clock:    clk_62m5_pllxilinx rising at 16.000ns
   Clock Uncertainty:    0.000ns
 
-  Minimum Data Path at Fast Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o_1 to U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM
+  Minimum Data Path at Fast Process Corner: U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o_3 to U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
-    SLICE_X42Y82.BQ      Tcko                  0.200   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o<3>
-                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o_1
-    RAMB8_X2Y41.DIADI1   net (fanout=1)        0.123   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o<1>
-    RAMB8_X2Y41.CLKAWRCLKTrckd_DIA   (-Th)     0.053   U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM
+    SLICE_X99Y72.DQ      Tcko                  0.198   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o<3>
+                                                       U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o_3
+    RAMB8_X4Y36.DIADI3   net (fanout=1)        0.264   U_VME_Core/U_Wrapped_VME/Inst_VME_bus/CRAMdata_o<3>
+    RAMB8_X4Y36.CLKAWRCLKTrckd_DIA   (-Th)     0.053   U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM
                                                        U_VME_Core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/CRAM_1/Mram_CRAM
     -------------------------------------------------  ---------------------------
-    Total                                      0.270ns (0.147ns logic, 0.123ns route)
-                                                       (54.4% logic, 45.6% route)
+    Total                                      0.409ns (0.145ns logic, 0.264ns route)
+                                                       (35.5% logic, 64.5% route)
 
 --------------------------------------------------------------------------------
 
@@ -1645,26 +2012,26 @@ Component Switching Limit Checks: TS_pllxilinx_62m5_clk_buf_0 = PERIOD TIMEGRP "
 --------------------------------------------------------------------------------
 Slack: 12.876ns (period - min period limit)
   Period: 16.000ns
-  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
-  Physical resource: clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1/CLKA
-  Logical resource: clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram1/CLKA
-  Location pin: RAMB16_X3Y72.CLKA
+  Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
+  Physical resource: clks_crossing_125M_62M5/sfifo/ram/Mram_ram/CLKBRDCLK
+  Logical resource: clks_crossing_125M_62M5/sfifo/ram/Mram_ram/CLKBRDCLK
+  Location pin: RAMB8_X3Y70.CLKBRDCLK
   Clock network: clk_62m5_pllxilinx
 --------------------------------------------------------------------------------
 Slack: 12.876ns (period - min period limit)
   Period: 16.000ns
   Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
-  Physical resource: clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram2/CLKA
-  Logical resource: clks_crossing_125M_62M5/mfifo/ram/true_dp/gen_dual_clk.U_RAM_DC/Mram_ram2/CLKA
-  Location pin: RAMB16_X3Y66.CLKA
+  Physical resource: U_VME_Core/U_Wrapped_VME_Inst_VME_CR_CSR_Space/Mram_CR_addr[11]_s_CR_Space[4095][7]_wide_mux_4097_OUT1/CLKA
+  Logical resource: U_VME_Core/U_Wrapped_VME_Inst_VME_CR_CSR_Space/Mram_CR_addr[11]_s_CR_Space[4095][7]_wide_mux_4097_OUT1/CLKA
+  Location pin: RAMB16_X3Y28.CLKA
   Clock network: clk_62m5_pllxilinx
 --------------------------------------------------------------------------------
 Slack: 12.876ns (period - min period limit)
   Period: 16.000ns
   Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
-  Physical resource: U_VME_Core/U_Wrapped_VME_Inst_VME_CR_CSR_Space/Mram_CR_addr[11]_s_CR_Space[4095][7]_wide_mux_4097_OUT1/CLKA
-  Logical resource: U_VME_Core/U_Wrapped_VME_Inst_VME_CR_CSR_Space/Mram_CR_addr[11]_s_CR_Space[4095][7]_wide_mux_4097_OUT1/CLKA
-  Location pin: RAMB16_X2Y30.CLKA
+  Physical resource: U_VME_Core/U_Wrapped_VME_Inst_VME_CR_CSR_Space/Mram_CR_addr[11]_s_CR_Space[4095][7]_wide_mux_4097_OUT2/CLKA
+  Logical resource: U_VME_Core/U_Wrapped_VME_Inst_VME_CR_CSR_Space/Mram_CR_addr[11]_s_CR_Space[4095][7]_wide_mux_4097_OUT2/CLKA
+  Location pin: RAMB16_X4Y28.CLKA
   Clock network: clk_62m5_pllxilinx
 --------------------------------------------------------------------------------
 
@@ -1686,11 +2053,11 @@ Derived Constraints for TS_tdc_125m_clk_n_i
 |           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
 |                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_tdc_125m_clk_n_i            |      8.000ns|      8.775ns|      7.279ns|           65|            0|      1041148|      1917881|
-| TS_pllxilinx_62m5_clk_buf_0   |     16.000ns|     14.557ns|          N/A|            0|            0|      1917881|            0|
+|TS_tdc_125m_clk_n_i            |      8.000ns|      7.761ns|      6.418ns|            0|            0|       553028|      1811123|
+| TS_pllxilinx_62m5_clk_buf_0   |     16.000ns|     12.835ns|          N/A|            0|            0|      1811123|            0|
 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
 
-1 constraint not met.
+All constraints were met.
 
 
 Data Sheet report:
@@ -1702,7 +2069,7 @@ Clock to Setup on destination clock clk_20m_vcxo_i
                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
 Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
 ---------------+---------+---------+---------+---------+
-clk_20m_vcxo_i |    7.101|         |         |         |
+clk_20m_vcxo_i |    8.039|         |         |         |
 ---------------+---------+---------+---------+---------+
 
 Clock to Setup on destination clock tdc_125m_clk_n_i
@@ -1710,8 +2077,8 @@ Clock to Setup on destination clock tdc_125m_clk_n_i
                 | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
 Source Clock    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
 ----------------+---------+---------+---------+---------+
-tdc_125m_clk_n_i|   14.557|         |         |         |
-tdc_125m_clk_p_i|   14.557|         |         |         |
+tdc_125m_clk_n_i|   12.835|         |         |         |
+tdc_125m_clk_p_i|   12.835|         |         |         |
 ----------------+---------+---------+---------+---------+
 
 Clock to Setup on destination clock tdc_125m_clk_p_i
@@ -1719,33 +2086,34 @@ Clock to Setup on destination clock tdc_125m_clk_p_i
                 | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
 Source Clock    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
 ----------------+---------+---------+---------+---------+
-tdc_125m_clk_n_i|   14.557|         |         |         |
-tdc_125m_clk_p_i|   14.557|         |         |         |
+tdc_125m_clk_n_i|   12.835|         |         |         |
+tdc_125m_clk_p_i|   12.835|         |         |         |
 ----------------+---------+---------+---------+---------+
 
 
 Timing summary:
 ---------------
 
-Timing errors: 65  Score: 23448  (Setup/Max: 23448, Hold: 0)
+Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)
 
-Constraints cover 2959650 paths, 0 nets, and 32094 connections
+Constraints cover 2364789 paths, 0 nets, and 32189 connections
 
 Design statistics:
-   Minimum period:  14.557ns{1}   (Maximum frequency:  68.695MHz)
+   Minimum period:  12.835ns{1}   (Maximum frequency:  77.912MHz)
+   Maximum path delay from/to any node:   4.080ns
 
 
 ------------------------------------Footnotes-----------------------------------
 1)  The minimum period statistic assumes all single cycle delays.
 
-Analysis completed Fri Jul 12 10:36:10 2013 
+Analysis completed Wed Jul 17 22:54:20 2013 
 --------------------------------------------------------------------------------
 
 Trace Settings:
 -------------------------
 Trace Settings 
 
-Peak Memory Usage: 332 MB
+Peak Memory Usage: 335 MB
 
 
 
diff --git a/hdl/svec/xilinx/xilinxprj_svec_tdc.xise b/hdl/svec/xilinx/xilinxprj_svec_tdc.xise
index 9aacee11e80373bcf5e5a7b98c0923a0eb94f03f..2f4a05649978a417d83e01e8186e542d39ac6f88 100644
--- a/hdl/svec/xilinx/xilinxprj_svec_tdc.xise
+++ b/hdl/svec/xilinx/xilinxprj_svec_tdc.xise
@@ -17,91 +17,91 @@
   <files>
     <file xil_pn:name="../hdl/rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="../hdl/rtl/top_tdc.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
     </file>
     <file xil_pn:name="../hdl/rtl/tdc_core_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="../hdl/rtl/clks_rsts_manager.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
     </file>
     <file xil_pn:name="../hdl/rtl/data_formatting.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
     </file>
     <file xil_pn:name="../hdl/rtl/leds_manager.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
     </file>
     <file xil_pn:name="../hdl/rtl/fmc_tdc_core.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
     </file>
     <file xil_pn:name="../hdl/rtl/fmc_tdc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
     </file>
     <file xil_pn:name="../hdl/rtl/circular_buffer.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
     </file>
     <file xil_pn:name="../hdl/rtl/start_retrig_ctrl.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
     </file>
     <file xil_pn:name="../hdl/rtl/reg_ctrl.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
     </file>
     <file xil_pn:name="../hdl/rtl/xvme64x_core.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
     </file>
     <file xil_pn:name="../hdl/rtl/acam_timecontrol_interface.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
     </file>
     <file xil_pn:name="../hdl/rtl/irq_generator.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
     </file>
     <file xil_pn:name="../hdl/rtl/one_hz_gen.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
     </file>
     <file xil_pn:name="../hdl/rtl/acam_databus_interface.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
     </file>
     <file xil_pn:name="../hdl/rtl/sdb_meta_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="../hdl/rtl/data_engine.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
     </file>
     <file xil_pn:name="../hdl/rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="../hdl/rtl/free_counter.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/VMEcore/VME64xCore_Top.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/VMEcore/VME_CR_CSR_Space.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/VMEcore/vme64x_pack.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
@@ -109,83 +109,63 @@
     </file>
     <file xil_pn:name="../hdl/ip_cores/VMEcore/VME_Wb_master.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/VMEcore/VME_swapper.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/VMEcore/VME_IRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/VMEcore/VME_Init.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/VMEcore/VME_Funct_Match.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/VMEcore/VME_CSR_pack.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/VMEcore/VME_CRAM.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/VMEcore/VME_CR_pack.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/VMEcore/VME_bus.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/VMEcore/VME_Am_Match.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/VMEcore/VME_Access_Decode.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
-    </file>
-    <file xil_pn:name="../hdl/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/mem_core/blk_mem_gen_v6_3_flist.txt" xil_pn:type="FILE_USERDOC"/>
-    <file xil_pn:name="../hdl/ip_cores/mem_core/blk_mem_gen_v6_3.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="67"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="../hdl/ip_cores/mem_core/blk_mem_gen_v6_2_readme.txt" xil_pn:type="FILE_USERDOC"/>
     <file xil_pn:name="../hdl/ip_cores/mem_core/blk_mem_gen_v6_2_flist.txt" xil_pn:type="FILE_USERDOC"/>
-    <file xil_pn:name="../hdl/ip_cores/mem_core/blk_mem_gen_v6_2.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
     <file xil_pn:name="../hdl/ip_cores/mem_core/blk_mem_gen_v6_1_flist.txt" xil_pn:type="FILE_USERDOC"/>
-    <file xil_pn:name="../hdl/ip_cores/mem_core/blk_mem_gen_v6_1.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
     <file xil_pn:name="../hdl/ip_cores/mem_core/blk_mem_circ_buff_v6_4_flist.txt" xil_pn:type="FILE_USERDOC"/>
-    <file xil_pn:name="../hdl/ip_cores/mem_core/blk_mem_circ_buff_v6_4.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
     <file xil_pn:name="../hdl/ip_cores/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="113"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="127"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="129"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="131"/>
@@ -193,19 +173,19 @@
     </file>
     <file xil_pn:name="../hdl/ip_cores/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="136"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="137"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="138"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="139"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="142"/>
@@ -213,27 +193,27 @@
     </file>
     <file xil_pn:name="../hdl/ip_cores/wishbone/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="143"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="144"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="145"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="146"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="147"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="148"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="149"/>
@@ -241,39 +221,39 @@
     </file>
     <file xil_pn:name="../hdl/ip_cores/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="150"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="151"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="152"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/wishbone/wb_irq_controller/irq_controller_regs.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="153"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/wishbone/wb_irq_controller/irq_controller.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="58"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="155"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="156"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="157"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="158"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="../hdl/ip_cores/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/>
@@ -362,24 +342,19 @@
     <file xil_pn:name="../ucf/svec_tdc.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../hdl/rtl/extra_pts.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="127"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
     <file xil_pn:name="../hdl/ip_cores/VMEcore/VME_SharedComps.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="128"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
-    </file>
-    <file xil_pn:name="../hdl/ip_cores/mem_core/blk_mem_gen_v6_3.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
     </file>
-    <file xil_pn:name="../hdl/ip_cores/mem_core/blk_mem_gen_v6_2.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    <file xil_pn:name="../hdl/ip_cores/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="161"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
     </file>
-    <file xil_pn:name="../hdl/ip_cores/mem_core/blk_mem_gen_v6_1.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    <file xil_pn:name="../hdl/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="205"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
     </file>
-    <file xil_pn:name="../hdl/ip_cores/mem_core/blk_mem_circ_buff_v6_4.xise" xil_pn:type="FILE_COREGENISE">
+    <file xil_pn:name="../hdl/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc" xil_pn:type="FILE_NGC">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
   </files>