#!   /usr/bin/env   python
#    coding: utf8

# Copyright CERN, 2013
# Author: Matthieu Cattin (CERN)
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 8/5/2012


# Control and status registers of the SVEC board
CARRIER_CSR=['Carrier control and status registers',{
        'CARRIER':[0x00, 'Carrier', {
                'PCB_REV':[0, 'PCB revision', 0x1F],
                'RESERVED':[5, 'Reserved', 0x7FF],
                'TYPE':[16, 'Carrier type', 0xFFFF]}],
        'STAT':[0x04, 'Status', {
                'FMC0_PRES':[0, 'FMC 1 presence (active low)', 0x1],
                'FMC1_PRES':[1, 'FMC 2 presence (active low)', 0x1],
                'SYS_PLL_LCK':[2, 'System PLL locked', 0x1],
                'DDR0_CAL_DONE':[3, 'DDR3 bank 4 calibration done', 0x1],
                'DDR1_CAL_DONE':[4, 'DDR3 bank 5 calibration done', 0x1],
                'RESERVED':[5, 'Reserved', 0xFFFFFFF]}],
        'CTRL':[0x08, 'Control', {
                'LED':[0, 'Front panel LEDs', 0xFFFF],
                'RESERVED':[16, 'Reserved', 0xFFFF]}],
        'RST':[0x0C, 'Reset', {
                'FMC0':[0, 'FMC 1 software reset (active low)', 0x1],
                'FMC1':[1, 'FMC 2 software reset (active low)', 0x1],
                'RESERVED':[2, 'Reserved', 0x3FFFFFFF]}]
        }]
