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High performance pulse and frequency distribution amplifier for time and frequency metrology. The pulse distribution board is an 1:8-channel (1 Hz and up) logic-level distribution amplifier, while the frequency distribution board is an 1:8-channel sine-wave (1-30 MHz) distribution amplifier. Two 1:8 boards fit side-by-sides in a 1U 19" rack enclosure, with either BNC or SMA connectors.

For more information, see the wiki

This library provides a generic API for ADC devices, so that applications can use this API to access any of the supported ADC boards. Currently the library supports the following boards:

fmc-adc-100m14b14cha

For testing and debugging purpose it supports also a couple of virtual boards that you can use to start the development of your application.

More info at the Wiki page

ADC testing procedures and software. More info at the Wiki page

FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU

Uses "IPBus Build" ( ipbb )

Build instructions at Instructions here

FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU

Uses "IPBus Build" ( ipbb )

Build instructions at Instructions here

A system to characterise large area silicon pad sensors with several hundred channels. It consists of two PCBs. One is an active switching 512-to-1 matrix. The second one is a passive probe card to contact the sensor. Testing.

A system to characterise large area silicon pad sensors with several hundred channels. It consists of two PCBs. One is an active switching 512-to-1 matrix. The second one is a passive probe card to contact the sensor. Software.

The AsyncArt Project is comprised by a set of Open-Source HDL libraries and examples targeted to the efficient implementation of Globally Asynchronous, Locally Synchronous (GALS) design architectures over Commercial-Off-The-Shelf FPGA devices.

BabyWR is a general purpose small pluggable WR node in a M.2 form-factor. More info at the Wiki page

Gateware for Beam Position Monitor, including digital signal processing chains, data acquisition engines, ADC and analog front-end peripherals control/monitoring, timing and control system interface.

Software for Beam Position Monitor, including digital signal processing chains, data acquisition engines, ADC and analog front-end peripherals control/monitoring, timing and control system interface.

A cute-wr is a compact WR-node implementation with minimum components required. The initial design is derived from SPEC, but would work in an opposite manner as a FMC wr-nic, providing 2 DIO channels, external CLK input, EEPROM, JTAG, RS232, and expandable IOs through FMC connector. The gateware and software of cute-wr would also keep maximum compatibility with SPEC. Project is obsolete. See cute-wr-dp for a similar board.

Compact Universal Timing Endpoint Based on White Rabbit with Xilinx Artix7. Follow-up of the CUTE-WR-DP. More info at the Wiki page

A VME rear transition module providing fibre-optic and electrical (RS485) inputs and outputs. Uses the CONV-TTL-RS485 as front-module. More info at the Wiki page

A level conversion board between TTL and 24V blocking levels in VME64x form factor. The project uses a rear transition module for connectivity and a front module with the active conversion and diagnostics electronics. More info at the Wiki page

Production and functional tests for Conv TTL Blocking. More info at the Wiki page

Gateware (HDL design) for Conv TTL RS485

Production and functional tests for Conv TTL RS485

DI/OT Kintex Ultrascale-based Peripheral Board with HPC FMC and SODIMM DDR4 slot. More info at the Wiki page