Explore projects
-
Firmware(gateware) for FPGA on AIDA-Innova TLU ( AIDAInnova_TLU )
Updated -
-
Active 32/64 channels 19" patch panel for FPGA boards, with robust 5V TTL I/Os, configurable through I²C and USB-C. More info at the Wiki page
Updated -
A software suite written in Python to help with production tests of PCBs. AKA PTS.
%(red)This pts-base project is used to re-organise the current pts project In the future this project will replace the existing pts project.
Updated -
BabyWR is a general purpose small pluggable WR node in a M.2 form-factor. More info at the Wiki page
Updated -
A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.
Updated -
-
Production and functional tests for PXIe controller COM Express based. More info at the Wiki page
Updated -
Tester board to test PXIe processor modules. Two variants: slot 2 and slot 10 (system timing slot). More info at the Wiki page
Updated -
Powerlink Industrial Ethernet stack. It runs on top of the Hydra rad-tol SoC project. More info at the Wiki page
Updated -
Configuration and boot software required to start up the SPEC7 board
Updated -
Programmable attenuator of RF signals with very high voltage range (50mV – 1000 V) for protecting digitizers against damage by high voltage signals. Four channels with SMA connectors; Three attenuation values: 0, -20, -40 dB; Bandwidth: DC – 2 GHz.
Updated -
Hydra is a RISC-V based radiation-tolerant SoC designed to operate up to 500 Gy TID. See the wiki for more details.
Updated -
A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware. ZIO supports sub-nanosecond timestamps, block-oriented input and output and transport of meta-data with the data samples. Users can change the buffer type and trigger type associated with a device at run time, and all of devices, triggers and buffers are easily implemented as add-on modules.
The PF_ZIO implementation, currently in beta status, implements a network interface to the ZIO transport, which allows each I/O channel to generate or receive network frames. Applications see the network of devices and can talk with several of them from the same socket. We support SOCK_STREAM, SOCK_DGRAM and SOCK_RAW.
Updated -
High-resolution frequency/phase-microstepper for timing laboratories. More info at the Wiki page
Updated -
The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page
Updated -
Updated
-
SAMD21-based monitoring module for DI/OT power supply and fan tray.
Updated -
This is a collection of simple macro implementations for Microsemi's ProASIC3 FPGAs to allow simulating post-synthesis designs using GHDL.
Updated