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This project contains all the HDL gateware necessary for the FPGA of the WR switch.
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This project contains all the HDL gateware necessary for the FPGA of the WR switch.
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A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).
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A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).
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A VHDL core for a VME64x slave. The other side behaves like a Wishbone master.
More info at the Wiki pageUpdated -
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A VHDL core for a VME64x slave. The other side behaves like a Wishbone master.
More info at the Wiki pageUpdated -
The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page
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A simple VME64x carrier for two low pin count FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network. Commercially available. More info at the Wiki page
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The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA
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A software suite written in Python to help with production tests of PCBs. AKA PTS.
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A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.
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A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.
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Mock Turtle is an HDL core of a generic control system node, based on a deterministic multicore CPU architecture. Mock Turtle can use White Rabbit as the means of communication and synchronization in a distributed system. More info at the Wiki page
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A bridge between the local bus of the Gennum GN4124 (PCIe to local bus bridge) and Wishbone.
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Gateware (HDL design) for FMC TDC 1ns 5cha on SPEC and SVEC carriers.
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An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements. Commercially available. More info at the Wiki page
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FmcDIO5chTTLa is a 5-bit port digital IO card in FMC form-factor. Each single-bit port can be configured individually as input or output. The I/Os on LEMO 00 connectors are TTL compatible. Commercially available. More info at the Wiki page
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