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Idrogen is an Arria10 FPGA board with FMC mezzanine.

PCB design is performed by IJCLab / CNRS-IN2P3. Firmware is developed by Observatoire Radioastronomique de Nançay (ORN) / Observatoire de Paris/ CNRS-INSU

Firmware(gateware) for FPGA on AIDA-Innova TLU ( AIDAInnova_TLU )

Collection of WRTD reference designs provided by (and used at) CERN

BabyWR is a general purpose small pluggable WR node in a M.2 form-factor. More info at the Wiki page

Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.

More info at the Wiki page

FMC LPC card with two High Voltage (HV) outputs and one Low Voltage (5-10V) output. Has mV voltage sensing and mA current sensing capabilities. More info at the Wiki page

Test. May be deleted.

Production and functional tests for PXIe controller COM Express based. More info at the Wiki page

This project contains all the HDL gateware necessary for the FPGA of the WR switch.

A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).

Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

Powerlink Industrial Ethernet stack. It runs on top of the Hydra rad-tol SoC project. More info at the Wiki page

A VHDL core for a VME64x slave. The other side behaves like a Wishbone master.

More info at the Wiki page

Hydra is a RISC-V based radiation-tolerant SoC designed to operate up to 500 Gy TID. See the wiki for more details.

FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU

Uses "IPBus Build" ( ipbb )

Build instructions at Instructions here

The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page

The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA

This is a collection of simple macro implementations for Microsemi's ProASIC3 FPGAs to allow simulating post-synthesis designs using GHDL.

The TimIQ system is an IQ modulator allowing to phase shift a radio frequency clock with a resolution of 40 fs and an accuracy of 8 ps. Hardware.