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Gateware (VHDL) for the level conversion board Conv TTL Blocking in VME64x form factor between TTL and blocking levels. More info at the Wiki page

The AsyncArt Project is comprised by a set of Open-Source HDL libraries and examples targeted to the efficient implementation of Globally Asynchronous, Locally Synchronous (GALS) design architectures over Commercial-Off-The-Shelf FPGA devices.

A software suite written in Python to help with production tests of PCBs. AKA PTS.

This project contains all the HDL gateware necessary for the FPGA of the WR switch.

A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.

More info at the Wiki page

Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

Corelib - Project to share generic HDL cores.

FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC low pin count FPGA Mezzanine Card (VITA 57). More info at the Wiki page

The VFC is a VME carrier for two VITA 57 (FMC) mezzanines. For more details please refer to the wiki pages. Obsolete project. Replaced by VFC-HD.