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  • Gateware (HDL design) for FMC TDC 1ns 5cha on SPEC and SVEC carriers.

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  • Projects / FMC TDC 1ns 5cha - Software

    GNU General Public License v2.0 or later

    Host-side software support for the TDC FMC on the SPEC and SVEC FMC carriers.

    More info at the Wiki page

    HW project: https://www.ohwr.org/project/fmc-tdc/wiki
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  • Production and functional tests for FMC TDC 1ns 5cha.

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  • This project defines data structures, to be embedded in the FPGA memory address space, to enumerate the devices that have been synthetized in the current design. The same structure is also used as a simple flash file system. AKA Self-Describing Bus (SDB) Specification for Logic Cores. The layout is simple enough to be parsed both by the host and by the internal soft-core, if any.

    The documentation is public, and related code is GNU GPL licensed.

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  • Rules for low-level software to check an FPGA for sanity, to ease debugging and to provide support for low-level software auto-configuration for byte-order and optional components. More info at Wiki

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  • A fully open electronic watch project featuring an integrated GPS receiver. More info at the Wiki page

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  • The GSI Timing Starter Kit is a functional snapshot of the eventual FAIR timing system, which is under active development. It demonstrates real-time coordination of two front-end equipment controllers. The product consists of a data master (Linux PC) which coordinates events, a timing master which synchronizes clocks (White Rabbit switch), and two front-end equipment controllers (either SPECv4 or SCUv2).

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  • Corelib - Project to share generic HDL cores.

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  • Pascal Bos / Hdlmake

    GNU General Public License v3.0 only

    Tool for generating multi-purpose makefiles for FPGA projects.

    Main features:

    makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

    Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

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  • Brian Koropoff / Hdlmake

    GNU General Public License v3.0 only

    Tool for generating multi-purpose makefiles for FPGA projects.

    Main features:

    makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

    Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

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  • Projects / Hdlmake

    GNU General Public License v3.0 only

    Tool for generating multi-purpose makefiles for FPGA projects.

    Main features:

    makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

    Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

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  • Idrogen is an Arria10 FPGA board with FMC mezzanine.

    PCB design is performed by IJCLab / CNRS-IN2P3. Firmware is developed by Observatoire Radioastronomique de Nançay (ORN) / Observatoire de Paris/ CNRS-INSU

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  • Projects / LHC Instability Trigger Distribution LIST

    GNU General Public License v3.0 only

    LIST is a trigger distribution system based on White Rabbit. It can receive a trigger from a “cloud” of devices and distribute it to all relevant devices to for example freeze their acquisition buffers. The latency between reception and transmission of a trigger is done with a low and notably fixed latency, with an accuracy of better than 1 ns. The hardware of the LIST nodes is based on the SVEC FMC carrier equipped with a FMC TDC mezzanine and a Fine Delay mezzanine. More info at the Wiki page

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  • LIBSFP is a software library that contains generic functions to access SFP devices via I2C.

    More info can be found on this wiki page.

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  • Gateware (HDL design) for MasterFIP.

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  • A meta project used to discuss and present information about Open Hardware and related subjects. More info at the Wiki page More info about the CERN Open Hardware licence More info about the OHR.org site support

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  • Hardware design of the PandABox. Includes schematics, PCB layout and manufacturing files.

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  • PHASE (Portable Hardware Analyzer with Sharing Explorer) aims at unifying hardware debugging in a single tool. From the host machine, a user may graphically interconnect components to describe the connection between his computer and the target device to debug. For example, a USB JTAG cable might be the root node, connected to an Arria2 development board with a CPLD and an FPGA, containing a LM32 processor.

    Wherever possible, PHASE fetches design descriptions from the internet based on the detected JTAG IDCODEs, USB vendor IDs, or PnP BUS information. In the preceding example, each step of the chain would be automatically detected. The USB cable from the vendor+product codes, the FPGA from the JTAG IDCODE and the LM32 from the Arria2's sld hub. The user would now be presented with read/write access to the data and instruction buses for visual inspection or firmware loading. Furthermore, the user could launch gdb to halt and single-step the embedded LM32 CPU.

    If a device is not yet described, the user may assemble a driver out of the reusable software components. For example, an Altera USB-Blaster driver is just a FTDI device chained with a byte packeter and a JTAG bit banger. Once the design has been graphically assembled, it is automatically scanned for attached JTAG devices and the USB cable design is shared online with any future users of the same cable.

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  • Projects / PPSi

    GNU Lesser General Public License v2.1 only

    A Precise Time Protocol (PTP, IEEE 1588) software stack whose single source code can be compiled for many architectures (POSIX systems, WR switch, WR node, ...) and which is easily extensible.

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