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Production and functional tests for FMC TDC 1ns 5cha.

A distributed oscilloscope based on the White Rabbit network. More info at the Wiki page

A VHDL core for a VME64x slave. The other side behaves like a Wishbone master.

Production and functional tests for the MasterFIP.

Gateware (HDL design) for Conv TTL RS485

Production and functional tests for FMC ADC 100M 14b 4cha.

Open design and implementation of a low-cost ventilator for COVID-19 patients. More info at the Wiki page

Production and functional tests for PandABox.

More info at the Wiki page

Gateware for Beam Position Monitor, including digital signal processing chains, data acquisition engines, ADC and analog front-end peripherals control/monitoring, timing and control system interface.

Enumerates the capacitors in an Altium design by parsing the EDIF netlist and library, showing if insufficient voltage ratings are used (derating). More info at the Wiki page

A project to host all software and hardware developments related to testing the White Rabbit switch.

DIOT reliability studies files and reports. More info at the Wiki page

Gateware (HDL design) for FMC TDC 1ns 5cha on SPEC and SVEC carriers.

Couples a MAROC ASIC (64 channels each with a fixed threshold discriminator and a slow shaper + sample-and-hold + 12-bit ADC) to a FPGA. Read-out by Gigabit Ethernet (firmware supplied supports IPBus). Multiple boards can be plugged together to increase the channel count. Clocking circuitry compatible with the White Rabbit implementation of PTP. More info at the Wiki page

Software support for the SVEC board, including kernel and user-space Linux code.

Software for Beam Position Monitor, including digital signal processing chains, data acquisition engines, ADC and analog front-end peripherals control/monitoring, timing and control system interface.

The AsyncArt Project is comprised by a set of Open-Source HDL libraries and examples targeted to the efficient implementation of Globally Asynchronous, Locally Synchronous (GALS) design architectures over Commercial-Off-The-Shelf FPGA devices.

The FMC bus abstraction implements a Linux kernel bus named fmc. This allows to deal with FMC mezzanines in a carrier-independent way

Gateware (HDL design) for FMC ADC 400k 18b 4cha iso on SPEC and SVEC carriers.

Active 32/64 channels 19" patch panel for FPGA boards, with robust 5V TTL I/Os, configurable through I²C and USB-C. More info at the Wiki page