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Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

Detailed documentation on how to get ready to work with the Simple PCI Express Carrier, including hardware deployment instructions, full required toolchain setup and and a collection of step-by-step demonstrative tutorials.

A bridge between the local bus of the Gennum GN4124 (PCIe to local bus bridge) and Wishbone.

Active 32/64 channels 19" patch panel for FPGA boards, with robust 5V TTL I/Os, configurable through I²C and USB-C. More info at the Wiki page

Rules for low-level software to check an FPGA for sanity, to ease debugging and to provide support for low-level software auto-configuration for byte-order and optional components. More info at Wiki

Production and functional tests for FMC TDC 1ns 5cha.

Host-side software support for the TDC FMC on the SPEC and SVEC FMC carriers.

More info at the Wiki page

HW project: https://www.ohwr.org/project/fmc-tdc/wiki

Gateware (HDL design) for FMC TDC 1ns 5cha on SPEC and SVEC carriers.

An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements. Commercially available. More info at the Wiki page

FMC LPC card with two High Voltage (HV) outputs and one Low Voltage (5-10V) output. Has mV voltage sensing and mA current sensing capabilities. More info at the Wiki page

A fine delay generator in FMC format with 1 input and 4 outputs. The resolution is 1 ns. Commercially available. More info at the Wiki page

A fine delay generator in FMC LPC format with 1 input and 2 outputs. The resolution is 1 ns. Optimized for high frequency pulse repetition rates synchronized to an external clock. More info at the Wiki page

Production and functional tests for fmc-dac-600m-12b-1cha-dds

The FMC bus abstraction implements a Linux kernel bus named fmc. This allows to deal with FMC mezzanines in a carrier-independent way

Software to support the FMC ADC 400k 18b 4cha iso mezzanine, including Linux device driver, library and test program.

Gateware (HDL design) for FMC ADC 400k 18b 4cha iso on SPEC and SVEC carriers.

Production and functional tests for FMC ADC 100M 14b 4cha.

Enumerates the capacitors in an Altium design by parsing the EDIF netlist and library, showing if insufficient voltage ratings are used (derating). More info at the Wiki page