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A simple 4-lane PCIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. Commercially available. Linux and Labview drivers available for some mezzanine cards. More info at the Wiki page

The level conversion board project hosts a set of boards in VME form factor, with additional remote diagnostics/monitoring via I2C.

A three-channel TTL to NIM (Nuclear Instrumentation Module) level conversion board in VME form factor. More info at the Wiki page

A converter between USB/Ethernet and WorldFIP, allowing the bus arbitration and control of a WorldFIP fieldbus segment from a USB or Ethernet-equipped computer.

Etherbone is an FPGA-core that connects Ethernet to internal on-chip wishbone buses permitting any core to talk to any other across Ethernet.

DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.

Projects not directly identifiable with PCB or HDL core developments.

ADC testing procedures and software. More info at the Wiki page

A High Pin Count FMC carrier in VXS format with two Virtex 5 FPGAs plus a DSP on board.

RHINO (Reconfigurable Hardware Interface for computiNg and radiO) is a compute platform consisting of a FPGA element with dedicated memory, high speed communication, and FMC-LPC (Vita 57.1) IO expansion slots, all controlled via an ARM Cortex A8 processor running the BORPH operating system.

For progress updates, follow us on twitter @rhinoplatform

Development of software for the White Rabbit switch, and in particular the embedded Linux system running in the ARM9 processor. More info at the Wiki page

Linux device driver and associated utilities for PCIe FMC carriers. Aka GnuRabbit.

A Virtex6-based optical link interface AMC equipped with SFP+ and FMC sockets

A transparent Wishbone bridge between two FPGAs using high-speed serial links. This project is on hold.* More info at the Wiki page

A card used in CERN's Linac 3 for the control of the electromagnetic field inside RF accelerating cavities.

An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements. Commercially available. More info at the Wiki page

An FMC to test the correct mounting of FMC connectors on FMC carrier boards.

OpenPicus is an Italian project made to fill the gap between Embedded Low Cost and Wireless. Picus modules are based on the well known Microchip PIC 24F 16bit processor connected to a Wireless Transceiver (WI-FI or BLUETOOTH). The OpenPicus Framework let you develop your Apps in easy way even without specific experience with Communication protocols. The IDE is also FREE and you can create, compile and download to the modules yoru Apps, no programming tools are needed.

Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

An HPC FMC with 4 Digital to Analog Converter channels working at 250 MS/s with 16-bit resolution.

More information on the wiki page The design is currently used only for the CERN RF-group purposes