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Collection of WRTD reference designs provided by (and used at) CERN

wbgen2 is a tool for generating VHDL/Verilog cores which implement Wishbone bus slaves with certain registers, memory blocks, FIFOs and interrupts. The input is a C-like syntax file with an abstract description of what do we want to have in the slave. As a result, we get:

- Automatically allocated memory layout

- VHDL/Verilog code for the slave module

- C header files for driver development - Nice HTML documentation

Read the wbgen2-Documentation Get the latest version binaries https://www.ohwr.org/attachments/5659/wbgen2-bin.tar.bz2

A project to host all software and hardware developments related to testing the White Rabbit switch.

This project covers the hardware development of version 4 of the White Rabbit switch (WRS-v4). More info at the Wiki page

This project contains all the HDL gateware necessary for the FPGA of the WR switch.

This project contains all the HDL gateware necessary for the FPGA of the WR switch.

The robustness of a White Rabbit Network (WRN) is a broad subject covering methods (HW & SW) which enable to increase overall reliability of a WR-based system. This includes Forward Error Correction (FEC), Quality of Service (QoS) assurance, support of network redundancy, proper network design, thorough diagnostics, and increasing the reliability of network components (i.e. switches, nodes). Here, these methods are described and their implementation sources gathered.

A White Rabbit compliant Network Interface Card (NIC) based on the SPEC and the DIO FMC. This project hosts the HDL and associated software to configure the SPEC so it behaves as a NIC under the Linux OS.

A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).

A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).

Project containing information about how to calibrate White Rabbit gear. See also https://www.ohwr.org/project/white-rabbit/wikis/Calibration More info at the Wiki page

PCIe to VME bridge. More info at the Wiki page

VME board with 36 ADC channels with a sampling rate of 250 kS/s and 16 bits resolution. More info at the Wiki page

A VHDL core for a VME64x slave. The other side behaves like a Wishbone master.

More info at the Wiki page

READ-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS

A VHDL core for a VME64x slave. The other side behaves like a Wishbone master.

More info at the Wiki page

This is a collection of simple macro implementations for Microsemi's ProASIC3 FPGAs to allow simulating post-synthesis designs using GHDL.

VHDL coding style document to be used at ohwr.org The project contains also a tool to automatically check the coding style. More info at the Wiki page

The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page

The TimIQ system is an IQ modulator allowing to phase shift a radio frequency clock with a resolution of 40 fs and an accuracy of 8 ps. Hardware.