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Legacy-VME64x core implements a legacy VME (VMEbus IEEE-1014) and VME64x (based on the vme64x-core) slave.
The core offers for SoC interconnection:
Master WB interconnection and Slave WB for MSI IRQ.The core also provides a universal layer abstraction for common hardware components in VME design (e.g VME buffers). It allows for geographical and hardware switch addressing. More info at the Wiki page
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Idrogen is an Arria10 FPGA board with FMC mezzanine.
PCB design is performed by IJCLab / CNRS-IN2P3. Firmware is developed by Observatoire Radioastronomique de Nançay (ORN) / Observatoire de Paris/ CNRS-INSU
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Hydra is a RISC-V based radiation-tolerant SoC designed to operate up to 500 Gy TID. See the wiki for more details.
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Pascal Bos / Hdlmake
GNU General Public License v3.0 onlyTool for generating multi-purpose makefiles for FPGA projects.
Main features:
makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefilesHdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page
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Brian Koropoff / Hdlmake
GNU General Public License v3.0 onlyTool for generating multi-purpose makefiles for FPGA projects.
Main features:
makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefilesHdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page
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Projects / Hdlmake
GNU General Public License v3.0 onlyTool for generating multi-purpose makefiles for FPGA projects.
Main features:
makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefilesHdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page
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Detailed documentation on how to get ready to work with the Simple PCI Express Carrier, including hardware deployment instructions, full required toolchain setup and and a collection of step-by-step demonstrative tutorials.
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A bridge between the local bus of the Gennum GN4124 (PCIe to local bus bridge) and Wishbone.
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A carrier for two low pin count FPGA Mezzanine Cards (VITA 57), analog inputs and fail-safe functionality. It has memory and clocking resources and supports the White Rabbit timing and control network. Stand-alone board for use in a 'pizza-box'. More info at the Wiki page
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Gateware (HDL design) for FMC TDC 1ns 5cha on SPEC and SVEC carriers.
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An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements. Commercially available. More info at the Wiki page
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Projects / FMC High-Voltage supply - fmc-hv-2ch
GNU Lesser General Public License v2.1 onlyFMC LPC card with two High Voltage (HV) outputs and one Low Voltage (5-10V) output. Has mV voltage sensing and mA current sensing capabilities. More info at the Wiki page
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FmcDIO5chTTLa is a 5-bit port digital IO card in FMC form-factor. Each single-bit port can be configured individually as input or output. The I/Os on LEMO 00 connectors are TTL compatible. Commercially available. More info at the Wiki page
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Projects / FMC DEL 1ns 4cha - stand-alone application
GNU General Public License v3.0 onlyA fully operational stand-alone FMC Delay card based White-Rabbit node which can be initialized and perform periodic calibrations without requiring to be plugged on a PC, reducing final system cost, size and power consumption. More info at the Wiki page
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A fine delay generator in FMC format with 1 input and 4 outputs. The resolution is 1 ns. Commercially available. More info at the Wiki page
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Projects / FMC DEL 1ns 2cha
GNU Lesser General Public License v2.1 onlyA fine delay generator in FMC LPC format with 1 input and 2 outputs. The resolution is 1 ns. Optimized for high frequency pulse repetition rates synchronized to an external clock. More info at the Wiki page
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Production and functional tests for fmc-dac-600m-12b-1cha-dds
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