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The TimEX3 is a multipurpose compact PCI board designed to perform simple to medium complex logical functions. It is mainly used for the synchronization system of SOLEIL (signal duplication, top-up gating, etc.). This board is based on a Spartan-6 FPGA and PLX PCI9030 interface. It is designed with KiCad software, and released under CERN OHL License.

TiCkS is a flexible White Rabbit based time-stamping board. It is based on the SPEC board developed for the CTA collaboration. It provides an interface to a CTA camera (Inputs: Read-out Trigger signals, Busy Trigger), (Outputs: PPS signal , 10MHz clock, External trigger signal).

More info at the Wiki page

Test. May be deleted.

A Time to Digital Converter core for Spartan 6 FPGAs.

A simple 4-lane PCIe carrier for a FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. More info at the Wiki page

A simple VME64x carrier for two low pin count FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network. Commercially available. More info at the Wiki page

A simple 4-lane PCIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. Commercially available. Linux and Labview drivers available for some mezzanine cards. More info at the Wiki page

Couples a MAROC ASIC (64 channels each with a fixed threshold discriminator and a slow shaper + sample-and-hold + 12-bit ADC) to a FPGA. Read-out by Gigabit Ethernet (firmware supplied supports IPBus). Multiple boards can be plugged together to increase the channel count. Clocking circuitry compatible with the White Rabbit implementation of PTP. More info at the Wiki page

The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA

Production and functional tests for PXIe controller COM Express based. More info at the Wiki page

A software suite written in Python to help with production tests of PCBs. AKA PTS.

Powerlink Industrial Ethernet stack. It runs on top of the Hydra rad-tol SoC project. More info at the Wiki page

A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.

More info at the Wiki page

A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.

More info at the Wiki page

A VHDL core for a PCI slave. The other side behaves like a Wishbone master.

More info at the Wiki page

The nanoFIP test board is used to test the functionality of the nanoFIP design. Apart from the nanoFIP chip, the FielDrive and the FieldTR it houses another Actel FPGA that can access nanoFIP in stand-alone or in memory mode. This FPGA can also communicate through a RS232 port with a windows PC running the NFTC software. The components on the board are placed in such a way that with a focused beam, radiation tests can be performed to the nanoFIP, FielDrive and FieldTR, leaving the rest if the components in a radiation-safe zone. The card has been designed by the company HLP.

Gateware (HDL design) for nanoFIP.

Multi-channel Time Interval Counter and fine delay generator. Housed in a 19" module. Research project. More info at the Wiki page

Mock Turtle is an HDL core of a generic control system node, based on a deterministic multicore CPU architecture. Mock Turtle can use White Rabbit as the means of communication and synchronization in a distributed system. More info at the Wiki page