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Corelib - Project to share generic HDL cores.

A carrier for two low pin count FPGA Mezzanine Cards (VITA 57), analog inputs and fail-safe functionality. It has memory and clocking resources and supports the White Rabbit timing and control network. Stand-alone board for use in a 'pizza-box'. More info at the Wiki page

A fine delay generator in FMC LPC format with 1 input and 2 outputs. The resolution is 1 ns. Optimized for high frequency pulse repetition rates synchronized to an external clock. More info at the Wiki page

Production and functional tests for fmc-dac-600m-12b-1cha-dds

Gateware (HDL design) for FMC ADC 100M 14b 4cha on SPEC and SVEC carriers.

FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC low pin count FPGA Mezzanine Card (VITA 57). More info at the Wiki page

This project contains gateware for the Distributed IO Tier demonstrator according to the CERN Warm Interlocks specification

Gateware (VHDL) for the level conversion board Conv TTL Blocking in VME64x form factor between TTL and blocking levels. More info at the Wiki page

The AsyncArt Project is comprised by a set of Open-Source HDL libraries and examples targeted to the efficient implementation of Globally Asynchronous, Locally Synchronous (GALS) design architectures over Commercial-Off-The-Shelf FPGA devices.

A low cost, low complexity FMC carrier based on Xilinx Artix-7