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A low cost, low complexity FMC carrier based on Xilinx Artix-7
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DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.
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Gateware (HDL design) for FMC ADC 100M 14b 4cha on SPEC and SVEC carriers.
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A carrier for two low pin count FPGA Mezzanine Cards (VITA 57), analog inputs and fail-safe functionality. It has memory and clocking resources and supports the White Rabbit timing and control network. Stand-alone board for use in a 'pizza-box'. More info at the Wiki page
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A VHDL core for a PCI slave. The other side behaves like a Wishbone master.
More info at the Wiki pageUpdated -
A software suite written in Python to help with production tests of PCBs. AKA PTS.
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Production and functional tests for PXIe controller COM Express based. More info at the Wiki page
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