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Idrogen is an Arria10 FPGA board with FMC mezzanine.
PCB design is performed by IJCLab / CNRS-IN2P3. Firmware is developed by Observatoire Radioastronomique de Nançay (ORN) / Observatoire de Paris/ CNRS-INSU
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David Cussans / AIDAInnova_TLU-gw
GNU General Public License v3.0 or laterFirmware(gateware) for FPGA on AIDA-Innova TLU ( AIDAInnova_TLU )
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BabyWR is a general purpose small pluggable WR node in a M.2 form-factor. More info at the Wiki page
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Brian Koropoff / Hdlmake
GNU General Public License v3.0 onlyTool for generating multi-purpose makefiles for FPGA projects.
Main features:
makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefilesHdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page
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Production and functional tests for PXIe controller COM Express based. More info at the Wiki page
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A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).
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Pascal Bos / Hdlmake
GNU General Public License v3.0 onlyTool for generating multi-purpose makefiles for FPGA projects.
Main features:
makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefilesHdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page
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Projects / powerlink
BSD 3-Clause "New" or "Revised" LicensePowerlink Industrial Ethernet stack. It runs on top of the Hydra rad-tol SoC project. More info at the Wiki page
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Compact Universal Timing Endpoint Based on White Rabbit with Xilinx Artix7. Follow-up of the CUTE-WR-DP. More info at the Wiki page
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FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU
Uses "IPBus Build" ( ipbb )
Build instructions at Instructions here
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This project hosts compliance tests dedicated for WR devices and based on the ATTEST framework available from Veryx Technologies. To use the material available in this project, the ATTEST framework needs to be purchased.
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Projects / Euro ADC 65M 14b 40cha gw PUMA-gw
Apache License 2.0Updated -
Projects / AIDA-2020 TLU - Software
GNU Affero General Public License v3.0Updated -
Projects / AIDA-2020 TLU - Gateware
GNU General Public License v3.0 or laterFPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU
Uses "IPBus Build" ( ipbb )
Build instructions at Instructions here
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This project covers the hardware development of version 4 of the White Rabbit switch (WRS-v4). More info at the Wiki page
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A simple 4-lane PCIe carrier for a FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. More info at the Wiki page
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A low cost, low complexity FMC carrier based on Xilinx Artix-7
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Project containing information about how to calibrate White Rabbit gear. See also https://www.ohwr.org/project/white-rabbit/wikis/Calibration More info at the Wiki page
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