Explore projects

DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.

Compact Universal Timing Endpoint Based on White Rabbit with Xilinx Artix7. Follow-up of the CUTE-WR-DP. More info at the Wiki page

Gateware for Beam Position Monitor, including digital signal processing chains, data acquisition engines, ADC and analog front-end peripherals control/monitoring, timing and control system interface.

BabyWR is a general purpose small pluggable WR node in a M.2 form-factor. More info at the Wiki page

A low cost, low complexity FMC carrier based on Xilinx Artix-7

Firmware(gateware) for FPGA on AIDA-Innova TLU ( AIDAInnova_TLU )

FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU

Uses "IPBus Build" ( ipbb )

Build instructions at Instructions here

FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU

Uses "IPBus Build" ( ipbb )

Build instructions at Instructions here

VHDL core for absolute position encoders (SSI, BISS, ENDAT).

More info at the Wiki page