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READ-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS

This project contains all the HDL gateware necessary for the FPGA of the WR switch.

A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).

A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.

More info at the Wiki page

A VHDL core for a VME64x slave. The other side behaves like a Wishbone master.

More info at the Wiki page

Collection of WRTD reference designs provided by (and used at) CERN

An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements. Commercially available. More info at the Wiki page

FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC low pin count FPGA Mezzanine Card (VITA 57). More info at the Wiki page

A fine delay generator in FMC format with 1 input and 4 outputs. The resolution is 1 ns. Commercially available. More info at the Wiki page

Mock Turtle is an HDL core of a generic control system node, based on a deterministic multicore CPU architecture. Mock Turtle can use White Rabbit as the means of communication and synchronization in a distributed system. More info at the Wiki page

White Rabbit Trigger Distribution project. More info at the Wiki page

The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA

This project contains gateware for the Distributed IO Tier demonstrator according to the CERN Warm Interlocks specification

Gateware (HDL design) for FMC TDC 1ns 5cha on SPEC and SVEC carriers.

Gateware (HDL design) for FMC ADC 100M 14b 4cha on SPEC and SVEC carriers.

A software suite written in Python to help with production tests of PCBs. AKA PTS.

FmcDIO5chTTLa is a 5-bit port digital IO card in FMC form-factor. Each single-bit port can be configured individually as input or output. The I/Os on LEMO 00 connectors are TTL compatible. Commercially available. More info at the Wiki page

DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.

A bridge between the local bus of the Gennum GN4124 (PCIe to local bus bridge) and Wishbone.

The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page