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Mock Turtle is an HDL core of a generic control system node, based on a deterministic multicore CPU architecture. Mock Turtle can use White Rabbit as the means of communication and synchronization in a distributed system. More info at the Wiki page

A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).

Firmware(gateware) for FPGA on AIDA-Innova TLU ( AIDAInnova_TLU )

FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU

Uses "IPBus Build" ( ipbb )

Build instructions at Instructions here

Collection of WRTD reference designs provided by (and used at) CERN

TiCkS is a flexible White Rabbit based time-stamping board. It is based on the SPEC board developed for the CTA collaboration. It provides an interface to a CTA camera (Inputs: Read-out Trigger signals, Busy Trigger), (Outputs: PPS signal , 10MHz clock, External trigger signal).

More info at the Wiki page

BabyWR is a general purpose small pluggable WR node in a M.2 form-factor. More info at the Wiki page

A White Rabbit compliant Network Interface Card (NIC) based on the SPEC and the DIO FMC. This project hosts the HDL and associated software to configure the SPEC so it behaves as a NIC under the Linux OS.

Etherbone is an FPGA-core that connects Ethernet to internal on-chip wishbone buses permitting any core to talk to any other across Ethernet.

Couples a MAROC ASIC (64 channels each with a fixed threshold discriminator and a slow shaper + sample-and-hold + 12-bit ADC) to a FPGA. Read-out by Gigabit Ethernet (firmware supplied supports IPBus). Multiple boards can be plugged together to increase the channel count. Clocking circuitry compatible with the White Rabbit implementation of PTP. More info at the Wiki page

Gateware (HDL design) for nanoFIP.

Project containing information about how to calibrate White Rabbit gear. See also https://www.ohwr.org/project/white-rabbit/wikis/Calibration More info at the Wiki page

A software suite written in Python to help with production tests of PCBs. AKA PTS.

Production and functional tests for Conv TTL Blocking. More info at the Wiki page

Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

VHDL core for absolute position encoders (SSI, BISS, ENDAT).

More info at the Wiki page

A fully operational stand-alone FMC Delay card based White-Rabbit node which can be initialized and perform periodic calibrations without requiring to be plugged on a PC, reducing final system cost, size and power consumption. More info at the Wiki page

A VHDL core for a PCI slave. The other side behaves like a Wishbone master.

More info at the Wiki page

Corelib - Project to share generic HDL cores.

The nanoFIP test board is used to test the functionality of the nanoFIP design. Apart from the nanoFIP chip, the FielDrive and the FieldTR it houses another Actel FPGA that can access nanoFIP in stand-alone or in memory mode. This FPGA can also communicate through a RS232 port with a windows PC running the NFTC software. The components on the board are placed in such a way that with a focused beam, radiation tests can be performed to the nanoFIP, FielDrive and FieldTR, leaving the rest if the components in a radiation-safe zone. The card has been designed by the company HLP.