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Gateware for Beam Position Monitor, including digital signal processing chains, data acquisition engines, ADC and analog front-end peripherals control/monitoring, timing and control system interface.
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A project to host all software and hardware developments related to testing the White Rabbit switch.
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Gateware (HDL design) for FMC ADC 100M 14b 4cha on SPEC and SVEC carriers.
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Gateware (HDL design) for FMC TDC 1ns 5cha on SPEC and SVEC carriers.
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The TimEX3 is a multipurpose compact PCI board designed to perform simple to medium complex logical functions. It is mainly used for the synchronization system of SOLEIL (signal duplication, top-up gating, etc.). This board is based on a Spartan-6 FPGA and PLX PCI9030 interface. It is designed with KiCad software, and released under CERN OHL License.
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This project contains gateware for the Distributed IO Tier demonstrator according to the CERN Warm Interlocks specification
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Common gateware for the different level conversion circuits.
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Projects / AsyncArt
GNU Lesser General Public License v2.1 onlyThe AsyncArt Project is comprised by a set of Open-Source HDL libraries and examples targeted to the efficient implementation of Globally Asynchronous, Locally Synchronous (GALS) design architectures over Commercial-Off-The-Shelf FPGA devices.
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hdl-core-lib / vme64x-core
GNU Lesser General Public License v2.1 onlyREAD-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS
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Gateware (HDL design) for FMC ADC 400k 18b 4cha iso on SPEC and SVEC carriers.
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VME board with 36 ADC channels with a sampling rate of 250 kS/s and 16 bits resolution. More info at the Wiki page
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Detailed documentation on how to get ready to work with the Simple PCI Express Carrier, including hardware deployment instructions, full required toolchain setup and and a collection of step-by-step demonstrative tutorials.
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Gateware (VHDL) for the level conversion board Conv TTL Blocking in VME64x form factor between TTL and blocking levels. More info at the Wiki page
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The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page
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Legacy-VME64x core implements a legacy VME (VMEbus IEEE-1014) and VME64x (based on the vme64x-core) slave.
The core offers for SoC interconnection:
Master WB interconnection and Slave WB for MSI IRQ.The core also provides a universal layer abstraction for common hardware components in VME design (e.g VME buffers). It allows for geographical and hardware switch addressing. More info at the Wiki page
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A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.
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This project contains all the HDL gateware necessary for the FPGA of the WR switch.
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