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A carrier for two low pin count FPGA Mezzanine Cards (VITA 57), analog inputs and fail-safe functionality. It has memory and clocking resources and supports the White Rabbit timing and control network. Stand-alone board for use in a 'pizza-box'. More info at the Wiki page
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The TimIQ system is an IQ modulator allowing to phase shift a radio frequency clock with a resolution of 40 fs and an accuracy of 8 ps. Hardware.
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A bridge between the local bus of the Gennum GN4124 (PCIe to local bus bridge) and Wishbone.
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Pascal Bos / Hdlmake
GNU General Public License v3.0 onlyTool for generating multi-purpose makefiles for FPGA projects.
Main features:
makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefilesHdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page
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Multi-channel Time Interval Counter and fine delay generator. Housed in a 19" module. Research project. More info at the Wiki page
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VHDL coding style document to be used at ohwr.org The project contains also a tool to automatically check the coding style. More info at the Wiki page
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Production and functional tests for PXIe controller COM Express based. More info at the Wiki page
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Hydra is a RISC-V based radiation-tolerant SoC designed to operate up to 500 Gy TID. See the wiki for more details.
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The robustness of a White Rabbit Network (WRN) is a broad subject covering methods (HW & SW) which enable to increase overall reliability of a WR-based system. This includes Forward Error Correction (FEC), Quality of Service (QoS) assurance, support of network redundancy, proper network design, thorough diagnostics, and increasing the reliability of network components (i.e. switches, nodes). Here, these methods are described and their implementation sources gathered.
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Projects / VHDL macro libraries for Microsemi ProASIC3
GNU Affero General Public License v3.0This is a collection of simple macro implementations for Microsemi's ProASIC3 FPGAs to allow simulating post-synthesis designs using GHDL.
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Projects / Euro ADC 65M 14b 40cha gw PUMA-gw
Apache License 2.0Updated -
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The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA
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A low cost, low complexity FMC carrier based on Xilinx Artix-7
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This project contains all the HDL gateware necessary for the FPGA of the WR switch.
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Mathieu Saccani / VME64x core - msaccani
GNU Lesser General Public License v2.1 onlyA VHDL core for a VME64x slave. The other side behaves like a Wishbone master.
More info at the Wiki pageUpdated -
DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.
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