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  • Projects / Hdlmake

    GNU General Public License v3.0 only

    Tool for generating multi-purpose makefiles for FPGA projects.

    Main features:

    makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

    Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

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  • A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).

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  • Projects / FMC DEL 1ns 2cha

    GNU Lesser General Public License v2.1 only

    A fine delay generator in FMC LPC format with 1 input and 2 outputs. The resolution is 1 ns. Optimized for high frequency pulse repetition rates synchronized to an external clock. More info at the Wiki page

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  • Idrogen is an Arria10 FPGA board with FMC mezzanine.

    PCB design is performed by IJCLab / CNRS-IN2P3. Firmware is developed by Observatoire Radioastronomique de Nançay (ORN) / Observatoire de Paris/ CNRS-INSU

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  • Projects / powerlink

    BSD 3-Clause "New" or "Revised" License

    Powerlink Industrial Ethernet stack. It runs on top of the Hydra rad-tol SoC project. More info at the Wiki page

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  • Projects / AIDA-2020 TLU - Software

    GNU Affero General Public License v3.0
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  • A simple 4-lane PCIe carrier for a FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. More info at the Wiki page

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  • This project covers the hardware development of version 4 of the White Rabbit switch (WRS-v4). More info at the Wiki page

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  • Projects / AIDA-2020 TLU - Gateware

    GNU General Public License v3.0 or later

    FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU

    Uses "IPBus Build" ( ipbb )

    Build instructions at Instructions here

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  • Brian Koropoff / Hdlmake

    GNU General Public License v3.0 only

    Tool for generating multi-purpose makefiles for FPGA projects.

    Main features:

    makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

    Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

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  • Compact Universal Timing Endpoint Based on White Rabbit with Xilinx Artix7. Follow-up of the CUTE-WR-DP. More info at the Wiki page

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  • A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).

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  • Test. May be deleted.

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  • Gateware for Beam Position Monitor, including digital signal processing chains, data acquisition engines, ADC and analog front-end peripherals control/monitoring, timing and control system interface.

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  • This project hosts compliance tests dedicated for WR devices and based on the ATTEST framework available from Veryx Technologies. To use the material available in this project, the ATTEST framework needs to be purchased.

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  • The robustness of a White Rabbit Network (WRN) is a broad subject covering methods (HW & SW) which enable to increase overall reliability of a WR-based system. This includes Forward Error Correction (FEC), Quality of Service (QoS) assurance, support of network redundancy, proper network design, thorough diagnostics, and increasing the reliability of network components (i.e. switches, nodes). Here, these methods are described and their implementation sources gathered.

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  • We have designed an FPGA Mezzanine card (standard FMC/Vita 57) for high-channel-count electrophysiology, with 128 channels (potentially up to 512), based upon Intan Tech's RHA2132 (2 uV rms input-referred noise), sampled at 25kHz 18bit by AD7982. We are basing our design on the reference design provided by Reid Harrison of Intan Tech for their 16-channel evaluation board. The expected cost of the device should be under 5000$.

    In order to have an integrated solution we intend to have as default carrier the Opal Kelly Shuttle LX1, an inexpensive USB FMC carrier with an excellent USB controller. The integrated solution will be completed with software on the PC side to grab to disk continuously and/or display in some fashion all 128 channels.

    Our status: We have an alpha card. It has passed most tests---we can grab from any channel at 1MS/s. We have an alpha microcode: it grabs from any channel and stores on the PC.

    Our current team: Marcelo Magnasco (Rockefeller University, New York), design. Andres Cicuttin (ICTP, Trieste), schematics + fpga Maria Liz Crespo (ICTP, Trieste), fpga Sanjee Abeytunge (MSKCC, New York) layout Nicholas Joseph (RU) Macintosh drivers

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  • Couples a MAROC ASIC (64 channels each with a fixed threshold discriminator and a slow shaper + sample-and-hold + 12-bit ADC) to a FPGA. Read-out by Gigabit Ethernet (firmware supplied supports IPBus). Multiple boards can be plugged together to increase the channel count. Clocking circuitry compatible with the White Rabbit implementation of PTP. More info at the Wiki page

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