Skip to content

E
euro-adc-65m-14b-40cha-gw
Commit fd569f95 authored by Dave Newbold's avatar Dave Newbold
Browse files
Options

Adding channel state machine, updating enable signals

parent dbb2c5c4
Hide whitespace changes
Inline Side-by-side
Showing with 92 additions and 36 deletions
components/solid/addr_table/sc_chan.xml
View file @ fd569f95
......@@ -13,7 +13,7 @@
<node id="buf_full" mask="0x2"/>
<node id="dr_full" mask="0x4"/>
<node id="dr_warn" mask="0x8"/>
<node id="err" mask="0x10"/>
<node id="state" mask="0x70"/>
<node id="slip" mask="0xff00"/>
<node id="tap" mask="0x1f0000"/>
</node>
......
components/solid/firmware/hdl/sc_chan.vhd
View file @ fd569f95
......@@ -40,8 +40,8 @@ entity sc_chan is
nzs_blks: in std_logic_vector(3 downto 0);
nzs_en: in std_logic;
zs_en: in std_logic;
dr_en: in std_logic;
keep: in std_logic;
flush: in std_logic;
kack: out std_logic;
err: out std_logic;
trig: out std_logic_vector(N_CHAN_TRG - 1 downto 0);
......@@ -73,7 +73,14 @@ architecture rtl of sc_chan is
signal zs_thresh: std_logic_vector(13 downto 0);
signal sctr_p: std_logic_vector(11 downto 0);
signal dr_d: std_logic_vector(31 downto 0);
signal ro_en, err_i, blkend, dr_blkend, dr_wen: std_logic;
signal blkend, dr_blkend, dr_wen: std_logic;
type state_t is (ST_DIS, ST_WAIT, ST_RUN, ST_VETO, ST_ERR);
signal state: state_t;
signal nzs_en_d, dr_empty, enb, enb_d, zs_en_i, dr_en_i: std_logic;
signal state_dec: std_logic_vector(2 downto 0);
attribute ASYNC_REG: string;
attribute ASYNC_REG of enb, enb_d: signal is "yes";
begin
......@@ -120,7 +127,7 @@ begin
cap <= sync_ctrl(2) and ctrl_en_sync; -- CDC
inc <= sync_ctrl(3) and ctrl_en_sync; -- CDC
stat(0) <= X"00" & "000" & cntout & std_logic_vector(act_slip) & "000" & err_i & dr_warn & dr_full & buf_full & cap_full; -- CDC
stat(0) <= X"00" & "000" & cntout & std_logic_vector(act_slip) & '0' & state_dec & dr_warn & dr_full & buf_full & cap_full; -- CDC
-- Keep track of slips and taps for debug
......@@ -166,12 +173,67 @@ begin
"0000" & sctr_p when "10",
"00" & fake when others;
-- Channel status
-- State machine
nzs_en_d <= nzs_en when rising_edge(clk40)
err_i <= buf_full or dr_full;
err <= err_i;
ro_en <= not (ctrl_mode or err_i) and ctrl_en_buf;
-- veto <= dr_warn or not ro_en;
enb <= ctrl_en_buf when rising_edge(clk40); -- CDC, synchroniser for ctrl_en_buf
enb_d <= enb when rising_edge(clk40);
process(clk40)
begin
if rising_edge(clk40) then
if rst40 = '1' or enb_d = '0' then
state <= ST_DIS;
else
case state is
when ST_DIS => -- Starting state
if ctrl_mode = '0' then
state <= ST_WAIT;
end if;
when ST_WAIT => -- Wait for sync
if nzs_en = '1' and nzs_en_d = '0' then
state <= ST_RUN;
end if;
when ST_RUN => -- Normal running
if buf_full = '1' or dr_full = '1' then
state <= ST_ERR;
elsif dr_warn = '1' then
state <= ST_VETO;
end if;
when ST_VETO => -- Normal running
if buf_full = '1' or dr_full = '1' then
state <= ST_ERR;
elsif dr_empty = '1' then
state <= ST_RUN;
end if;
when ST_ERR => -- Stuck now, sucker
end case;
end if;
end if;
end process;
err <= '1' when state = ST_ERR else '0';
with state select state_dec <=
"000" when ST_DIS,
"001" when ST_WAIT,
"010" when ST_RUN,
"011" when ST_VETO,
"100" when others;
zs_en_i <= '0' when state = ST_DIS else zs_en;
dr_en_i <= dr_en when state = ST_RUN else '0';
-- Veto counters
-- TBD
-- ZS thresholds
......@@ -222,10 +284,10 @@ begin
cap => cap,
cap_full => cap_full,
zs_thresh => zs_thresh,
zs_en => zs_en,
zs_en => zs_en_i,
buf_full => buf_full,
dr_en => dr_en_i,
keep => keep,
flush => flush,
kack => kack,
q => dr_d,
q_blkend => dr_blkend,
......@@ -244,11 +306,13 @@ begin
clk_r => clk_dr,
q => q,
q_blkend => q_blkend,
empty => q_empty,
empty => dr_empty,
ren => ren,
warn => dr_warn,
full => dr_full
);
q_empty <= dr_empty;
-- Local triggers
......
components/solid/firmware/hdl/sc_chan_buf.vhd
View file @ fd569f95
......@@ -34,8 +34,8 @@ entity sc_chan_buf is
zs_thresh: in std_logic_vector(13 downto 0); -- ZS threshold; clk40 dom
zs_en: in std_logic; -- enable zs buffer; clk40 dom
buf_full: out std_logic; -- buffer err flag; clk40 dom
dr_en: in std_logic;
keep: in std_logic; -- block transfer cmd; clk40 dom
flush: in std_logic; -- block discard cmd; clk40 dom
kack: out std_logic;
q: out std_logic_vector(31 downto 0); -- output to derand; clk40 dom
q_blkend: out std_logic;
......@@ -211,9 +211,9 @@ begin
-- Readout to derand
kack <= keep;
go <= keep or flush;
go <= blkend and dr_en;
kack <= go and keep;
process(clk40)
begin
if rising_edge(clk40) then
......
components/solid/firmware/hdl/sc_channels.vhd
View file @ fd569f95
......@@ -36,8 +36,8 @@ entity sc_channels is
nzs_blks: in std_logic_vector(3 downto 0);
nzs_en: in std_logic;
zs_en: in std_logic;
dr_en: in std_logic;
keep: in std_logic;
flush: in std_logic;
kack: out std_logic_vector(N_CHAN - 1 downto 0);
err: out std_logic;
trig: out sc_trig_array;
......@@ -113,8 +113,8 @@ begin
nzs_blks => nzs_blks,
nzs_en => nzs_en,
zs_en => zs_en,
dr_en => dr_en,
keep => keep,
flush => flush,
kack => kack(i),
err => chan_err(i),
trig => ltrig,
......
components/solid/firmware/hdl/sc_daq.vhd
View file @ fd569f95
......@@ -47,7 +47,7 @@ architecture rtl of sc_daq is
signal clk40_i, rst40_i, clk160, clk280: std_logic;
signal sync_ctrl: std_logic_vector(3 downto 0);
signal sctr: std_logic_vector(47 downto 0);
signal trig_en, nzs_en, zs_en: std_logic;
signal dr_en, nzs_en, zs_en: std_logic;
signal trig_keep, trig_flush: std_logic;
signal trig_kack: std_logic_vector(N_CHAN - 1 downto 0);
signal fake: std_logic_vector(13 downto 0);
......@@ -100,7 +100,7 @@ begin
led => led_out,
sctr => sctr,
chan_sync_ctrl => sync_ctrl,
trig_en => trig_en,
dr_en => dr_en,
nzs_en => nzs_en,
zs_en => zs_en,
rand => rand,
......@@ -161,8 +161,8 @@ begin
nzs_blks => nzs_blks,
nzs_en => nzs_en,
zs_en => zs_en,
dr_en => dr_en,
keep => trig_keep,
flush => trig_flush,
kack => trig_kack,
err => chan_err,
trig => chan_trig,
......@@ -185,11 +185,10 @@ begin
clk40 => clk40_i,
rst40 => rst40_i,
clk160 => clk160,
trig_en => trig_en,
trig_en => dr_en,
zs_en => zs_en,
sctr => sctr,
keep => trig_keep,
flush => trig_flush,
kack => trig_kack,
zs_sel => zs_sel,
trig => chan_trig,
......
components/solid/firmware/hdl/sc_seq.vhd
View file @ fd569f95
......@@ -36,7 +36,6 @@ entity sc_seq is
valid_ext: in std_logic;
ack_ext: out std_logic;
keep: out std_logic;
flush: out std_logic;
err: out std_logic
);
......@@ -197,6 +196,5 @@ begin
end process;
keep <= keep_i;
flush <= not keep_i;
end rtl;
components/solid/firmware/hdl/sc_timing.vhd
View file @ fd569f95
......@@ -33,7 +33,7 @@ entity sc_timing is
led: out std_logic; -- LED flash out
sctr: out std_logic_vector(47 downto 0); -- sample counter
chan_sync_ctrl: out std_logic_vector(3 downto 0); -- Timing signals to channels
trig_en: out std_logic;
dr_en: out std_logic;
nzs_en: out std_logic;
zs_en: out std_logic;
rand: out std_logic_vector(31 downto 0);
......@@ -203,7 +203,7 @@ begin
sctr => sctr_i,
nzs_en => nzs_en,
zs_en => zs_en,
trig_en => trig_en
dr_en => dr_en
);
nzs_blks <= ctrl_nzs_blks;
......
components/solid/firmware/hdl/sc_timing_startup.vhd
View file @ fd569f95
......@@ -22,7 +22,7 @@ entity sc_timing_startup is
sctr: in unsigned(47 downto 0);
nzs_en: out std_logic;
zs_en: out std_logic;
trig_en: out std_logic
dr_en: out std_logic
);
end sc_timing_startup;
......@@ -40,7 +40,7 @@ begin
up <= '0';
nzs_en <= '0';
zs_en <= '0';
trig_en <= '0';
dr_en <= '0';
else
if sync = '1' then
up <= '1';
......@@ -51,7 +51,7 @@ begin
elsif unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = unsigned(nzs_blks) + 1 and sctr(BLK_RADIX - 1 downto 0) = to_unsigned(ZS_DEL - 1, BLK_RADIX) then
zs_en <= '1';
elsif unsigned(sctr(7 + BLK_RADIX downto BLK_RADIX)) = unsigned(nzs_blks) + 1 + unsigned(zs_blks) then
trig_en <= '1';
dr_en <= '1';
end if;
end if;
end if;
......
components/solid/firmware/hdl/sc_trig.vhd
View file @ fd569f95
......@@ -28,7 +28,6 @@ entity sc_trig is
zs_en: in std_logic;
sctr: in std_logic_vector(47 downto 0);
keep: out std_logic;
flush: out std_logic;
kack: in std_logic_vector(N_CHAN - 1 downto 0);
zs_sel: out std_logic_vector(1 downto 0);
trig: in sc_trig_array;
......@@ -249,14 +248,10 @@ begin
valid_ext => d_valid,
ack_ext => d_ack,
keep => keep_i,
flush => flush_i,
err => err
);
-- Channel interface
keep <= keep_i and mark;
flush <= flush_i and mark;
keep <= keep_i;
-- Readout header to ROC
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment