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euro-adc-65m-14b-40cha-gw
Commit dd59b6a7 authored by Dave Newbold's avatar Dave Newbold
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Adding test output

parent f9991f65
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Showing with 16 additions and 8 deletions
boards/pc051b/base_fw/synth/firmware/hdl/top_pc051b.vhd
View file @ dd59b6a7
...@@ -35,8 +35,8 @@ entity top is port( ...@@ -35,8 +35,8 @@ entity top is port(
sync_in: in std_logic; -- IO via timing interface sync_in: in std_logic; -- IO via timing interface
trig_in: in std_logic; trig_in: in std_logic;
trig_out: out std_logic; trig_out: out std_logic;
adc_d_p: in std_logic_vector(63 downto 0); -- ADC serial input data adc_d_p: inout std_logic_vector(63 downto 0); -- ADC serial input data
adc_d_n: in std_logic_vector(63 downto 0) adc_d_n: inout std_logic_vector(63 downto 0)
); );
end top; end top;
......
components/solid/firmware/hdl/sc_chan.vhd
View file @ dd59b6a7
...@@ -31,8 +31,8 @@ entity sc_chan is ...@@ -31,8 +31,8 @@ entity sc_chan is
rst40: in std_logic; rst40: in std_logic;
clk160: in std_logic; clk160: in std_logic;
clk280: in std_logic; clk280: in std_logic;
d_p: in std_logic; d_p: inout std_logic;
d_n: in std_logic; d_n: inout std_logic;
sync_ctrl: in std_logic_vector(3 downto 0); sync_ctrl: in std_logic_vector(3 downto 0);
zs_sel: in std_logic_vector(1 downto 0); zs_sel: in std_logic_vector(1 downto 0);
sctr: in std_logic_vector(47 downto 0); sctr: in std_logic_vector(47 downto 0);
......
components/solid/firmware/hdl/sc_daq.vhd
View file @ dd59b6a7
...@@ -29,8 +29,8 @@ entity sc_daq is ...@@ -29,8 +29,8 @@ entity sc_daq is
led_out: out std_logic; led_out: out std_logic;
chan: in std_logic_vector(7 downto 0); chan: in std_logic_vector(7 downto 0);
chan_err: out std_logic; chan_err: out std_logic;
d_p: in std_logic_vector(N_CHAN - 1 downto 0); d_p: inout std_logic_vector(N_CHAN - 1 downto 0);
d_n: in std_logic_vector(N_CHAN - 1 downto 0); d_n: inout std_logic_vector(N_CHAN - 1 downto 0);
clk125: in std_logic; clk125: in std_logic;
rst125: in std_logic; rst125: in std_logic;
pllclk: in std_logic; pllclk: in std_logic;
......
projects/64ch/firmware/hdl/payload.vhd
View file @ dd59b6a7
...@@ -46,8 +46,8 @@ entity payload is ...@@ -46,8 +46,8 @@ entity payload is
sync_in: in std_logic; sync_in: in std_logic;
trig_in: in std_logic; trig_in: in std_logic;
trig_out: out std_logic; trig_out: out std_logic;
adc_d_p: in std_logic_vector(63 downto 0); adc_d_p: inout std_logic_vector(63 downto 0);
adc_d_n: in std_logic_vector(63 downto 0) adc_d_n: inout std_logic_vector(63 downto 0)
); );
end payload; end payload;
...@@ -183,6 +183,14 @@ begin ...@@ -183,6 +183,14 @@ begin
ib => adc_d_n(i), ib => adc_d_n(i),
o => open o => open
); );
bufo: OBUFTDS
port map(
i => '0',
t => '1',
o => adc_d_p(i),
ob => adc_p_n(i)
);
end generate; end generate;
......
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