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euro-adc-65m-14b-40cha-gw
Commit d915102a authored by Dave Newbold's avatar Dave Newbold
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Adding io bufs to timing board

parent 33fb096b
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projects/timing/firmware/cfg/payload.dep
View file @ d915102a
src payload.vhd
src ipbus_decode_top.vhd
addrtab -t top.xml
src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd
include -c components/pdts pdts_fmc_io.dep
src -c components/pdts pdts_rx_div_mmcm.vhd
src -c components/pdts pdts_synchro.vhd
include master_top.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
#src ipbus_decode_top.vhd
#addrtab -t top.xml
#src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd
src sc_timing_iobufs.vhd
#src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
projects/timing/firmware/hdl/payload.vhd
View file @ d915102a
-- master
--
-- Interface to timing FMC v1 for PDTS master block
--
-- Dave Newbold, February 2017
library IEEE;
......@@ -21,154 +17,92 @@ entity payload is
soft_rst: out std_logic;
userled: out std_logic;
clk125: in std_logic;
fmc_clk_p: in std_logic;
fmc_clk_n: in std_logic;
rec_clk_p: in std_logic;
rec_clk_n: in std_logic;
rec_d_p: in std_logic;
rec_d_n: in std_logic;
clk_out_p: out std_logic;
clk_out_n: out std_logic;
rj45_din_p: in std_logic;
rj45_din_n: in std_logic;
rj45_dout_p: out std_logic;
rj45_dout_n: out std_logic;
sfp_dout_p: out std_logic;
sfp_dout_n: out std_logic;
cdr_lol: in std_logic;
cdr_los: in std_logic;
sfp_los: in std_logic;
sfp_tx_dis: out std_logic;
sfp_flt: in std_logic;
uid_scl: out std_logic;
uid_sda: inout std_logic;
sfp_scl: out std_logic;
sfp_sda: inout std_logic;
pll_scl: out std_logic;
pll_sda: inout std_logic;
pll_rstn: out std_logic;
gpin_0_p: in std_logic;
gpin_0_n: in std_logic;
gpout_0_p: out std_logic;
gpout_0_n: out std_logic;
gpout_1_p: out std_logic;
gpout_1_n: out std_logic
clk_rstn_p: out std_logic;
clk_rstn_n: out std_logic;
clk_o_p: out std_logic;
clk_o_n: out std_logic;
clk_i_p: in std_logic;
clk_i_n: in std_logic;
trig_o_p: out std_logic;
trig_o_n: out std_logic;
trig_i_p: in std_logic;
trig_i_n: in std_logic;
sync_o_p: out std_logic;
sync_o_n: out std_logic;
sync_i_p: in std_logic;
sync_i_n: in std_logic;
trig_sel_p: out std_logic;
trig_sel_n: out std_logic;
sync_sel_p: out std_logic;
sync_sel_n: out std_logic;
scl_p: out std_logic;
scl_n: out std_logic;
sda_o_p: out std_logic;
sda_o_n: out std_logic;
sda_i_p: in std_logic;
sda_i_n: in std_logic;
busy_o_p: out std_logic;
busy_o_n: out std_logic;
busy_i_p: in std_logic_vector(9 downto 0);
busy_i_n: in std_logic_vector(9 downto 0)
);
end payload;
architecture rtl of payload is
signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
signal fmc_clk, rec_clk, rec_d, sfp_dout, rst_io, rsti, clk, stb, rst, locked: std_logic;
-- signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
-- signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
attribute IOB: string;
attribute IOB of sfp_dout: signal is "TRUE";
-- attribute IOB: string;
-- attribute IOB of sfp_dout: signal is "TRUE";
begin
-- ipbus address decode
fabric: entity work.ipbus_fabric_sel
generic map(
NSLV => N_SLAVES,
SEL_WIDTH => IPBUS_SEL_WIDTH
)
port map(
ipb_in => ipb_in,
ipb_out => ipb_out,
sel => ipbus_sel_top(ipb_in.ipb_addr),
ipb_to_slaves => ipbw,
ipb_from_slaves => ipbr
);
-- IO
io: entity work.pdts_fmc_io
port map(
ipb_clk => ipb_clk,
ipb_rst => ipb_rst,
ipb_in => ipbw(N_SLV_IO),
ipb_out => ipbr(N_SLV_IO),
soft_rst => soft_rst,
nuke => nuke,
rst => rst_io,
locked => locked,
cdr_lol => cdr_lol,
cdr_los => cdr_los,
sfp_los => sfp_los,
sfp_tx_dis => sfp_tx_dis,
sfp_flt => sfp_flt,
userled => userled,
fmc_clk_p => fmc_clk_p,
fmc_clk_n => fmc_clk_n,
fmc_clk => fmc_clk,
rec_clk_p => rec_clk_p,
rec_clk_n => rec_clk_n,
rec_clk => rec_clk,
rec_d_p => rec_d_p,
rec_d_n => rec_d_n,
rec_d => rec_d,
clk_out_p => clk_out_p,
clk_out_n => clk_out_n,
rj45_din_p => rj45_din_p,
rj45_din_n => rj45_din_n,
rj45_dout_p => rj45_dout_p,
rj45_dout_n => rj45_dout_n,
sfp_dout => sfp_dout,
sfp_dout_p => sfp_dout_p,
sfp_dout_n => sfp_dout_n,
uid_scl => uid_scl,
uid_sda => uid_sda,
sfp_scl => sfp_scl,
sfp_sda => sfp_sda,
pll_scl => pll_scl,
pll_sda => pll_sda,
pll_rstn => pll_rstn,
gpin_0_p => gpin_0_p,
gpin_0_n => gpin_0_n,
gpout_0_p => gpout_0_p,
gpout_0_n => gpout_0_n,
gpout_1_p => gpout_1_p,
gpout_1_n => gpout_1_n
);
-- Clock divider
clkgen: entity work.pdts_rx_div_mmcm
port map(
sclk => fmc_clk,
clk => clk,
phase_rst => rst_io,
phase_locked => locked
);
rsti <= rst_io or not locked;
synchro: entity work.pdts_synchro
generic map(
N => 1
)
port map(
clk => ipb_clk,
clks => clk,
d(0) => rsti,
q(0) => rst
);
-- master block
master: entity work.master
bufs: entity work.sc_timing_iobufs
port map(
ipb_clk => ipb_clk,
ipb_rst => ipb_rst,
ipb_in => ipbw(N_SLV_MASTER),
ipb_out => ipbr(N_SLV_MASTER),
mclk => fmc_clk,
clk => clk,
rst => rst,
q => sfp_dout
clk_rstn => '1',
clk_rstn_p => clk_rstn_p,
clk_rstn_n => clk_rstn_n,
clk => '0',
clk_o_p => clk_o_p,
clk_o_n => clk_o_n,
clk_i => open,
clk_i_p => clk_i_p,
clk_i_n => clk_i_n,
trig_o => '0',
trig_o_p => trig_o_p,
trig_o_n => trig_o_n,
trig_i => open,
trig_i_p => trig_i_p,
trig_i_n => trig_i_n,
sync_o => '0',
sync_o_p => sync_o_p,
sync_o_n => sync_o_n,
sync_i => open,
sync_i_p => sync_i_p,
sync_i_n => sync_i_n,
trig_sel => '0',
trig_sel_p => trig_sel_p,
trig_sel_n => trig_sel_n,
sync_sel => '0',
sync_sel_p => sync_sel_p,
sync_sel_n => sync_sel_n,
scl => '0',
scl_p => scl_p,
scl_n => scl_n,
sda_o => '0',
sda_o_p => sda_o_p,
sda_o_n => sda_o_n,
sda_i => open,
sda_i_p => sda_i_p,
sda_i_n => sda_i_n,
busy_o => '0',
busy_o_p => busy_o_p,
busy_o_n => busy_o_n,
busy_i => open
busy_i_p => busy_i_p,
busy_i_n => busy_i_n
);
end rtl;
projects/timing/firmware/hdl/sc_timing_iobufs.vhd 0 → 100644
View file @ d915102a
-- sc_timing_iobufs
--
-- The IO buffers for the timing board. Dull.
--
-- Dave Newbold, July 2017
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library unisim;
use unisim.VComponents.all;
entity sc_timing_iobufs is
port(
clk_rstn: in std_logic;
clk_rstn_p: out std_logic;
clk_rstn_n: out std_logic;
clk: in std_logic;
clk_o_p: out std_logic;
clk_o_n: out std_logic;
clk_i: out std_logic;
clk_i_p: in std_logic;
clk_i_n: in std_logic;
trig_o: in std_logic;
trig_o_p: out std_logic;
trig_o_n: out std_logic;
trig_i: out std_logic;
trig_i_p: in std_logic;
trig_i_n: in std_logic;
sync_o: in std_logic;
sync_o_p: out std_logic;
sync_o_n: out std_logic;
sync_i: in std_logic;
sync_i_p: in std_logic;
sync_i_n: in std_logic;
trig_sel: in std_logic;
trig_sel_p: out std_logic;
trig_sel_n: out std_logic;
sync_sel: in std_logic;
sync_sel_p: out std_logic;
sync_sel_n: out std_logic;
scl: in std_logic;
scl_p: out std_logic;
scl_n: out std_logic;
sda_o: in std_logic;
sda_o_p: out std_logic;
sda_o_n: out std_logic;
sda_i: out std_logic;
sda_i_p: in std_logic;
sda_i_n: in std_logic;
busy_o: in std_logic;
busy_o_p: out std_logic;
busy_o_n: out std_logic;
busy_i: out std_logic;
busy_i_p: in std_logic_vector(9 downto 0);
busy_i_n: in std_logic_vector(9 downto 0)
);
end sc_timing_iobufs;
architecture rtl of sc_timing_iobufs is
signal clk_o, clk_i_u: std_logic;
begin
obuf_clk_rstn: OBUFDS
port map(
i => clk_rstn,
o => clk_rstn_p,
ob => clk_rstn_n
);
oddr_clkout: ODDR -- Feedback clock, not through MMCM
port map(
q => clk_o,
c => clk,
ce => '1',
d1 => '0',
d2 => '1',
r => '0',
s => '0'
);
obuf_clk_rstn: OBUFDS
port map(
i => clk_o,
o => clk_o_p,
ob => clk_o_n
);
ibufg_in: IBUFGDS
port map(
i => clk_i_p,
ib => clk_i_n,
o => clk_i_u
);
bufg_in: BUFG
port map(
i => clk_i_u,
o => clk_i
);
obuf_trig_o: OBUFDS
port map(
i => trig_o,
o => trig_o_p,
ob => trig_o_n
);
ibuf_trig_i: IBUFDS
port map(
i => trig_i_p,
ib => trig_i_n,
o => trig_i
);
obuf_sync_o: OBUFDS
port map(
i => sync_o,
o => sync_o_p,
ob => sync_o_n
);
ibuf_sync_i: IBUFDS
port map(
i => sync_i_p,
ib => sync_i_n,
o => sync_i
);
obuf_trig_sel: OBUFDS
port map(
i => trig_sel,
o => trig_sel_p,
ob => trig_sel_n
);
obuf_sync_sel: OBUFDS
port map(
i => sync_sel,
o => sync_sel_p,
ob => sync_sel_n
);
obuf_scl: OBUFDS
port map(
i => scl,
o => scl_p,
ob => scl_n
);
obuf_sda_o: OBUFDS
port map(
i => sda_o,
o => sda_o_p,
ob => sda_o_n
);
ibuf_sda_i: IBUFDS
port map(
i => sda_i_p,
ib => sda_i_n,
o => sda_i
);
obuf_busy_o: OBUFDS
port map(
i => busy_o,
o => busy_o_p,
ob => busy_o_n
);
busy_i_gen: for i in 9 downto 0 generate
ibuf_sda_i: IBUFDS
port map(
i => busy_i_p(i),
ib => busy_i_n(i),
o => busy_i(i)
);
end generate;
end rtl;
projects/timing/firmware/hdl/top_enclustra_ax3_pm3.vhd
View file @ d915102a
......@@ -22,38 +22,34 @@ entity top is port(
rgmii_rx_ctl: in std_logic;
rgmii_rxc: in std_logic;
phy_rstn: out std_logic;
fmc_clk_p: in std_logic;
fmc_clk_n: in std_logic;
rec_clk_p: in std_logic;
rec_clk_n: in std_logic;
rec_d_p: in std_logic;
rec_d_n: in std_logic;
clk_out_p: out std_logic;
clk_out_n: out std_logic;
rj45_din_p: in std_logic;
rj45_din_n: in std_logic;
rj45_dout_p: out std_logic;
rj45_dout_n: out std_logic;
sfp_dout_p: out std_logic;
sfp_dout_n: out std_logic;
pll_rstn: out std_logic;
cdr_lol: in std_logic;
cdr_los: in std_logic;
sfp_los: in std_logic;
sfp_tx_dis: out std_logic;
sfp_flt: in std_logic;
uid_scl: out std_logic;
uid_sda: inout std_logic;
sfp_scl: out std_logic;
sfp_sda: inout std_logic;
pll_scl: out std_logic;
pll_sda: inout std_logic;
gpin_0_p: in std_logic;
gpin_0_n: in std_logic;
gpout_0_p: out std_logic;
gpout_0_n: out std_logic;
gpout_1_p: out std_logic;
gpout_1_n: out std_logic
clk_rstn_p: out std_logic;
clk_rstn_n: out std_logic;
clk_o_p: out std_logic;
clk_o_n: out std_logic;
clk_i_p: in std_logic;
clk_i_n: in std_logic;
trig_o_p: out std_logic;
trig_o_n: out std_logic;
trig_i_p: in std_logic;
trig_i_n: in std_logic;
sync_o_p: out std_logic;
sync_o_n: out std_logic;
sync_i_p: in std_logic;
sync_i_n: in std_logic;
trig_sel_p: out std_logic;
trig_sel_n: out std_logic;
sync_sel_p: out std_logic;
sync_sel_n: out std_logic;
scl_p: out std_logic;
scl_n: out std_logic;
sda_o_p: out std_logic;
sda_o_n: out std_logic;
sda_i_p: in std_logic;
sda_i_n: in std_logic;
busy_o_p: out std_logic;
busy_o_n: out std_logic;
busy_i_p: in std_logic_vector(9 downto 0);
busy_i_n: in std_logic_vector(9 downto 0)
);
end top;
......@@ -112,38 +108,34 @@ begin
soft_rst => soft_rst,
userled => userled,
clk125 => clk125,
fmc_clk_p => fmc_clk_p,
fmc_clk_n => fmc_clk_n,
rec_clk_p => rec_clk_p,
rec_clk_n => rec_clk_n,
rec_d_p => rec_d_p,
rec_d_n => rec_d_n,
clk_out_p => clk_out_p,
clk_out_n => clk_out_n,
rj45_din_p => rj45_din_p,
rj45_din_n => rj45_din_n,
rj45_dout_p => rj45_dout_p,
rj45_dout_n => rj45_dout_n,
sfp_dout_p => sfp_dout_p,
sfp_dout_n => sfp_dout_n,
cdr_lol => cdr_lol,
cdr_los => cdr_los,
sfp_los => sfp_los,
sfp_tx_dis => sfp_tx_dis,
sfp_flt => sfp_flt,
uid_scl => uid_scl,
uid_sda => uid_sda,
sfp_scl => sfp_scl,
sfp_sda => sfp_sda,
pll_scl => pll_scl,
pll_sda => pll_sda,
pll_rstn => pll_rstn,
gpin_0_p => gpin_0_p,
gpin_0_n => gpin_0_n,
gpout_0_p => gpout_0_p,
gpout_0_n => gpout_0_n,
gpout_1_p => gpout_1_p,
gpout_1_n => gpout_1_n
clk_rstn_p => clk_rstn_p,
clk_rstn_n => clk_rstn_n,
clk_o_p => clk_o_p,
clk_o_n => clk_o_n,
clk_i_p => clk_i_p,
clk_i_n => clk_i_n,
trig_o_p => trig_o_p,
trig_o_n => trig_o_n,
trig_i_p => trig_i_p,
trig_i_n => trig_i_n,
sync_o_p => sync_o_p,
sync_o_n => sync_o_n,
sync_i_p => sync_i_p,
sync_i_n => sync_i_n,
trig_sel_p => trig_sel_p,
trig_sel_n => trig_sel_n,
sync_sel_p => sync_sel_p,
sync_sel_n => sync_sel_n,
scl_p => scl_p,
scl_n => scl_n,
sda_o_p => sda_o_p,
sda_o_n => sda_o_n,
sda_i_p => sda_i_p,
sda_i_n => sda_i_n,
busy_o_p => busy_o_p,
busy_o_n => busy_o_n,
busy_i_p => busy_i_p,
busy_i_n => busy_i_n
);
end rtl;
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