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euro-adc-65m-14b-40cha
euro-adc-65m-14b-40cha-gw
Commits
d80cb1c6
Commit
d80cb1c6
authored
Jun 07, 2017
by
Dave Newbold
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Addrtab update
parent
83a4db91
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3 changed files
with
31 additions
and
25 deletions
+31
-25
ipbus_decode_sc_trig.vhd
components/solid/firmware/hdl/ipbus_decode_sc_trig.vhd
+14
-11
ipbus_decode_top.vhd
projects/8ch/firmware/hdl/ipbus_decode_top.vhd
+12
-9
ipbus_decode_top_sim.vhd
projects/8ch/firmware/hdl/ipbus_decode_top_sim.vhd
+5
-5
No files found.
components/solid/firmware/hdl/ipbus_decode_sc_trig.vhd
View file @
d80cb1c6
...
...
@@ -17,12 +17,13 @@ package ipbus_decode_sc_trig is
subtype
ipbus_sel_t
is
std_logic_vector
(
IPBUS_SEL_WIDTH
-
1
downto
0
);
function
ipbus_sel_sc_trig
(
addr
:
in
std_logic_vector
(
31
downto
0
))
return
ipbus_sel_t
;
-- START automatically generated VHDL the
Fri Mar 17 13:58:05
2017
-- START automatically generated VHDL the
Wed Jun 7 10:07:49
2017
constant
N_SLV_CSR
:
integer
:
=
0
;
constant
N_SLV_LOC
:
integer
:
=
1
;
constant
N_SLV_DTMON
:
integer
:
=
2
;
constant
N_SLV_SEQ
:
integer
:
=
3
;
constant
N_SLAVES
:
integer
:
=
4
;
constant
N_SLV_MASKS
:
integer
:
=
4
;
constant
N_SLAVES
:
integer
:
=
5
;
-- END automatically generated VHDL
...
...
@@ -34,15 +35,17 @@ package body ipbus_decode_sc_trig is
variable
sel
:
ipbus_sel_t
;
begin
-- START automatically generated VHDL the Fri Mar 17 13:58:05 2017
if
std_match
(
addr
,
"----------------------------00--"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_CSR
,
IPBUS_SEL_WIDTH
));
-- csr / base 0x00000000 / mask 0x0000000c
elsif
std_match
(
addr
,
"----------------------------010-"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_LOC
,
IPBUS_SEL_WIDTH
));
-- loc / base 0x00000004 / mask 0x0000000e
elsif
std_match
(
addr
,
"----------------------------011-"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_DTMON
,
IPBUS_SEL_WIDTH
));
-- dtmon / base 0x00000006 / mask 0x0000000e
elsif
std_match
(
addr
,
"----------------------------1---"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_SEQ
,
IPBUS_SEL_WIDTH
));
-- seq / base 0x00000008 / mask 0x00000008
-- START automatically generated VHDL the Wed Jun 7 10:07:49 2017
if
std_match
(
addr
,
"---------------------------000--"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_CSR
,
IPBUS_SEL_WIDTH
));
-- csr / base 0x00000000 / mask 0x0000001c
elsif
std_match
(
addr
,
"---------------------------0010-"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_LOC
,
IPBUS_SEL_WIDTH
));
-- loc / base 0x00000004 / mask 0x0000001e
elsif
std_match
(
addr
,
"---------------------------0011-"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_DTMON
,
IPBUS_SEL_WIDTH
));
-- dtmon / base 0x00000006 / mask 0x0000001e
elsif
std_match
(
addr
,
"---------------------------01---"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_SEQ
,
IPBUS_SEL_WIDTH
));
-- seq / base 0x00000008 / mask 0x00000018
elsif
std_match
(
addr
,
"---------------------------1----"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_MASKS
,
IPBUS_SEL_WIDTH
));
-- masks / base 0x00000010 / mask 0x00000010
-- END automatically generated VHDL
else
...
...
projects/8ch/firmware/hdl/ipbus_decode_top.vhd
View file @
d80cb1c6
...
...
@@ -17,15 +17,16 @@ package ipbus_decode_top is
subtype
ipbus_sel_t
is
std_logic_vector
(
IPBUS_SEL_WIDTH
-
1
downto
0
);
function
ipbus_sel_top
(
addr
:
in
std_logic_vector
(
31
downto
0
))
return
ipbus_sel_t
;
-- START automatically generated VHDL the
Fri Mar 17 13:58:05
2017
-- START automatically generated VHDL the
Wed Jun 7 21:43:12
2017
constant
N_SLV_CSR
:
integer
:
=
0
;
constant
N_SLV_CHAN
:
integer
:
=
1
;
constant
N_SLV_IO
:
integer
:
=
2
;
constant
N_SLV_TIMING
:
integer
:
=
3
;
constant
N_SLV_TLINK
:
integer
:
=
4
;
constant
N_SLV_TRIG
:
integer
:
=
5
;
constant
N_SLV_ROC
:
integer
:
=
6
;
constant
N_SLAVES
:
integer
:
=
7
;
constant
N_SLV_FAKE
:
integer
:
=
4
;
constant
N_SLV_TLINK
:
integer
:
=
5
;
constant
N_SLV_TRIG
:
integer
:
=
6
;
constant
N_SLV_ROC
:
integer
:
=
7
;
constant
N_SLAVES
:
integer
:
=
8
;
-- END automatically generated VHDL
...
...
@@ -37,7 +38,7 @@ package body ipbus_decode_top is
variable
sel
:
ipbus_sel_t
;
begin
-- START automatically generated VHDL the
Fri Mar 17 13:58:05
2017
-- START automatically generated VHDL the
Wed Jun 7 21:43:12
2017
if
std_match
(
addr
,
"------------------------0000----"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_CSR
,
IPBUS_SEL_WIDTH
));
-- csr / base 0x00000000 / mask 0x000000f0
elsif
std_match
(
addr
,
"------------------------0001----"
)
then
...
...
@@ -47,11 +48,13 @@ package body ipbus_decode_top is
elsif
std_match
(
addr
,
"------------------------0100----"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_TIMING
,
IPBUS_SEL_WIDTH
));
-- timing / base 0x00000040 / mask 0x000000f0
elsif
std_match
(
addr
,
"------------------------0101----"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_
TLINK
,
IPBUS_SEL_WIDTH
));
-- tlink
/ base 0x00000050 / mask 0x000000f0
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_
FAKE
,
IPBUS_SEL_WIDTH
));
-- fake
/ base 0x00000050 / mask 0x000000f0
elsif
std_match
(
addr
,
"------------------------0110----"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_T
RIG
,
IPBUS_SEL_WIDTH
));
-- trig
/ base 0x00000060 / mask 0x000000f0
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_T
LINK
,
IPBUS_SEL_WIDTH
));
-- tlink
/ base 0x00000060 / mask 0x000000f0
elsif
std_match
(
addr
,
"------------------------100-----"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_ROC
,
IPBUS_SEL_WIDTH
));
-- roc / base 0x00000080 / mask 0x000000e0
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_TRIG
,
IPBUS_SEL_WIDTH
));
-- trig / base 0x00000080 / mask 0x000000e0
elsif
std_match
(
addr
,
"------------------------101-----"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_ROC
,
IPBUS_SEL_WIDTH
));
-- roc / base 0x000000a0 / mask 0x000000e0
-- END automatically generated VHDL
else
...
...
projects/8ch/firmware/hdl/ipbus_decode_top_sim.vhd
View file @
d80cb1c6
...
...
@@ -17,7 +17,7 @@ package ipbus_decode_top_sim is
subtype
ipbus_sel_t
is
std_logic_vector
(
IPBUS_SEL_WIDTH
-
1
downto
0
);
function
ipbus_sel_top_sim
(
addr
:
in
std_logic_vector
(
31
downto
0
))
return
ipbus_sel_t
;
-- START automatically generated VHDL the
Tue Jun 6 13:22:51
2017
-- START automatically generated VHDL the
Wed Jun 7 10:07:49
2017
constant
N_SLV_CSR
:
integer
:
=
0
;
constant
N_SLV_CHAN
:
integer
:
=
1
;
constant
N_SLV_TIMING
:
integer
:
=
2
;
...
...
@@ -37,7 +37,7 @@ package body ipbus_decode_top_sim is
variable
sel
:
ipbus_sel_t
;
begin
-- START automatically generated VHDL the
Tue Jun 6 13:22:51
2017
-- START automatically generated VHDL the
Wed Jun 7 10:07:49
2017
if
std_match
(
addr
,
"------------------------0000----"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_CSR
,
IPBUS_SEL_WIDTH
));
-- csr / base 0x00000000 / mask 0x000000f0
elsif
std_match
(
addr
,
"------------------------0001----"
)
then
...
...
@@ -48,10 +48,10 @@ package body ipbus_decode_top_sim is
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_FAKE
,
IPBUS_SEL_WIDTH
));
-- fake / base 0x00000050 / mask 0x000000f0
elsif
std_match
(
addr
,
"------------------------0110----"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_TLINK
,
IPBUS_SEL_WIDTH
));
-- tlink / base 0x00000060 / mask 0x000000f0
elsif
std_match
(
addr
,
"------------------------0111----"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_TRIG
,
IPBUS_SEL_WIDTH
));
-- trig / base 0x00000070 / mask 0x000000f0
elsif
std_match
(
addr
,
"------------------------100-----"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_ROC
,
IPBUS_SEL_WIDTH
));
-- roc / base 0x00000080 / mask 0x000000e0
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_TRIG
,
IPBUS_SEL_WIDTH
));
-- trig / base 0x00000080 / mask 0x000000e0
elsif
std_match
(
addr
,
"------------------------101-----"
)
then
sel
:
=
ipbus_sel_t
(
to_unsigned
(
N_SLV_ROC
,
IPBUS_SEL_WIDTH
));
-- roc / base 0x000000a0 / mask 0x000000e0
-- END automatically generated VHDL
else
...
...
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