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euro-adc-65m-14b-40cha-gw
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eurocard
euro-adc-65m-14b-40cha
euro-adc-65m-14b-40cha-gw
Commits
d5ed0949
Commit
d5ed0949
authored
Jul 14, 2017
by
Dave Newbold
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Altering trigger dist logic
parent
c59d7782
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payload.vhd
projects/timing/firmware/hdl/payload.vhd
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projects/timing/firmware/hdl/payload.vhd
View file @
d5ed0949
...
...
@@ -162,7 +162,7 @@ begin
sync_out_ds
<=
ctrl_en_sync
and
not
or_reduce
(
std_logic_vector
(
ctr
))
when
falling_edge
(
clki
);
-- Sync out downstream
trig_i
<=
trig_in_ds
when
rising_edge
(
clki
);
-- Should be IOB reg
trig_out_ds
<=
or_reduce
(
trig_i
and
ctrl_trig_in_mask
)
and
ctrl_en_trig_out
when
falling_edge
(
clki
);
-- Trig out downstream
trig_out_us
<=
or_reduce
(
trig_i
and
ctrl_trig_in_mask
)
when
falling_edge
(
clki
);
-- Trig out upstream
trig_out_us
<=
or_reduce
(
trig_i
and
ctrl_trig_in_mask
)
and
ctrl_en_trig_out
when
falling_edge
(
clki
);
-- Trig out upstream
-- Cable IO
...
...
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