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euro-adc-65m-14b-40cha
euro-adc-65m-14b-40cha-gw
Commits
bb42abe9
Commit
bb42abe9
authored
May 02, 2018
by
Dave Newbold
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Adding empty block suppression
parent
e18cfc17
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3 changed files
with
6 additions
and
2 deletions
+6
-2
sc_chan.xml
components/solid/addr_table/sc_chan.xml
+1
-0
sc_chan.vhd
components/solid/firmware/hdl/sc_chan.vhd
+3
-1
sc_chan_buf.vhd
components/solid/firmware/hdl/sc_chan_buf.vhd
+2
-1
No files found.
components/solid/addr_table/sc_chan.xml
View file @
bb42abe9
...
...
@@ -6,6 +6,7 @@
<node
id=
"invert"
mask=
"0x4"
/>
<node
id=
"swap"
mask=
"0x8"
/>
<node
id=
"mode"
mask=
"0x10"
/>
<node
id=
"suppress"
mask=
"0x20"
/>
<node
id=
"src"
mask=
"0xc0"
/>
</node>
<node
id=
"stat"
address=
"0x1"
>
...
...
components/solid/firmware/hdl/sc_chan.vhd
View file @
bb42abe9
...
...
@@ -64,7 +64,7 @@ architecture rtl of sc_chan is
signal
slip_l
,
slip_h
,
cap
,
inc
:
std_logic
;
signal
act_slip
:
unsigned
(
7
downto
0
);
signal
cntout
:
std_logic_vector
(
4
downto
0
);
signal
ctrl_en_sync
,
ctrl_en_buf
,
ctrl_invert
,
ctrl_swap
:
std_logic
;
signal
ctrl_en_sync
,
ctrl_en_buf
,
ctrl_invert
,
ctrl_swap
,
ctrl_suppress
:
std_logic
;
signal
ctrl_mode
:
std_logic
;
signal
ctrl_src
:
std_logic_vector
(
1
downto
0
);
signal
cap_full
,
buf_full
,
dr_full
,
dr_warn
:
std_logic
;
...
...
@@ -120,6 +120,7 @@ begin
ctrl_invert
<=
ctrl
(
0
)(
2
);
ctrl_swap
<=
ctrl
(
0
)(
3
);
ctrl_mode
<=
ctrl
(
0
)(
4
);
ctrl_suppress
<=
ctrl
(
0
)(
5
);
ctrl_src
<=
ctrl
(
0
)(
7
downto
6
);
slip_l
<=
sync_ctrl
(
0
)
and
ctrl_en_sync
;
-- CDC
...
...
@@ -287,6 +288,7 @@ begin
zs_en
=>
zs_en_i
,
buf_full
=>
buf_full
,
dr_en
=>
dr_en_i
,
suppress
=>
ctrl_suppress
,
keep
=>
keep
,
kack
=>
kack
,
q
=>
dr_d
,
...
...
components/solid/firmware/hdl/sc_chan_buf.vhd
View file @
bb42abe9
...
...
@@ -35,6 +35,7 @@ entity sc_chan_buf is
zs_en
:
in
std_logic
;
-- enable zs buffer; clk40 dom
buf_full
:
out
std_logic
;
-- buffer err flag; clk40 dom
dr_en
:
in
std_logic
;
suppress
:
in
std_logic
;
keep
:
in
std_logic
;
-- block transfer cmd; clk40 dom
kack
:
out
std_logic
;
q
:
out
std_logic_vector
(
31
downto
0
);
-- output to derand; clk40 dom
...
...
@@ -212,7 +213,7 @@ begin
-- Readout to derand
go
<=
blkend
and
dr_en
;
kack
<=
go
and
keep
;
kack
<=
go
and
keep
and
not
(
q_zs_b
(
15
)
and
q_zs_b
(
14
)
and
suppress
)
;
process
(
clk40
)
begin
...
...
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