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euro-adc-65m-14b-40cha-gw
Commit b1ab5b5e authored by Dave Newbold's avatar Dave Newbold
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Re-arranging trigger generators

parent d55d7c9a
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Showing with 154 additions and 97 deletions
components/solid/addr_table/sc_trig.xml
View file @ b1ab5b5e
......@@ -9,16 +9,12 @@
<node id="rveto" mask="0x2"/>
</node>
</node>
<node id="loc" address="0x4" description="local trigger generator" fwinfo="endpoint;width=0">
<node id="trig_en" mask="0xff"/>
<node id="trig_force" mask="0x100"/>
<node id="rnd_mode" mask="0x30000"/>
<node id="rnd_div" mask="0xfc0000"/>
<node id="loc_mask" address="0x4" description="local trigger generator" fwinfo="endpoint;width=0">
</node>
<node id="dtmon" address="0x6" description="deadtime monitor buffer" fwinfo="endpoint;width=1">
<node id="addr" address="0x0"/>
<node id="data" address="0x1" mode="port"/>
</node>
<node id="seq" address="0x8" module="file://sc_seq.xml"/>
<node id="masks" address="0x10" mode="block" size="0x10" description="channel trigger masks" fwinfo="endpoint;width=4"/>
<node id="chan_mask" address="0x10" mode="block" size="0x10" description="channel trigger masks" fwinfo="endpoint;width=4"/>
</node>
components/solid/firmware/cfg/sc_trig.dep
View file @ b1ab5b5e
src sc_trig.vhd sc_local_trig.vhd sc_trig_ro_block.vhd sc_deadtime_mon.vhd
src sc_trig_gen_random.vhd sc_trig_gen_or.vhd
src sc_trig_gen.vhd sc_trig_gen_or.vhd
include sc_seq.dep
src ipbus_decode_sc_trig.vhd
addrtab -t sc_trig.xml
......
components/solid/firmware/hdl/sc_chan_trig.vhd
View file @ b1ab5b5e
......@@ -55,16 +55,13 @@ begin
);
dd <= d when rising_edge(clk40); -- pipeline register
trg0: entity work.sc_ctrig_thresh -- direct threshold trigger, delay = 1
generic map(
VAL_WIDTH => VAL_WIDTH,
DELAY => 2
VAL_WIDTH => VAL_WIDTH
)
port map(
clk => clk40,
rst => rst40,
clr => mark,
d => dd,
threshold => ctrl(0)(VAL_WIDTH - 1 downto 0),
trig => trig_i(0)
......@@ -78,7 +75,6 @@ begin
clk => clk40,
rst => rst40,
clr => mark,
en => en,
d => dd,
cthresh => ctrl(1)(24 downto 16),
wsize => ctrl(1)(31 downto 28),
......@@ -93,7 +89,6 @@ begin
port map(
clk => clk40,
rst => rst40,
clr => mark,
en => en,
d => dd,
cthresh => ctrl(2)(24 downto 16),
......
components/solid/firmware/hdl/sc_ctrig_npeaks.vhd
View file @ b1ab5b5e
......@@ -54,13 +54,10 @@ begin
thresh: entity work.sc_ctrig_thresh
generic map(
VAL_WIDTH => cthresh'length,
DELAY => 3
VAL_WIDTH => cthresh'length
)
port map(
clk => clk,
rst => rsti,
clr => clr,
d => count,
threshold => cthresh,
trig => trig
......
components/solid/firmware/hdl/sc_ctrig_thresh.vhd
View file @ b1ab5b5e
......@@ -10,13 +10,10 @@ use ieee.numeric_std.all;
entity sc_ctrig_thresh is
generic(
VAL_WIDTH: natural;
DELAY: positive := 1
VAL_WIDTH: natural
);
port(
clk: in std_logic;
rst: in std_logic;
clr: in std_logic;
d: in std_logic_vector(VAL_WIDTH - 1 downto 0);
threshold: in std_logic_vector(VAL_WIDTH - 1 downto 0);
trig: out std_logic
......@@ -25,24 +22,12 @@ entity sc_ctrig_thresh is
end sc_ctrig_thresh;
architecture rtl of sc_ctrig_thresh is
signal cdel: std_logic_vector(DELAY - 1 downto 0);
begin
cdel <= cdel(DELAY - 2 downto 0) & clr when rising_edge(clk);
signal t: std_logic;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
trig <= '0';
elsif unsigned(d) > unsigned(threshold) then
trig <= '1';
elsif cdel(DELAY - 1) = '1' then
trig <= '0';
end if;
end if;
end process;
begin
t <= '1' when unsigned(d) > unsigned(threshold) else '0';
trig <= t when rising_edge(clk);
end rtl;
components/solid/firmware/hdl/sc_ctrig_tot.vhd
View file @ b1ab5b5e
......@@ -51,13 +51,10 @@ begin
thresh: entity work.sc_ctrig_thresh
generic map(
VAL_WIDTH => cthresh'length,
DELAY => 2
VAL_WIDTH => cthresh'length
)
port map(
clk => clk,
rst => rsti,
clr => clr,
d => count,
threshold => cthresh,
trig => trig
......
components/solid/firmware/hdl/sc_daq.vhd
View file @ b1ab5b5e
......@@ -26,6 +26,7 @@ entity sc_daq is
sync_in: in std_logic;
sync_out: out std_logic;
trig_in: in std_logic;
trig_out: out std_logic;
chan: in std_logic_vector(7 downto 0);
chan_err: out std_logic;
d_p: in std_logic_vector(N_CHAN - 1 downto 0);
......@@ -47,7 +48,7 @@ architecture rtl of sc_daq is
signal trig_en, nzs_en, zs_en: std_logic;
signal trig_keep, trig_flush, trig_veto: std_logic_vector(N_CHAN - 1 downto 0);
signal fake: std_logic_vector(13 downto 0);
signal force_trig: std_logic;
signal force_trig, thresh_hit: std_logic;
signal zs_sel: std_logic_vector(1 downto 0);
signal chan_trig: sc_trig_array;
signal link_d, link_q: std_logic_vector(15 downto 0);
......@@ -130,8 +131,10 @@ begin
rst40 => rst40_i,
rand => rand,
sctr => sctr,
trig => force_trig,
trig_in => trig_in
force => force_trig,
hit => thresh_hit,
trig_in => trig_in,
trig_out => trig_out
);
-- Data channels
......@@ -189,6 +192,7 @@ begin
zs_sel => zs_sel,
trig => chan_trig,
force => force_trig,
thresh_hit => thresh_hit,
ro_d => trig_d,
ro_blkend => trig_blkend,
ro_we => trig_we,
......
components/solid/firmware/hdl/sc_local_trig.vhd
View file @ b1ab5b5e
......@@ -33,6 +33,8 @@ entity sc_local_trig is
trig_q: out std_logic_vector(15 downto 0);
trig_valid: out std_logic;
trig_ack: in std_logic;
force: in std_logic;
thresh_hit: out std_logic;
ro_q: out std_logic_vector(31 downto 0);
ro_valid: out std_logic;
ro_blkend: out std_logic;
......@@ -46,11 +48,7 @@ end sc_local_trig;
architecture rtl of sc_local_trig is
signal ctrl: ipb_reg_v(0 downto 0);
signal stb: std_logic_vector(0 downto 0);
signal ctrl_trig_en: std_logic_vector(7 downto 0);
signal ctrl_rnd_mode: std_logic_vector(1 downto 0);
signal ctrl_trig_force: std_logic;
signal ctrl_rnd_div: std_logic_vector(5 downto 0);
signal ctrl_trig_en: std_logic_vector(N_TRG - 1 downto 0);
signal tv, te, ta, tc: std_logic_vector(N_TRG - 1 downto 0);
signal s: integer range N_TRG - 1 downto 0;
signal ch: integer range 2 ** ro_ctr'length - 1 downto 0;
......@@ -63,48 +61,44 @@ begin
-- Control register
csr: entity work.ipbus_syncreg_v
csr: entity work.ipbus_reg_v
generic map(
N_CTRL => 1,
N_STAT => 0
N_REG => 1
)
port map(
clk => clk,
rst => rst,
ipb_in => ipb_in,
ipb_out => ipb_out,
slv_clk => clk40,
reset => rst,
ipbus_in => ipb_in,
ipbus_out => ipb_out,
q => ctrl,
stb => stb
qmask(0) => (N_TRIG - 1 downto 0 => '1', others => '0')
);
ctrl_trig_en <= ctrl(0)(7 downto 0);
ctrl_trig_force <= ctrl(0)(8);
ctrl_rnd_mode <= ctrl(0)(17 downto 16);
ctrl_rnd_div <= ctrl(0)(23 downto 18);
ctrl_trig_en <= ctrl(0)(N_TRG - 1 downto 0);
-- Random trigger generator
-- Threshold trigger generator
tg0: entity work.sc_trig_gen_random
tg0: entity work.sc_trig_gen_or
generic map(
TBIT => 0,
DELAY => 2
)
port map(
clk => clk40,
en => trig_en,
mode => ctrl_rnd_mode,
sctr => sctr(31 downto 0),
rand => rand,
div => ctrl_rnd_div,
mark => mark,
force => ctrl_trig_force,
chan_trig => chan_trig,
hit => thresh_hit,
valid => tv(0),
ack => ta(0)
);
-- Threshold trigger generator
-- peaks-over-threshold trigger generator
tg1: entity work.sc_trig_gen_or
generic map(
TBIT => 0,
DELAY => 2
TBIT => 1,
DELAY => 3
)
port map(
clk => clk40,
......@@ -114,13 +108,13 @@ begin
valid => tv(1),
ack => ta(1)
);
-- peaks-over-threshold trigger generator
-- time-over-threshold trigger generator
tg2: entity work.sc_trig_gen_or
generic map(
TBIT => 1,
DELAY => 3
TBIT => 2,
DELAY => 2
)
port map(
clk => clk40,
......@@ -130,19 +124,18 @@ begin
valid => tv(2),
ack => ta(2)
);
-- time-over-threshold trigger generator
-- random / external trigger generator
tg3: entity work.sc_trig_gen_or
tg3: entity work.sc_trig_gen
generic map(
TBIT => 2,
DELAY => 2
)
port map(
clk => clk40,
en => trig_en,
mark => mark,
chan_trig => chan_trig,
trig => force,
valid => tv(3),
ack => ta(3)
);
......
components/solid/firmware/hdl/sc_rtrig.vhd
View file @ b1ab5b5e
......@@ -19,8 +19,10 @@ entity sc_rtrig is
rst40: in std_logic;
rand: in std_logic_vector(31 downto 0);
sctr: in std_logic_vector(47 downto 0);
trig: out std_logic;
trig_in: in std_logic
force: out std_logic;
thresh_hit: in std_logic;
trig_in: in std_logic;
trig_out: out std_logic
);
end sc_rtrig;
......@@ -30,6 +32,7 @@ architecture rtl of sc_rtrig is
begin
ipb_out <= IPB_RBUS_NULL;
trig <= '0';
force <= '0';
trig_out <= '0';
end rtl;
components/solid/firmware/hdl/sc_trig.vhd
View file @ b1ab5b5e
......@@ -34,6 +34,7 @@ entity sc_trig is
zs_sel: out std_logic_vector(1 downto 0);
trig: in sc_trig_array;
force: in std_logic;
thresh_hit: out std_logic;
ro_d: out std_logic_vector(31 downto 0);
ro_blkend: out std_logic;
ro_we: out std_logic;
......@@ -127,8 +128,8 @@ begin
port map(
clk => clk,
reset => rst,
ipbus_in => ipbw(N_SLV_MASKS),
ipbus_out => ipbr(N_SLV_MASKS),
ipbus_in => ipbw(N_SLV_CHAN_MASK),
ipbus_out => ipbr(N_SLV_CHAN_MASK),
q => masks
);
......@@ -145,8 +146,8 @@ begin
port map(
clk => clk,
rst => rst,
ipb_in => ipbw(N_SLV_LOC),
ipb_out => ipbr(N_SLV_LOC),
ipb_in => ipbw(N_SLV_LOC_MASK),
ipb_out => ipbr(N_SLV_LOC_MASK),
clk40 => clk40,
rst40 => rst40,
trig_en => trig_en,
......@@ -157,6 +158,8 @@ begin
trig_q => lq,
trig_valid => lvalid,
trig_ack => lack,
force => force,
thresh_hit => thresh_hit,
ro_q => t_q,
ro_valid => t_valid,
ro_blkend => t_blkend,
......
components/solid/firmware/hdl/sc_trig_gen.vhd 0 → 100644
View file @ b1ab5b5e
-- sc_trig_gen
--
-- Local trigger module based on an incoming bit
--
-- Dave Newbold, August 2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.top_decl.all;
entity sc_trig_gen is
generic(
DELAY: positive := 1
);
port(
clk: in std_logic;
en: in std_logic;
mark: in std_logic;
trig: in std_logic;
hit: out std_logic;
valid: out std_logic;
ack: in std_logic
);
end sc_trig_gen;
architecture rtl of sc_trig_gen is
signal t, m, tc, v: std_logic;
signal mark_del: std_logic_vector(DELAY - 1 downto 0);
begin
-- Define the trigger condition and block boundary
t <= trig;
mark_del <= mark_del(DELAY - 2 downto 0) & mark when rising_edge(clk);
m <= mark_del(DELAY - 1);
-- Catch a trigger feature with the block
process(clk)
begin
if rising_edge(clk) then
if en = '0' then
tc <= '0';
elsif t = '1' then
tc <= '1';
elsif m = '1' then
tc <= '0';
end if;
end if;
end process;
-- Trigger request output
hit <= t;
v <= (v or (tc and m)) and not (mark or ack or not en) when rising_edge(clk);
valid <= v;
end rtl;
components/solid/firmware/hdl/sc_trig_gen_or.vhd
View file @ b1ab5b5e
-- sc_trig_gen_thresh
-- sc_trig_gen_or
--
-- Local trigger module for simple 'ored' threshold triggers
-- This trigger will fire if any channel has a high bit in a given block
--
-- Assume threshold bits are valid 2 cycles after mark (i.e. 2nd cycle of block)
-- We produce valid flag 3 cycles after mark
--
-- Dave Newbold, August 2016
library IEEE;
......@@ -25,6 +22,7 @@ entity sc_trig_gen_or is
en: in std_logic;
mark: in std_logic;
chan_trig: in sc_trig_array;
hit: out std_logic;
valid: out std_logic;
ack: in std_logic
);
......@@ -33,14 +31,36 @@ end sc_trig_gen_or;
architecture rtl of sc_trig_gen_or is
signal mark_d, mark_dd: std_logic;
signal t, m, tc, v: std_logic;
signal mark_del: std_logic_vector(DELAY - 1 downto 0);
signal v: std_logic;
begin
-- Define the trigger condition and block boundary
t <= or_reduce(chan_trig(TBIT));
mark_del <= mark_del(DELAY - 2 downto 0) & mark when rising_edge(clk);
v <= ((v and not mark_del(DELAY - 1)) or (or_reduce(chan_trig(TBIT)) and mark_del(DELAY - 1))) and not (ack or not en) when rising_edge(clk);
m <= mark_del(DELAY - 1);
-- Catch a trigger feature with the block
process(clk)
begin
if rising_edge(clk) then
if en = '0' then
tc <= '0';
elsif t = '1' then
tc <= '1';
elsif m = '1' then
tc <= '0';
end if;
end if;
end process;
-- Trigger request output
hit <= t;
v <= (v or (tc and m)) and not (mark or ack or not en) when rising_edge(clk);
valid <= v;
end rtl;
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