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euro-adc-65m-14b-40cha
euro-adc-65m-14b-40cha-gw
Commits
af9b4532
Commit
af9b4532
authored
Apr 19, 2018
by
Dave Newbold
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Cleaning up random triggers
parent
bf793295
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5 changed files
with
4 additions
and
12 deletions
+4
-12
sc_daq.vhd
components/solid/firmware/hdl/sc_daq.vhd
+0
-2
sc_local_trig.vhd
components/solid/firmware/hdl/sc_local_trig.vhd
+1
-2
sc_roc.vhd
components/solid/firmware/hdl/sc_roc.vhd
+0
-1
sc_rtrig.vhd
components/solid/firmware/hdl/sc_rtrig.vhd
+3
-5
sc_trig.vhd
components/solid/firmware/hdl/sc_trig.vhd
+0
-2
No files found.
components/solid/firmware/hdl/sc_daq.vhd
View file @
af9b4532
...
...
@@ -184,7 +184,6 @@ begin
trig_en
=>
trig_en
,
zs_en
=>
zs_en
,
sctr
=>
sctr
,
rand
=>
rand
,
keep
=>
trig_keep
,
flush
=>
trig_flush
,
veto
=>
trig_veto
,
...
...
@@ -239,7 +238,6 @@ begin
board_id
=>
board_id
,
clk40
=>
clk40_i
,
rst40
=>
rst40_i
,
rand
=>
rand
,
d_trig
=>
trig_d
,
blkend_trig
=>
trig_blkend
,
we_trig
=>
trig_we
,
...
...
components/solid/firmware/hdl/sc_local_trig.vhd
View file @
af9b4532
...
...
@@ -24,7 +24,6 @@ entity sc_local_trig is
hops
:
in
std_logic_vector
(
31
downto
0
);
mark
:
in
std_logic
;
sctr
:
in
std_logic_vector
(
47
downto
0
);
rand
:
in
std_logic_vector
(
31
downto
0
);
chan_trig
:
in
sc_trig_array
;
trig_q
:
out
std_logic_vector
(
15
downto
0
);
trig_valid
:
out
std_logic
;
...
...
@@ -110,7 +109,7 @@ begin
tg3
:
entity
work
.
sc_trig_gen
generic
map
(
DELAY
=>
2
DELAY
=>
0
)
port
map
(
clk
=>
clk40
,
...
...
components/solid/firmware/hdl/sc_roc.vhd
View file @
af9b4532
...
...
@@ -27,7 +27,6 @@ entity sc_roc is
board_id
:
in
std_logic_vector
(
7
downto
0
);
clk40
:
in
std_logic
;
rst40
:
in
std_logic
;
rand
:
in
std_logic_vector
(
31
downto
0
);
d_trig
:
in
std_logic_vector
(
31
downto
0
);
blkend_trig
:
in
std_logic
;
we_trig
:
in
std_logic
;
...
...
components/solid/firmware/hdl/sc_rtrig.vhd
View file @
af9b4532
...
...
@@ -35,7 +35,6 @@ architecture rtl of sc_rtrig is
signal
ctrl_en
,
ctrl_mode
:
std_logic
;
signal
ctrl_div
:
std_logic_vector
(
5
downto
0
);
signal
mask
:
std_logic_vector
(
23
downto
0
);
signal
t
:
std_logic
;
begin
...
...
@@ -59,9 +58,8 @@ begin
mask
(
i
)
<=
'0'
when
i
>
to_integer
(
unsigned
(
ctrl_div
))
else
'1'
;
end
generate
;
t
<=
((
not
ctrl_mode
and
not
or_reduce
(
rand
(
mask
'range
)
and
mask
))
or
(
ctrl_mode
and
not
or_reduce
(
sctr
(
BLK_RADIX
+
mask
'left
downto
BLK_RADIX
)
and
mask
)))
and
ctrl_en
;
force
<=
t
;
force
<=
((
not
ctrl_mode
and
not
or_reduce
(
rand
(
mask
'range
)
and
mask
))
or
(
ctrl_mode
and
not
or_reduce
(
sctr
(
BLK_RADIX
+
mask
'left
downto
BLK_RADIX
)
and
mask
)))
and
ctrl_en
and
not
or_reduce
(
sctr
(
BLK_RADIX
-
1
downto
0
));
end
rtl
;
components/solid/firmware/hdl/sc_trig.vhd
View file @
af9b4532
...
...
@@ -27,7 +27,6 @@ entity sc_trig is
trig_en
:
in
std_logic
;
zs_en
:
in
std_logic
;
sctr
:
in
std_logic_vector
(
47
downto
0
);
rand
:
in
std_logic_vector
(
31
downto
0
);
keep
:
out
std_logic_vector
(
N_CHAN
-
1
downto
0
);
flush
:
out
std_logic_vector
(
N_CHAN
-
1
downto
0
);
veto
:
in
std_logic_vector
(
N_CHAN
-
1
downto
0
);
...
...
@@ -189,7 +188,6 @@ begin
hops
=>
hop_cfg
,
mark
=>
mark
,
sctr
=>
sctr
,
rand
=>
rand
,
chan_trig
=>
ctrig
,
trig_q
=>
lq
,
trig_valid
=>
lvalid
,
...
...
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