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euro-adc-65m-14b-40cha-gw
Commit a3a3483c authored by Dave Newbold's avatar Dave Newbold
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Adding pll clock routing

parent f610bc0e
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boards/pc051a/base_fw/synth/firmware/hdl/pc051a_infra.vhd
View file @ a3a3483c
......@@ -23,6 +23,8 @@ entity pc051a_infra is
clk125_o: out std_logic;
rst125_o: out std_logic;
clk200: out std_logic; -- 200MHz unbuffered clock for IDELAYCTRL
pllclk: out std_logic;
pllrefclk: out std_logic;
nuke: in std_logic; -- The signal of doom
soft_rst: in std_logic; -- The signal of lesser doom
leds: out std_logic_vector(1 downto 0); -- status LEDs
......@@ -98,6 +100,8 @@ begin
sfp_los => sfp_los,
clk125_out => clk125,
clk125_fr => clk125_fr,
pllclk => pllclk,
pllrefclk => pllrefclk,
rsti => rst_eth,
locked => eth_locked,
tx_data => mac_tx_data,
......
boards/pc051a/base_fw/synth/firmware/hdl/top_pc051a.vhd
View file @ a3a3483c
......@@ -60,6 +60,7 @@ end top;
architecture rtl of top is
signal clk_ipb, rst_ipb, clk125, rst125, nuke, soft_rst, userled, clk200, stealth_mode: std_logic;
signal pllclk, pllrefclk: std_logic;
signal ipb_out: ipb_wbus;
signal ipb_in: ipb_rbus;
signal debug: std_logic_vector(3 downto 0);
......@@ -84,6 +85,8 @@ begin
clk125_o => clk125,
rst125_o => rst125,
clk200 => clk200,
pllclk => pllclk,
pllrefclk => pllrefclk,
nuke => nuke,
soft_rst => soft_rst,
leds => infra_leds,
......@@ -111,6 +114,8 @@ begin
clk125 => clk125,
rst125 => rst125,
clk200 => clk200,
pllclk => pllclk,
pllrefclk => pllrefclk,
nuke => nuke,
soft_rst => soft_rst,
stealth_mode => stealth_mode,
......
boards/pc051b/base_fw/synth/firmware/hdl/pc051b_infra.vhd
View file @ a3a3483c
......@@ -23,6 +23,8 @@ entity pc051b_infra is
clk125_o: out std_logic;
rst125_o: out std_logic;
clk200: out std_logic; -- 200MHz unbuffered clock for IDELAYCTRL
pllclk: out std_logic;
pllrefclk: out std_logic;
nuke: in std_logic; -- The signal of doom
soft_rst: in std_logic; -- The signal of lesser doom
leds: out std_logic_vector(1 downto 0); -- status LEDs
......@@ -98,6 +100,8 @@ begin
sfp_los => sfp_los,
clk125_out => clk125,
clk125_fr => clk125_fr,
pllclk => pllclk,
pllrefclk => pllrefclk,
rsti => rst_eth,
locked => eth_locked,
tx_data => mac_tx_data,
......
boards/pc051b/base_fw/synth/firmware/hdl/top_pc051b.vhd
View file @ a3a3483c
......@@ -44,6 +44,7 @@ end top;
architecture rtl of top is
signal clk_ipb, rst_ipb, clk125, rst125, nuke, soft_rst, userled, clk200, stealth_mode: std_logic;
signal pllclk, pllrefclk: std_logic;
signal ipb_out: ipb_wbus;
signal ipb_in: ipb_rbus;
signal debug: std_logic_vector(3 downto 0);
......@@ -70,6 +71,8 @@ begin
clk125_o => clk125,
rst125_o => rst125,
clk200 => clk200,
pllclk => pllclk,
pllrefclk => pllrefclk,
nuke => nuke,
soft_rst => soft_rst,
leds => infra_leds,
......@@ -93,6 +96,8 @@ begin
clk125 => clk125,
rst125 => rst125,
clk200 => clk200,
pllclk => pllclk,
pllrefclk => pllrefclk,
nuke => nuke,
soft_rst => soft_rst,
stealth_mode => stealth_mode,
......
components/solid/firmware/hdl/sc_daq.vhd
View file @ a3a3483c
......@@ -33,6 +33,8 @@ entity sc_daq is
d_n: in std_logic_vector(N_CHAN - 1 downto 0);
clk125: in std_logic;
rst125: in std_logic;
pllclk: in std_logic;
pllrefclk: in std_logic;
board_id: in std_logic_vector(7 downto 0)
);
......@@ -212,6 +214,8 @@ begin
ipb_out => ipbr(N_SLV_TLINK),
clk125 => clk125,
rst125 => rst125,
pllclk => pllclk,
pllrefclk => pllrefclk,
link_ok => link_ok,
clk40 => clk40_i,
rst40 => rst40_i,
......
projects/64ch/firmware/hdl/payload.vhd
View file @ a3a3483c
......@@ -24,6 +24,8 @@ entity payload is
clk125: in std_logic;
rst125: in std_logic;
clk200: in std_logic;
pllclk: in std_logic;
pllrefclk: in std_logic;
nuke: out std_logic;
soft_rst: out std_logic;
stealth_mode: out std_logic;
......@@ -161,6 +163,8 @@ begin
d_n => adc_d_n,
clk125 => clk125,
rst125 => rst125,
pllclk => pllclk,
pllrefclk => pllrefclk,
board_id => addr
);
......
projects/8ch/firmware/hdl/payload.vhd
View file @ a3a3483c
......@@ -24,6 +24,8 @@ entity payload is
clk125: in std_logic;
rst125: in std_logic;
clk200: in std_logic;
pllclk: in std_logic;
pllrefclk: in std_logic;
nuke: out std_logic;
soft_rst: out std_logic;
stealth_mode: out std_logic;
......@@ -216,6 +218,8 @@ begin
d_n => adc_d_n,
clk125 => clk125,
rst125 => rst125,
pllclk => pllclk,
pllrefclk => pllrefclk,
board_id => ctrl_board_id
);
......
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