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euro-adc-65m-14b-40cha-gw
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eurocard
euro-adc-65m-14b-40cha
euro-adc-65m-14b-40cha-gw
Commits
a2173ca6
Commit
a2173ca6
authored
Nov 03, 2017
by
Dave Newbold (UoB)
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Fixing align script again
parent
b745568a
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4 changed files
with
10 additions
and
11 deletions
+10
-11
pc051a_infra.vhd
boards/pc051a/base_fw/synth/firmware/hdl/pc051a_infra.vhd
+1
-1
top_pc051a.vhd
boards/pc051a/base_fw/synth/firmware/hdl/top_pc051a.vhd
+1
-1
align_adc.py
projects/64ch/software/align_adc.py
+5
-5
payload.vhd
projects/8ch/firmware/hdl/payload.vhd
+3
-4
No files found.
boards/pc051a/base_fw/synth/firmware/hdl/pc051a_infra.vhd
View file @
a2173ca6
...
...
@@ -81,7 +81,7 @@ begin
q
=>
led_p
);
leds
<=
(
led_p
(
0
),
locked
&
onehz
);
leds
<=
(
led_p
(
0
),
locked
and
onehz
);
debug
<=
(
others
=>
'0'
);
...
...
boards/pc051a/base_fw/synth/firmware/hdl/top_pc051a.vhd
View file @
a2173ca6
...
...
@@ -86,7 +86,7 @@ begin
clk200
=>
clk200
,
nuke
=>
nuke
,
soft_rst
=>
soft_rst
,
leds
=>
i
i
nfra_leds
,
leds
=>
infra_leds
,
debug
=>
open
,
mac_addr
(
47
downto
4
)
=>
MAC_ADDR
(
47
downto
4
),
mac_addr
(
3
downto
0
)
=>
dip_sw
,
...
...
projects/64ch/software/align_adc.py
View file @
a2173ca6
...
...
@@ -35,7 +35,7 @@ offsets = [0, 13, 2, 1, 4, 3, 6, 5, 8, 7, 10, 9, 12, 11]
invert
=
[
0x1d
,
0x1e
,
0x1f
,
0x20
,
0x21
,
0x22
,
0x23
,
0x24
,
0x25
]
uhal
.
setLogLevelTo
(
uhal
.
LogLevel
.
ERROR
)
board
=
uhal
.
getDevice
(
"board"
,
"ipbusudp-2.0://192.168.235.
86
:50001"
,
"file://addrtab/top.xml"
)
board
=
uhal
.
getDevice
(
"board"
,
"ipbusudp-2.0://192.168.235.
50
:50001"
,
"file://addrtab/top.xml"
)
#board = uhal.getDevice("board", "ipbusudp-2.0://192.168.235.16:50001", "file://addrtab/top_sim.xml")
board
.
getClient
()
.
setTimeoutPeriod
(
10000
)
...
...
@@ -50,7 +50,7 @@ board.dispatch()
time
.
sleep
(
1
)
chans
=
range
(
0x
64
)
chans
=
range
(
0x
40
)
adcs
=
range
(
0x10
)
patt
=
0x0ff
cap_len
=
0x80
...
...
@@ -80,7 +80,7 @@ for i_chan in chans:
res
=
[
False
]
*
(
15
*
taps_per_slip
)
tr
=
[]
for
i_slip
in
range
(
1
):
for
i_slip
in
range
(
1
4
):
ok
=
False
for
i_tap
in
range
(
32
):
board
.
getNode
(
"daq.timing.csr.ctrl.chan_cap"
)
.
write
(
0x1
)
# Capture
...
...
@@ -99,8 +99,8 @@ for i_chan in chans:
for
w
in
d
:
if
int
(
w
)
&
0x3ff
==
patt
:
c
+=
1
#
print hex(w),
#
print hex(i_chan), hex(i_slip), hex(i_tap), c
#
print hex(w),
#
print hex(i_chan), hex(i_slip), hex(i_tap), c
res
[
offsets
[
i_slip
]
*
taps_per_slip
+
(
31
-
i_tap
)]
=
(
c
==
cap_len
)
ok
=
(
c
==
cap_len
)
or
ok
board
.
getNode
(
"daq.timing.csr.ctrl.chan_inc"
)
.
write
(
0x1
)
# Increment tap
...
...
projects/8ch/firmware/hdl/payload.vhd
View file @
a2173ca6
...
...
@@ -74,8 +74,7 @@ architecture rtl of payload is
signal
ctrl_rst_mmcm
,
locked
,
idelayctrl_rdy
,
ctrl_rst_idelayctrl
,
ctrl_sync_mode
,
ctrl_stealth_mode
:
std_logic
;
signal
ctrl_chan
:
std_logic_vector
(
7
downto
0
);
signal
ctrl_board_id
:
std_logic_vector
(
7
downto
0
);
signal
chan_err
,
led
:
std_logic
;
signal
daq_leds
:
std_logic_vector
(
2
downto
0
);
signal
chan_err
,
led
,
daq_led
:
std_logic
;
begin
...
...
@@ -123,7 +122,7 @@ begin
ctrl_board_id
<=
ctrl
(
0
)(
23
downto
16
);
stealth_mode
<=
ctrl_stealth_mode
;
userleds
<=
"000
0
"
&
daq_led
when
ctrl_stealth_mode
=
'0'
else
(
others
=>
'0'
);
userleds
<=
"000"
&
daq_led
when
ctrl_stealth_mode
=
'0'
else
(
others
=>
'0'
);
-- Required for timing alignment at inputs
...
...
@@ -210,7 +209,7 @@ begin
sync_in
=>
sync_in
,
trig_in
=>
trig_in
,
trig_out
=>
trig_out
,
led_out
=>
daq_led
s
(
2
)
,
led_out
=>
daq_led
,
chan
=>
ctrl_chan
,
chan_err
=>
chan_err
,
d_p
=>
adc_d_p
,
...
...
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