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euro-adc-65m-14b-40cha-gw
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euro-adc-65m-14b-40cha
euro-adc-65m-14b-40cha-gw
Commits
9a87e6c4
Commit
9a87e6c4
authored
Jun 20, 2017
by
Dave Newbold
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Syntax fix
parent
bb9aa1b4
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3 changed files
with
1 addition
and
3 deletions
+1
-3
sc_chan_trig.vhd
components/solid/firmware/hdl/sc_chan_trig.vhd
+1
-1
sc_ctrig_npeaks.vhd
components/solid/firmware/hdl/sc_ctrig_npeaks.vhd
+0
-1
sc_ctrig_tot.vhd
components/solid/firmware/hdl/sc_ctrig_tot.vhd
+0
-1
No files found.
components/solid/firmware/hdl/sc_chan_trig.vhd
View file @
9a87e6c4
...
...
@@ -74,7 +74,7 @@ begin
port
map
(
clk
=>
clk40
,
rst
=>
rst40
,
clr
=>
mark
,
en
=>
en
,
d
=>
dd
,
cthresh
=>
ctrl
(
1
)(
24
downto
16
),
wsize
=>
ctrl
(
1
)(
31
downto
28
),
...
...
components/solid/firmware/hdl/sc_ctrig_npeaks.vhd
View file @
9a87e6c4
...
...
@@ -15,7 +15,6 @@ entity sc_ctrig_npeaks is
port
(
clk
:
in
std_logic
;
rst
:
in
std_logic
;
clr
:
in
std_logic
;
en
:
in
std_logic
;
d
:
in
std_logic_vector
(
VAL_WIDTH
-
1
downto
0
);
cthresh
:
in
std_logic_vector
(
8
downto
0
);
...
...
components/solid/firmware/hdl/sc_ctrig_tot.vhd
View file @
9a87e6c4
...
...
@@ -15,7 +15,6 @@ entity sc_ctrig_tot is
port
(
clk
:
in
std_logic
;
rst
:
in
std_logic
;
clr
:
in
std_logic
;
en
:
in
std_logic
;
d
:
in
std_logic_vector
(
VAL_WIDTH
-
1
downto
0
);
cthresh
:
in
std_logic_vector
(
8
downto
0
);
...
...
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