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euro-adc-65m-14b-40cha-gw
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euro-adc-65m-14b-40cha
euro-adc-65m-14b-40cha-gw
Commits
91f78627
Commit
91f78627
authored
Nov 11, 2017
by
Dave Newbold
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Adding loc constraints for MGTs
parent
05796eba
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pc051a.tcl
boards/pc051a/base_fw/synth/firmware/ucf/pc051a.tcl
+2
-0
pc051b.tcl
boards/pc051b/base_fw/synth/firmware/ucf/pc051b.tcl
+2
-0
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boards/pc051a/base_fw/synth/firmware/ucf/pc051a.tcl
View file @
91f78627
...
...
@@ -29,6 +29,8 @@ set_property PACKAGE_PIN F6 [get_ports eth_clk_p]
set_property PACKAGE_PIN E6
[
get_ports eth_clk_n
]
set_property LOC GTPE2_CHANNEL_X0Y4
[
get_cells -hier -filter
{
name=~infra/eth/*/gtpe2_i
}]
set_property LOC GTPE2_CHANNEL_X0Y6
[
get_cells -hier -filter
{
name=~tlink/mgt_us/*/gtpe2_i
}]
set_property LOC GTPE2_CHANNEL_X0Y7
[
get_cells -hier -filter
{
name=~tlink/mgt_ds/*/gtpe2_i
}]
proc
false_path
{
patt clk
}
{
set p
[
get_ports -quiet
$patt
-filter
{
direction != out
}]
...
...
boards/pc051b/base_fw/synth/firmware/ucf/pc051b.tcl
View file @
91f78627
...
...
@@ -24,6 +24,8 @@ set_property PACKAGE_PIN F6 [get_ports eth_clk_p]
set_property PACKAGE_PIN E6
[
get_ports eth_clk_n
]
set_property LOC GTPE2_CHANNEL_X0Y4
[
get_cells -hier -filter
{
name=~infra/eth/*/gtpe2_i
}]
set_property LOC GTPE2_CHANNEL_X0Y6
[
get_cells -hier -filter
{
name=~tlink/mgt_us/*/gtpe2_i
}]
set_property LOC GTPE2_CHANNEL_X0Y7
[
get_cells -hier -filter
{
name=~tlink/mgt_ds/*/gtpe2_i
}]
proc
false_path
{
patt clk
}
{
set p
[
get_ports -quiet
$patt
-filter
{
direction != out
}]
...
...
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