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euro-adc-65m-14b-40cha-gw
Commit 81e3f7a2 authored by Dave Newbold's avatar Dave Newbold
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Adding kack, removing veto

parent c145bdb1
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Showing with 49 additions and 60 deletions
components/solid/firmware/hdl/sc_chan.vhd
View file @ 81e3f7a2
......@@ -42,8 +42,8 @@ entity sc_chan is
zs_en: in std_logic;
keep: in std_logic;
flush: in std_logic;
kack: out std_logic;
err: out std_logic;
veto: out std_logic;
trig: out std_logic_vector(N_CHAN_TRG - 1 downto 0);
clk_dr: in std_logic;
q: out std_logic_vector(31 downto 0);
......@@ -73,7 +73,7 @@ architecture rtl of sc_chan is
signal zs_thresh: std_logic_vector(13 downto 0);
signal sctr_p: std_logic_vector(11 downto 0);
signal dr_d: std_logic_vector(31 downto 0);
signal ro_en, keep_i, flush_i, err_i, blkend, dr_blkend, dr_wen: std_logic;
signal ro_en, err_i, blkend, dr_blkend, dr_wen: std_logic;
begin
......@@ -171,9 +171,7 @@ begin
err_i <= buf_full or dr_full;
err <= err_i;
ro_en <= not (ctrl_mode or err_i) and ctrl_en_buf;
keep_i <= keep and ro_en;
flush_i <= flush and ro_en;
veto <= dr_warn or not ro_en;
-- veto <= dr_warn or not ro_en;
-- ZS thresholds
......@@ -226,8 +224,9 @@ begin
zs_thresh => zs_thresh,
zs_en => zs_en,
buf_full => buf_full,
keep => keep_i,
flush => flush_i,
keep => keep,
flush => flush,
kack => kack,
q => dr_d,
q_blkend => dr_blkend,
wen => dr_wen
......
components/solid/firmware/hdl/sc_chan_buf.vhd
View file @ 81e3f7a2
......@@ -36,6 +36,7 @@ entity sc_chan_buf is
buf_full: out std_logic; -- buffer err flag; clk40 dom
keep: in std_logic; -- block transfer cmd; clk40 dom
flush: in std_logic; -- block discard cmd; clk40 dom
kack: out std_logic;
q: out std_logic_vector(31 downto 0); -- output to derand; clk40 dom
q_blkend: out std_logic;
wen: out std_logic -- derand write enable
......@@ -210,6 +211,7 @@ begin
-- Readout to derand
kack <= keep;
go <= keep or flush;
process(clk40)
......
components/solid/firmware/hdl/sc_channels.vhd
View file @ 81e3f7a2
......@@ -36,10 +36,10 @@ entity sc_channels is
nzs_blks: in std_logic_vector(3 downto 0);
nzs_en: in std_logic;
zs_en: in std_logic;
keep: in std_logic_vector(N_CHAN - 1 downto 0);
flush: in std_logic_vector(N_CHAN - 1 downto 0);
keep: in std_logic;
flush: in std_logic;
kack: out std_logic_vector(N_CHAN - 1 downto 0);
err: out std_logic;
veto: out std_logic_vector(N_CHAN - 1 downto 0);
trig: out sc_trig_array;
dr_chan: in std_logic_vector(7 downto 0);
clk_dr: in std_logic;
......@@ -113,10 +113,10 @@ begin
nzs_blks => nzs_blks,
nzs_en => nzs_en,
zs_en => zs_en,
keep => keep(i),
flush => flush(i),
keep => keep,
flush => flush,
kack => kack(i),
err => chan_err(i),
veto => veto(i),
trig => ltrig,
clk_dr => clk_dr,
q => chan_q(i),
......
components/solid/firmware/hdl/sc_daq.vhd
View file @ 81e3f7a2
......@@ -48,7 +48,8 @@ architecture rtl of sc_daq is
signal sync_ctrl: std_logic_vector(3 downto 0);
signal sctr: std_logic_vector(47 downto 0);
signal trig_en, nzs_en, zs_en: std_logic;
signal trig_keep, trig_flush, trig_veto: std_logic_vector(N_CHAN - 1 downto 0);
signal trig_keep, trig_flush: std_logic;
signal trig_kack: std_logic_vector(N_CHAN - 1 downto 0);
signal fake: std_logic_vector(13 downto 0);
signal force_trig, thresh_hit: std_logic;
signal nzs_blks: std_logic_vector(3 downto 0);
......@@ -162,8 +163,8 @@ begin
zs_en => zs_en,
keep => trig_keep,
flush => trig_flush,
kack => trig_kack,
err => chan_err,
veto => trig_veto,
trig => chan_trig,
dr_chan => ro_chan,
clk_dr => ipb_clk,
......@@ -189,7 +190,7 @@ begin
sctr => sctr,
keep => trig_keep,
flush => trig_flush,
veto => trig_veto,
kack => trig_kack,
zs_sel => zs_sel,
trig => chan_trig,
force => force_trig,
......
components/solid/firmware/hdl/sc_seq.vhd
View file @ 81e3f7a2
......@@ -35,8 +35,8 @@ entity sc_seq is
d_ext: in std_logic_vector(15 downto 0);
valid_ext: in std_logic;
ack_ext: out std_logic;
keep: out std_logic_vector(N_CHAN - 1 downto 0);
flush: out std_logic_vector(N_CHAN - 1 downto 0);
keep: out std_logic;
flush: out std_logic;
err: out std_logic
);
......@@ -196,7 +196,7 @@ begin
end if;
end process;
keep <= (keep'range => keep_i);
flush <= not (flush'range => keep_i);
keep <= keep_i;
flush <= not keep_i;
end rtl;
components/solid/firmware/hdl/sc_trig.vhd
View file @ 81e3f7a2
......@@ -27,9 +27,9 @@ entity sc_trig is
trig_en: in std_logic;
zs_en: in std_logic;
sctr: in std_logic_vector(47 downto 0);
keep: out std_logic_vector(N_CHAN - 1 downto 0);
flush: out std_logic_vector(N_CHAN - 1 downto 0);
veto: in std_logic_vector(N_CHAN - 1 downto 0);
keep: out std_logic;
flush: out std_logic;
kack: in std_logic_vector(N_CHAN - 1 downto 0);
zs_sel: out std_logic_vector(1 downto 0);
trig: in sc_trig_array;
force: in std_logic;
......@@ -255,20 +255,8 @@ begin
-- Channel interface
veto_p <= veto or (veto'range => rveto);
keep <= keep_i and not veto_p when mark = '1' else (others => '0');
flush <= not keep_i or veto_p when mark = '1' else (others => '0');
process(clk40)
begin
if rising_edge(clk40) then
if trig_en = '0' then
veto_i <= (others => '0');
elsif mark = '1' then
veto_i <= veto_p;
end if;
end if;
end process;
keep <= keep_i and mark;
flush <= flush_i and mark;
-- Readout header to ROC
......@@ -280,7 +268,7 @@ begin
sctr => sctr,
mark => mark,
keep => keep_i,
veto => veto_i,
kack => kack,
tctr => tctr,
ro_q => b_q,
ro_valid => b_valid,
......@@ -313,21 +301,23 @@ begin
-- Deadtime monitor
dmon: entity work.sc_deadtime_mon
port map(
clk => clk,
rst => rst,
ipb_in => ipbw(N_SLV_DTMON),
ipb_out => ipbr(N_SLV_DTMON),
en => ctrl_dtmon_en,
clk40 => clk40,
rst40 => rst40,
clk160 => clk160,
mark => mark,
sctr => sctr(BLK_RADIX - 1 downto 0),
keep => keep_i,
veto => veto_i
);
-- dmon: entity work.sc_deadtime_mon
-- port map(
-- clk => clk,
-- rst => rst,
-- ipb_in => ipbw(N_SLV_DTMON),
-- ipb_out => ipbr(N_SLV_DTMON),
-- en => ctrl_dtmon_en,
-- clk40 => clk40,
-- rst40 => rst40,
-- clk160 => clk160,
-- mark => mark,
-- sctr => sctr(BLK_RADIX - 1 downto 0),
-- keep => keep_i,
-- veto => veto_i
-- );
ipbr(N_SLV_DTMON) <= IPB_RBUS_NULL;
-- Ext trigger
......
components/solid/firmware/hdl/sc_trig_ro_block.vhd
View file @ 81e3f7a2
......@@ -19,8 +19,8 @@ entity sc_trig_ro_block is
trig_en: in std_logic;
sctr: in std_logic_vector(47 downto 0);
mark: in std_logic;
keep: in std_logic_vector(N_CHAN - 1 downto 0);
veto: in std_logic_vector(N_CHAN - 1 downto 0);
keep: in std_logic;
kack: in std_logic_vector(N_CHAN - 1 downto 0);
tctr: out std_logic_vector(27 downto 0);
ro_q: out std_logic_vector(31 downto 0);
ro_valid: out std_logic;
......@@ -58,8 +58,7 @@ begin
-- Block data to ROC
chen <= (63 downto N_CHAN => '0') & (keep and not veto); -- Assumption on 64 channels max here...
keep_c <= (63 downto N_CHAN => '0') & keep;
keep_c <= (63 downto N_CHAN => '0') & kack;
go <= (go or (ro_go and or_reduce(keep) and not rveto)) and not blkend and trig_en when rising_edge(clk40);
blkend <= '1' when ro_ctr = X"06" else '0';
......@@ -83,9 +82,7 @@ begin
X"0" & std_logic_vector(tctr_i) when X"00", -- Type 0
std_logic_vector(bctr) & (BLK_RADIX - 1 downto 0 => '0') when X"01",
X"0000" & std_logic_vector(sctr(47 downto 32)) when X"02",
chen(31 downto 0) when X"03", -- Corresponds to CH_WORD = 3 in sc_roc
chen(63 downto 32) when X"04",
keep_c(31 downto 0) when X"05",
keep_c(31 downto 0) when X"03",
keep_c(63 downto 32) when others;
end rtl;
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