Commit 79a80152 authored by Dave Newbold's avatar Dave Newbold

First cleanup of dep files for ipbb

parent 5a48690b
......@@ -13,8 +13,8 @@ operating system (e.g. Centos7) is required.
source ipbb-0.2.3/env.sh
ipbb init build
cd build
ipbb add git https://github.com/ipbus/ipbus-firmware.git -b tags/ipbus_2_0_v1
ipbb add git BITBUCKET-URL -b tags/v8
ipbb add git https://github.com/ipbus/ipbus-firmware.git -b ipbus_2_0_v1
ipbb add git BITBUCKET-URL -b v8
ipbb proj create vivado 64chan solid:projects/64chan_test
cd proj/64chan
ipbb vivado project
......
set xlib $::env(XILINX_SIMLIBS)
vmap secureip $xlib/secureip
vmap unisim $xlib/unisim
vmap unimacro $xlib/unimacro
vmap unifast $xlib/unifast
vmap unisims_ver $xlib/unisims_ver
vmap unimacro_ver $xlib/unimacro_ver
vmap unifast_ver $xlib/unifast_ver
vmap simprims_ver $xlib/simprims_ver
src pc051a_infra_sim.vhd
src -c ipbus-firmware:components/ipbus_util ../sim_hdl/clock_sim_7s.vhd
src -c ipbus-firmware:components/ipbus_eth ../sim/eth_mac_sim.vhd
include -c ipbus-firmware:components/ipbus_core
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
@device_family = "artix7"
@device_name = "xc7a200t"
@device_package = "fbg484"
@device_speed = "-2"
@boardname = "pc051a"
setup lib_mappings.tcl
src top_pc051a_sim.vhd
include pc051a_infra_sim.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
-- kc705_basex_infra
--
-- All board-specific stuff goes here.
--
-- Dave Newbold, June 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
entity pc051a_infra_sim is
port(
clk_ipb_o: out std_logic; -- IPbus clock
rst_ipb_o: out std_logic;
clk125_o: out std_logic;
rst125_o: out std_logic;
nuke: in std_logic; -- The signal of doom
soft_rst: in std_logic; -- The signal of lesser doom
mac_addr: in std_logic_vector(47 downto 0); -- MAC address
ip_addr: in std_logic_vector(31 downto 0); -- IP address
ipb_in: in ipb_rbus; -- ipbus
ipb_out: out ipb_wbus
);
end pc051a_infra_sim;
architecture rtl of pc051a_infra_sim is
signal clk125_fr, clk125, clk_ipb, clk_ipb_i, rst125, rst_ipb, rst_ipb_ctrl: std_logic;
signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
begin
-- DCM clock generation for internal bus, ethernet
clocks: entity work.clock_sim_7s
port map(
clko_125 => clk125,
clko_ipb => clk_ipb_i,
locked => open,
nuke => nuke,
soft_rst => soft_rst,
rsto_125 => rst125,
rsto_ipb => rst_ipb,
rsto_ipb_ctrl => rst_ipb_ctrl
);
clk_ipb <= clk_ipb_i; -- Best to align delta delays on all clocks for simulation
clk_ipb_o <= clk_ipb_i;
rst_ipb_o <= rst_ipb;
clk125_o <= clk125;
rst125_o <= rst125;
-- Ethernet MAC core and PHY interface
eth: entity work.eth_mac_sim
generic map(
MULTI_PACKET => true
)
port map(
clk => clk125,
rst => rst125,
tx_data => mac_tx_data,
tx_valid => mac_tx_valid,
tx_last => mac_tx_last,
tx_error => mac_tx_error,
tx_ready => mac_tx_ready,
rx_data => mac_rx_data,
rx_valid => mac_rx_valid,
rx_last => mac_rx_last,
rx_error => mac_rx_error
);
-- ipbus control logic
ipbus: entity work.ipbus_ctrl
port map(
mac_clk => clk125,
rst_macclk => rst125,
ipb_clk => clk_ipb,
rst_ipb => rst_ipb_ctrl,
mac_rx_data => mac_rx_data,
mac_rx_valid => mac_rx_valid,
mac_rx_last => mac_rx_last,
mac_rx_error => mac_rx_error,
mac_tx_data => mac_tx_data,
mac_tx_valid => mac_tx_valid,
mac_tx_last => mac_tx_last,
mac_tx_error => mac_tx_error,
mac_tx_ready => mac_tx_ready,
ipb_out => ipb_out,
ipb_in => ipb_in,
mac_addr => mac_addr,
ip_addr => ip_addr
);
end rtl;
-- Top-level design for ipbus demo
--
-- You must edit this file to set the IP and MAC addresses
--
-- Dave Newbold, 08/01/16
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
use work.top_decl.all;
entity top is
end top;
architecture rtl of top is
signal clk_ipb, rst_ipb, clk125, rst125, nuke, soft_rst, userled, clk200: std_logic;
signal ipb_out: ipb_wbus;
signal ipb_in: ipb_rbus;
begin
-- Infrastructure
infra: entity work.pc051a_infra_sim -- Should work for artix also...
port map(
clk_ipb_o => clk_ipb,
rst_ipb_o => rst_ipb,
clk125_o => clk125,
rst125_o => rst125,
nuke => nuke,
soft_rst => soft_rst,
mac_addr => MAC_ADDR,
ip_addr => IP_ADDR,
ipb_in => ipb_in,
ipb_out => ipb_out
);
payload: entity work.payload_sim
port map(
ipb_clk => clk_ipb,
ipb_rst => rst_ipb,
ipb_in => ipb_out,
ipb_out => ipb_in,
clk125 => clk125,
rst125 => rst125,
nuke => nuke,
soft_rst => soft_rst
);
end rtl;
@device_family = "artix7"
@device_name = "xc7a200t"
@device_package = "fbg484"
@device_speed = "-2"
@boardname = "pc051a"
setup settings_v7.tcl
src top_pc051a.vhd
include pc051a_infra.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
src --cd ../ucf pc051a.tcl
src pc051a_infra.vhd
src -c ipbus-firmware:components/ipbus_util clocks_7s_serdes.vhd ipbus_clock_div.vhd led_stretcher.vhd
include -c ipbus-firmware:components/ipbus_core
include -c ipbus-firmware:components/ipbus_eth artix_basex.dep
src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd ipbus_package.vhd
set obj [get_projects top]
set_property "default_lib" "xil_defaultlib" $obj
set_property "simulator_language" "Mixed" $obj
set_property "source_mgmt_mode" "DisplayOnly" $obj
set_property "target_language" "VHDL" $obj
-- kc705_basex_infra
--
-- All board-specific stuff goes here.
--
-- Dave Newbold, June 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
entity pc051a_infra is
port(
eth_clk_p: in std_logic; -- 125MHz MGT clock
eth_clk_n: in std_logic;
eth_rx_p: in std_logic; -- Ethernet MGT input
eth_rx_n: in std_logic;
eth_tx_p: out std_logic; -- Ethernet MGT output
eth_tx_n: out std_logic;
sfp_los: in std_logic;
clk_ipb_o: out std_logic; -- IPbus clock
rst_ipb_o: out std_logic;
clk125_o: out std_logic;
rst125_o: out std_logic;
clk200: out std_logic; -- 200MHz unbuffered clock for IDELAYCTRL
nuke: in std_logic; -- The signal of doom
soft_rst: in std_logic; -- The signal of lesser doom
leds: out std_logic_vector(1 downto 0); -- status LEDs
debug: out std_logic_vector(3 downto 0);
mac_addr: in std_logic_vector(47 downto 0); -- MAC address
ip_addr: in std_logic_vector(31 downto 0); -- IP address
ipb_in: in ipb_rbus; -- ipbus
ipb_out: out ipb_wbus
);
end pc051a_infra;
architecture rtl of pc051a_infra is
signal clk125_fr, clk125, clk_ipb, clk_ipb_i, locked, clk_locked, eth_locked, rst125, rst_ipb, rst_ipb_ctrl, rst_eth, onehz, pkt: std_logic;
signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
signal led_p: std_logic_vector(0 downto 0);
begin
-- DCM clock generation for internal bus, ethernet
clocks: entity work.clocks_7s_serdes
port map(
clki_fr => clk125_fr,
clki_125 => clk125,
clko_ipb => clk_ipb_i,
clko_200 => clk200,
eth_locked => eth_locked,
locked => clk_locked,
nuke => nuke,
soft_rst => soft_rst,
rsto_125 => rst125,
rsto_ipb => rst_ipb,
rsto_eth => rst_eth,
rsto_ipb_ctrl => rst_ipb_ctrl,
onehz => onehz
);
clk_ipb <= clk_ipb_i; -- Best to align delta delays on all clocks for simulation
clk_ipb_o <= clk_ipb_i;
rst_ipb_o <= rst_ipb;
clk125_o <= clk125;
rst125_o <= rst125;
locked <= clk_locked and eth_locked;
stretch: entity work.led_stretcher
generic map(
WIDTH => 1
)
port map(
clk => clk125,
d(0) => pkt,
q => led_p
);
leds <= ('0', onehz);
debug <= sfp_los & '0' & led_p(0) & (locked and onehz);
-- Ethernet MAC core and PHY interface
eth: entity work.eth_7s_1000basex_gtp
port map(
gt_clkp => eth_clk_p,
gt_clkn => eth_clk_n,
gt_txp => eth_tx_p,
gt_txn => eth_tx_n,
gt_rxp => eth_rx_p,
gt_rxn => eth_rx_n,
sfp_los => sfp_los,
clk125_out => clk125,
clk125_fr => clk125_fr,
rsti => rst_eth,
locked => eth_locked,
tx_data => mac_tx_data,
tx_valid => mac_tx_valid,
tx_last => mac_tx_last,
tx_error => mac_tx_error,
tx_ready => mac_tx_ready,
rx_data => mac_rx_data,
rx_valid => mac_rx_valid,
rx_last => mac_rx_last,
rx_error => mac_rx_error
);
-- ipbus control logic
ipbus: entity work.ipbus_ctrl
port map(
mac_clk => clk125,
rst_macclk => rst125,
ipb_clk => clk_ipb,
rst_ipb => rst_ipb_ctrl,
mac_rx_data => mac_rx_data,
mac_rx_valid => mac_rx_valid,
mac_rx_last => mac_rx_last,
mac_rx_error => mac_rx_error,
mac_tx_data => mac_tx_data,
mac_tx_valid => mac_tx_valid,
mac_tx_last => mac_tx_last,
mac_tx_error => mac_tx_error,
mac_tx_ready => mac_tx_ready,
ipb_out => ipb_out,
ipb_in => ipb_in,
mac_addr => mac_addr,
ip_addr => ip_addr,
pkt => pkt
);
end rtl;
-- Top-level design for ipbus demo
--
-- You must edit this file to set the IP and MAC addresses
--
-- Dave Newbold, 08/01/16
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
use work.top_decl.all;
entity top is port(
eth_clk_p: in std_logic; -- 125MHz MGT clock
eth_clk_n: in std_logic;
eth_rx_p: in std_logic; -- Ethernet MGT input
eth_rx_n: in std_logic;
eth_tx_p: out std_logic; -- Ethernet MGT output
eth_tx_n: out std_logic;
sfp_los: in std_logic;
sfp_tx_disable: out std_logic;
sfp_scl: out std_logic;
sfp_sda: out std_logic;
leds: out std_logic_vector(1 downto 0); -- TE712 LEDs
leds_c: out std_logic_vector(3 downto 0); -- carrier LEDs
dip_sw: in std_logic_vector(3 downto 0); -- carrier switches
si5326_scl: out std_logic;
si5326_sda: inout std_logic;
si5326_rstn: out std_logic;
si5326_phase_inc: out std_logic;
si5326_phase_dec: out std_logic;
si5326_clk1_validn: in std_logic;
si5326_clk2_validn: in std_logic;
si5326_lol: in std_logic;
si5326_clk_sel: out std_logic;
si5326_rate0: out std_logic;
si5326_rate1: out std_logic;
clk40_p: in std_logic;
clk40_n: in std_logic;
adc_spi_cs: out std_logic_vector(1 downto 0);
adc_spi_mosi: out std_logic;
adc_spi_miso: in std_logic_vector(1 downto 0);
adc_spi_sclk: out std_logic;
adc_d_p: in std_logic_vector(N_CHAN - 1 downto 0);
adc_d_n: in std_logic_vector(N_CHAN - 1 downto 0);
analog_scl: out std_logic;
analog_sda: inout std_logic;
sync_a_p: inout std_logic;
sync_a_n: inout std_logic;
sync_b_p: inout std_logic;
sync_b_n: inout std_logic;
-- sync_c_p: inout std_logic;
-- sync_c_n: inout std_logic;
clk_pll_p: out std_logic;
clk_pll_n: out std_logic
);
end top;
architecture rtl of top is
signal clk_ipb, rst_ipb, clk125, rst125, nuke, soft_rst, userled, clk200: std_logic;
signal ipb_out: ipb_wbus;
signal ipb_in: ipb_rbus;
signal debug: std_logic_vector(3 downto 0);
signal si5326_sda_o, analog_sda_o: std_logic;
begin
-- Infrastructure
infra: entity work.pc051a_infra -- Should work for artix also...
port map(
eth_clk_p => eth_clk_p,
eth_clk_n => eth_clk_n,
eth_tx_p => eth_tx_p,
eth_tx_n => eth_tx_n,
eth_rx_p => eth_rx_p,
eth_rx_n => eth_rx_n,
sfp_los => sfp_los,
clk_ipb_o => clk_ipb,
rst_ipb_o => rst_ipb,
clk125_o => clk125,
rst125_o => rst125,
clk200 => clk200,
nuke => nuke,
soft_rst => soft_rst,
leds => leds(1 downto 0),
debug => leds_c,
mac_addr(47 downto 4) => MAC_ADDR(47 downto 4),
mac_addr(3 downto 0) => dip_sw,
ip_addr(31 downto 4) => IP_ADDR(31 downto 4),
ip_addr(3 downto 0) => dip_sw,
ipb_in => ipb_in,
ipb_out => ipb_out
);
sfp_tx_disable <= '0';
sfp_scl <= '1';
sfp_sda <= '1';
payload: entity work.payload
port map(
ipb_clk => clk_ipb,
ipb_rst => rst_ipb,
ipb_in => ipb_out,
ipb_out => ipb_in,
clk125 => clk125,
rst125 => rst125,
clk200 => clk200,
nuke => nuke,
soft_rst => soft_rst,
userleds => open,
si5326_scl => si5326_scl,
si5326_sda_o => si5326_sda_o,
si5326_sda_i => si5326_sda,
si5326_rstn => si5326_rstn,
si5326_phase_inc => si5326_phase_inc,
si5326_phase_dec => si5326_phase_dec,
si5326_clk1_validn => si5326_clk1_validn,
si5326_clk2_validn => si5326_clk2_validn,
si5326_lol => si5326_lol,
si5326_clk_sel => si5326_clk_sel,
si5326_rate0 => si5326_rate0,
si5326_rate1 => si5326_rate1,
clk40_p => clk40_p,
clk40_n => clk40_n,
adc_cs => adc_spi_cs,
adc_mosi => adc_spi_mosi,
adc_miso => adc_spi_miso,
adc_sclk => adc_spi_sclk,
adc_d_p => adc_d_p,
adc_d_n => adc_d_n,
analog_scl => analog_scl,
analog_sda_o => analog_sda_o,
analog_sda_i => analog_sda,
sync_a_p => sync_a_p,
sync_a_n => sync_a_n,
sync_b_p => sync_b_p,
sync_b_n => sync_b_n,
-- sync_c_p => sync_c_p,
-- sync_c_n => sync_c_n,
clk_pll_p => clk_pll_p,
clk_pll_n => clk_pll_n
);
si5326_sda <= '0' when si5326_sda_o = '0' else 'Z';
analog_sda <= '0' when analog_sda_o = '0' else 'Z';
end rtl;
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
# Ethernet RefClk (125MHz)
create_clock -period 8.000 -name eth_refclk [get_ports eth_clk_p]
# Ethernet monitor clock hack (62.5MHz)
create_clock -period 16.000 -name clk_dc [get_pins infra/eth/dc_buf/O]
# System synchronous clock (40MHz nominal)
create_clock -period 25.000 -name clk40 [get_ports clk40_p]
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks clk40] -group [get_clocks -include_generated_clocks eth_refclk] -group [get_clocks -include_generated_clocks [get_clocks -filter {name =~ infra/eth/phy/*/RXOUTCLK}]] -group [get_clocks -include_generated_clocks [get_clocks -filter {name =~ infra/eth/phy/*/TXOUTCLK}]]
# Area constraints
create_pblock infra
resize_pblock [get_pblocks infra] -add {CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}
#add_cells_to_pblock [get_pblocks infra] [get_cells -quiet [list infra]]
create_pblock chans
resize_pblock [get_pblocks chans] -add {CLOCKREGION_X0Y3:CLOCKREGION_X0Y3}
#add_cells_to_pblock [get_pblocks chans] [get_cells -quiet [list payload]]
#remove_cells_from_pblock [get_pblocks chans] [get_cells payload/idelctrl]
set_property PACKAGE_PIN F6 [get_ports eth_clk_p]
set_property PACKAGE_PIN E6 [get_ports eth_clk_n]
set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells -hier -filter {name=~infra/eth/*/gtpe2_i}]
proc false_path {patt clk} {
set p [get_ports -quiet $patt -filter {direction != out}]
if {[llength $p] != 0} {
set_input_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != out}]
set_false_path -from [get_ports $patt -filter {direction != out}]
}
set p [get_ports -quiet $patt -filter {direction != in}]
if {[llength $p] != 0} {
set_output_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != in}]
set_false_path -to [get_ports $patt -filter {direction != in}]
}
}
set_property IOSTANDARD LVCMOS33 [get_ports {sfp_*}]
set_property PACKAGE_PIN W17 [get_ports {sfp_los}]
set_property PULLUP TRUE [get_ports {sfp_los}]
set_property PACKAGE_PIN V19 [get_ports {sfp_tx_disable}]
set_property PACKAGE_PIN Y18 [get_ports {sfp_scl}]
set_property PACKAGE_PIN U20 [get_ports {sfp_sda}]
false_path sfp_* eth_refclk
set_property IOSTANDARD LVCMOS33 [get_ports {leds[*]}]
set_property PACKAGE_PIN W22 [get_ports {leds[0]}]
set_property PACKAGE_PIN U22 [get_ports {leds[1]}]
false_path {leds[*]} eth_refclk
set_property IOSTANDARD LVCMOS25 [get_ports {leds_c[*]}]
set_property PACKAGE_PIN B13 [get_ports {leds_c[0]}]
set_property PACKAGE_PIN C13 [get_ports {leds_c[1]}]
set_property PACKAGE_PIN E17 [get_ports {leds_c[2]}]
set_property PACKAGE_PIN F16 [get_ports {leds_c[3]}]
false_path {leds_c[*]} eth_refclk
set_property IOSTANDARD LVCMOS25 [get_ports {dip_sw[*]}]
set_property PACKAGE_PIN D14 [get_ports {dip_sw[0]}]
set_property PACKAGE_PIN D15 [get_ports {dip_sw[1]}]
set_property PACKAGE_PIN E13 [get_ports {dip_sw[2]}]
set_property PACKAGE_PIN E14 [get_ports {dip_sw[3]}]
false_path {dip_sw[*]} eth_refclk
set_property IOSTANDARD LVCMOS33 [get_ports {si5326_*}]
set_property PACKAGE_PIN T18 [get_ports {si5326_scl}]
set_property PACKAGE_PIN R18 [get_ports {si5326_sda}]
set_property PACKAGE_PIN R19 [get_ports {si5326_rstn}]
set_property PACKAGE_PIN U18 [get_ports {si5326_phase_inc}]
set_property PACKAGE_PIN U17 [get_ports {si5326_phase_dec}]
set_property PACKAGE_PIN P16 [get_ports {si5326_clk1_validn}]
set_property PACKAGE_PIN R17 [get_ports {si5326_clk2_validn}]
set_property PACKAGE_PIN Y21 [get_ports {si5326_lol}]
set_property PACKAGE_PIN Y19 [get_ports {si5326_clk_sel}]
set_property PACKAGE_PIN P19 [get_ports {si5326_rate0}]
set_property PACKAGE_PIN U21 [get_ports {si5326_rate1}]
false_path {si5326_*} eth_refclk
#set_property IOSTANDARD LVCMOS33 [get_ports {analog_*}]
#set_property PACKAGE_PIN Y22 [get_ports {analog_scl}]
#set_property PACKAGE_PIN T21 [get_ports {analog_sda}]
#false_path {analog_*} eth_refclk
set_property IOSTANDARD LVCMOS25 [get_ports {analog_*}]
set_property PACKAGE_PIN H20 [get_ports {analog_scl}]
set_property PACKAGE_PIN J22 [get_ports {analog_sda}]
set_property PULLTYPE PULLUP [get_ports {analog_sda}]
false_path {analog_*} eth_refclk
set_property IOSTANDARD LVDS_25 [get_ports {clk40_*}]
set_property PACKAGE_PIN W11 [get_ports {clk40_p}]
set_property PACKAGE_PIN W12 [get_ports {clk40_n}]
set_property IOSTANDARD LVDS_25 [get_ports {sync_*}]
set_property PACKAGE_PIN J15 [get_ports {sync_a_p}]
set_property PACKAGE_PIN H15 [get_ports {sync_a_n}]
set_property PACKAGE_PIN G17 [get_ports {sync_b_p}]
set_property PACKAGE_PIN G18 [get_ports {sync_b_n}]
#set_property PACKAGE_PIN H17 [get_ports {sync_c_p}]
#set_property PACKAGE_PIN H18 [get_ports {sync_c_n}]
false_path {sync_*} eth_refclk
set_property IOSTANDARD LVDS_25 [get_ports {clk_pll_*}]
set_property PACKAGE_PIN E22 [get_ports {clk_pll_p}]
set_property PACKAGE_PIN D22 [get_ports {clk_pll_n}]
false_path {clk_pll_*} eth_refclk