Commit 69ffdae5 authored by Dave Newbold's avatar Dave Newbold
parents dc0cc16a ce7d37f0
......@@ -17,10 +17,10 @@ package ipbus_decode_sc_chan is
subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
function ipbus_sel_sc_chan(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-- START automatically generated VHDL the Fri Mar 17 13:58:05 2017
-- START automatically generated VHDL the Thu Jun 15 20:45:58 2017
constant N_SLV_CSR: integer := 0;
constant N_SLV_BUF: integer := 1;
constant N_SLV_PTRS: integer := 2;
constant N_SLV_ZS_THRESH: integer := 2;
constant N_SLV_TRIG_THRESH: integer := 3;
constant N_SLAVES: integer := 4;
-- END automatically generated VHDL
......@@ -34,13 +34,13 @@ package body ipbus_decode_sc_chan is
variable sel: ipbus_sel_t;
begin
-- START automatically generated VHDL the Fri Mar 17 13:58:05 2017
-- START automatically generated VHDL the Thu Jun 15 20:45:58 2017
if std_match(addr, "----------------------------000-") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000000 / mask 0x0000000e
elsif std_match(addr, "----------------------------001-") then
sel := ipbus_sel_t(to_unsigned(N_SLV_BUF, IPBUS_SEL_WIDTH)); -- buf / base 0x00000002 / mask 0x0000000e
elsif std_match(addr, "----------------------------010-") then
sel := ipbus_sel_t(to_unsigned(N_SLV_PTRS, IPBUS_SEL_WIDTH)); -- ptrs / base 0x00000004 / mask 0x0000000e
elsif std_match(addr, "----------------------------01--") then
sel := ipbus_sel_t(to_unsigned(N_SLV_ZS_THRESH, IPBUS_SEL_WIDTH)); -- zs_thresh / base 0x00000004 / mask 0x0000000c
elsif std_match(addr, "----------------------------10--") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TRIG_THRESH, IPBUS_SEL_WIDTH)); -- trig_thresh / base 0x00000008 / mask 0x0000000c
-- END automatically generated VHDL
......
-- Address decode logic for ipbus fabric
--
-- This file has been AUTOGENERATED from the address table - do not hand edit
--
-- We assume the synthesis tool is clever enough to recognise exclusive conditions
-- in the if statement.
--
-- Dave Newbold, February 2011
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package ipbus_decode_sc_daq is
constant IPBUS_SEL_WIDTH: positive := 5; -- Should be enough for now?
subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
function ipbus_sel_sc_daq(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-- START automatically generated VHDL the Thu Jun 15 20:45:58 2017
constant N_SLV_CHAN: integer := 0;
constant N_SLV_TIMING: integer := 1;
constant N_SLV_FAKE: integer := 2;
constant N_SLV_RTRIG: integer := 3;
constant N_SLV_TLINK: integer := 4;
constant N_SLV_TRIG: integer := 5;
constant N_SLV_ROC: integer := 6;
constant N_SLAVES: integer := 7;
-- END automatically generated VHDL
end ipbus_decode_sc_daq;
package body ipbus_decode_sc_daq is
function ipbus_sel_sc_daq(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
variable sel: ipbus_sel_t;
begin
-- START automatically generated VHDL the Thu Jun 15 20:45:58 2017
if std_match(addr, "-------------------------000----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CHAN, IPBUS_SEL_WIDTH)); -- chan / base 0x00000000 / mask 0x00000070
elsif std_match(addr, "-------------------------0010---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TIMING, IPBUS_SEL_WIDTH)); -- timing / base 0x00000010 / mask 0x00000078
elsif std_match(addr, "-------------------------0100---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_FAKE, IPBUS_SEL_WIDTH)); -- fake / base 0x00000020 / mask 0x00000078
elsif std_match(addr, "-------------------------0101---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_RTRIG, IPBUS_SEL_WIDTH)); -- rtrig / base 0x00000028 / mask 0x00000078
elsif std_match(addr, "-------------------------0110---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TLINK, IPBUS_SEL_WIDTH)); -- tlink / base 0x00000030 / mask 0x00000078
elsif std_match(addr, "-------------------------10-----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TRIG, IPBUS_SEL_WIDTH)); -- trig / base 0x00000040 / mask 0x00000060
elsif std_match(addr, "-------------------------11-----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_ROC, IPBUS_SEL_WIDTH)); -- roc / base 0x00000060 / mask 0x00000060
-- END automatically generated VHDL
else
sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
end if;
return sel;
end function ipbus_sel_sc_daq;
end ipbus_decode_sc_daq;
......@@ -17,15 +17,16 @@ package ipbus_decode_top is
subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
function ipbus_sel_top(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-- START automatically generated VHDL the Fri Mar 17 13:57:18 2017
-- START automatically generated VHDL the Thu Jun 8 10:16:08 2017
constant N_SLV_CSR: integer := 0;
constant N_SLV_CHAN: integer := 1;
constant N_SLV_IO: integer := 2;
constant N_SLV_TIMING: integer := 3;
constant N_SLV_TLINK: integer := 4;
constant N_SLV_TRIG: integer := 5;
constant N_SLV_ROC: integer := 6;
constant N_SLAVES: integer := 7;
constant N_SLV_FAKE: integer := 4;
constant N_SLV_TLINK: integer := 5;
constant N_SLV_TRIG: integer := 6;
constant N_SLV_ROC: integer := 7;
constant N_SLAVES: integer := 8;
-- END automatically generated VHDL
......@@ -37,7 +38,7 @@ package body ipbus_decode_top is
variable sel: ipbus_sel_t;
begin
-- START automatically generated VHDL the Fri Mar 17 13:57:18 2017
-- START automatically generated VHDL the Thu Jun 8 10:16:08 2017
if std_match(addr, "------------------------0000----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000000 / mask 0x000000f0
elsif std_match(addr, "------------------------0001----") then
......@@ -47,11 +48,13 @@ package body ipbus_decode_top is
elsif std_match(addr, "------------------------0100----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TIMING, IPBUS_SEL_WIDTH)); -- timing / base 0x00000040 / mask 0x000000f0
elsif std_match(addr, "------------------------0101----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TLINK, IPBUS_SEL_WIDTH)); -- tlink / base 0x00000050 / mask 0x000000f0
sel := ipbus_sel_t(to_unsigned(N_SLV_FAKE, IPBUS_SEL_WIDTH)); -- fake / base 0x00000050 / mask 0x000000f0
elsif std_match(addr, "------------------------0110----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TRIG, IPBUS_SEL_WIDTH)); -- trig / base 0x00000060 / mask 0x000000f0
sel := ipbus_sel_t(to_unsigned(N_SLV_TLINK, IPBUS_SEL_WIDTH)); -- tlink / base 0x00000060 / mask 0x000000f0
elsif std_match(addr, "------------------------100-----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_ROC, IPBUS_SEL_WIDTH)); -- roc / base 0x00000080 / mask 0x000000e0
sel := ipbus_sel_t(to_unsigned(N_SLV_TRIG, IPBUS_SEL_WIDTH)); -- trig / base 0x00000080 / mask 0x000000e0
elsif std_match(addr, "------------------------101-----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_ROC, IPBUS_SEL_WIDTH)); -- roc / base 0x000000a0 / mask 0x000000e0
-- END automatically generated VHDL
else
......
......@@ -17,15 +17,10 @@ package ipbus_decode_top_sim is
subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
function ipbus_sel_top_sim(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-- START automatically generated VHDL the Wed Jun 7 10:07:49 2017
-- START automatically generated VHDL the Thu Jun 15 20:48:09 2017
constant N_SLV_CSR: integer := 0;
constant N_SLV_CHAN: integer := 1;
constant N_SLV_TIMING: integer := 2;
constant N_SLV_FAKE: integer := 3;
constant N_SLV_TLINK: integer := 4;
constant N_SLV_TRIG: integer := 5;
constant N_SLV_ROC: integer := 6;
constant N_SLAVES: integer := 7;
constant N_SLV_DAQ: integer := 1;
constant N_SLAVES: integer := 2;
-- END automatically generated VHDL
......@@ -37,21 +32,11 @@ package body ipbus_decode_top_sim is
variable sel: ipbus_sel_t;
begin
-- START automatically generated VHDL the Wed Jun 7 10:07:49 2017
if std_match(addr, "------------------------0000----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000000 / mask 0x000000f0
elsif std_match(addr, "------------------------0001----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CHAN, IPBUS_SEL_WIDTH)); -- chan / base 0x00000010 / mask 0x000000f0
elsif std_match(addr, "------------------------0100----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TIMING, IPBUS_SEL_WIDTH)); -- timing / base 0x00000040 / mask 0x000000f0
elsif std_match(addr, "------------------------0101----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_FAKE, IPBUS_SEL_WIDTH)); -- fake / base 0x00000050 / mask 0x000000f0
elsif std_match(addr, "------------------------0110----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TLINK, IPBUS_SEL_WIDTH)); -- tlink / base 0x00000060 / mask 0x000000f0
elsif std_match(addr, "------------------------100-----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TRIG, IPBUS_SEL_WIDTH)); -- trig / base 0x00000080 / mask 0x000000e0
elsif std_match(addr, "------------------------101-----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_ROC, IPBUS_SEL_WIDTH)); -- roc / base 0x000000a0 / mask 0x000000e0
-- START automatically generated VHDL the Thu Jun 15 20:48:09 2017
if std_match(addr, "-----------------------0--------") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000000 / mask 0x00000100
elsif std_match(addr, "-----------------------1--------") then
sel := ipbus_sel_t(to_unsigned(N_SLV_DAQ, IPBUS_SEL_WIDTH)); -- daq / base 0x00000100 / mask 0x00000100
-- END automatically generated VHDL
else
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment