Commit 68d53c23 authored by Dave Newbold's avatar Dave Newbold

Adjusting timing startup

parent a6bbab04
......@@ -47,9 +47,9 @@ begin
if up = '1' then
if and_reduce(std_logic_vector(sctr(BLK_RADIX - 1 downto 0))) = '1' then
nzs_en <= '1';
elsif unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = NZS_BLKS and sctr(BLK_RADIX - 1 downto 0) = to_unsigned(ZS_DEL - 1, BLK_RADIX) then
elsif unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = NZS_BLKS + 1 and sctr(BLK_RADIX - 1 downto 0) = to_unsigned(ZS_DEL - 1, BLK_RADIX) then
zs_en <= '1';
elsif unsigned(sctr(7 + BLK_RADIX downto BLK_RADIX)) = NZS_BLKS + unsigned(zs_blks) then
elsif unsigned(sctr(7 + BLK_RADIX downto BLK_RADIX)) = NZS_BLKS + 1 + unsigned(zs_blks) then
trig_en <= '1';
end if;
end if;
......
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