Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
E
euro-adc-65m-14b-40cha-gw
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
eurocard
euro-adc-65m-14b-40cha
euro-adc-65m-14b-40cha-gw
Commits
68d53c23
Commit
68d53c23
authored
Apr 20, 2018
by
Dave Newbold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Adjusting timing startup
parent
a6bbab04
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
2 additions
and
2 deletions
+2
-2
sc_timing_startup.vhd
components/solid/firmware/hdl/sc_timing_startup.vhd
+2
-2
No files found.
components/solid/firmware/hdl/sc_timing_startup.vhd
View file @
68d53c23
...
...
@@ -47,9 +47,9 @@ begin
if
up
=
'1'
then
if
and_reduce
(
std_logic_vector
(
sctr
(
BLK_RADIX
-
1
downto
0
)))
=
'1'
then
nzs_en
<=
'1'
;
elsif
unsigned
(
sctr
(
3
+
BLK_RADIX
downto
BLK_RADIX
))
=
NZS_BLKS
and
sctr
(
BLK_RADIX
-
1
downto
0
)
=
to_unsigned
(
ZS_DEL
-
1
,
BLK_RADIX
)
then
elsif
unsigned
(
sctr
(
3
+
BLK_RADIX
downto
BLK_RADIX
))
=
NZS_BLKS
+
1
and
sctr
(
BLK_RADIX
-
1
downto
0
)
=
to_unsigned
(
ZS_DEL
-
1
,
BLK_RADIX
)
then
zs_en
<=
'1'
;
elsif
unsigned
(
sctr
(
7
+
BLK_RADIX
downto
BLK_RADIX
))
=
NZS_BLKS
+
unsigned
(
zs_blks
)
then
elsif
unsigned
(
sctr
(
7
+
BLK_RADIX
downto
BLK_RADIX
))
=
NZS_BLKS
+
1
+
unsigned
(
zs_blks
)
then
trig_en
<=
'1'
;
end
if
;
end
if
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment