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euro-adc-65m-14b-40cha-gw
Commit 5f924703 authored by Dave Newbold's avatar Dave Newbold
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Removing test outputs

parent f3e359aa
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Showing with 13 additions and 60 deletions
boards/pc051b/base_fw/synth/firmware/hdl/top_pc051b.vhd
View file @ 5f924703
...@@ -35,8 +35,8 @@ entity top is port( ...@@ -35,8 +35,8 @@ entity top is port(
sync_in: in std_logic; -- IO via timing interface sync_in: in std_logic; -- IO via timing interface
trig_in: in std_logic; trig_in: in std_logic;
trig_out: out std_logic; trig_out: out std_logic;
adc_d_p: inout std_logic_vector(63 downto 0); -- ADC serial input data adc_d_p: in std_logic_vector(63 downto 0); -- ADC serial input data
adc_d_n: inout std_logic_vector(63 downto 0) adc_d_n: in std_logic_vector(63 downto 0)
); );
end top; end top;
......
components/solid/addr_table/sc_chan.xml
View file @ 5f924703
...@@ -6,7 +6,6 @@ ...@@ -6,7 +6,6 @@
<node id="invert" mask="0x4"/> <node id="invert" mask="0x4"/>
<node id="mode" mask="0x10"/> <node id="mode" mask="0x10"/>
<node id="src" mask="0xc0"/> <node id="src" mask="0xc0"/>
<node id="tt" mask="0x100"/>
</node> </node>
<node id="stat" address="0x1"> <node id="stat" address="0x1">
<node id="cap_full" mask="0x1"/> <node id="cap_full" mask="0x1"/>
......
components/solid/firmware/hdl/sc_chan.vhd
View file @ 5f924703
...@@ -31,8 +31,8 @@ entity sc_chan is ...@@ -31,8 +31,8 @@ entity sc_chan is
rst40: in std_logic; rst40: in std_logic;
clk160: in std_logic; clk160: in std_logic;
clk280: in std_logic; clk280: in std_logic;
d_p: inout std_logic; d_p: in std_logic;
d_n: inout std_logic; d_n: in std_logic;
sync_ctrl: in std_logic_vector(3 downto 0); sync_ctrl: in std_logic_vector(3 downto 0);
zs_sel: in std_logic_vector(1 downto 0); zs_sel: in std_logic_vector(1 downto 0);
sctr: in std_logic_vector(47 downto 0); sctr: in std_logic_vector(47 downto 0);
...@@ -114,7 +114,6 @@ begin ...@@ -114,7 +114,6 @@ begin
ctrl_invert <= ctrl(0)(2); ctrl_invert <= ctrl(0)(2);
ctrl_mode <= ctrl(0)(4); ctrl_mode <= ctrl(0)(4);
ctrl_src <= ctrl(0)(7 downto 6); ctrl_src <= ctrl(0)(7 downto 6);
ctrl_tt <= not ctrl(0)(8);
slip <= sync_ctrl(0) and ctrl_en_sync; -- CDC slip <= sync_ctrl(0) and ctrl_en_sync; -- CDC
cap <= sync_ctrl(1) and ctrl_en_sync; -- CDC cap <= sync_ctrl(1) and ctrl_en_sync; -- CDC
...@@ -147,8 +146,7 @@ begin ...@@ -147,8 +146,7 @@ begin
slip => slip, slip => slip,
inc => inc, inc => inc,
cntout => cntout, cntout => cntout,
q => d_in, q => d_in
tt => ctrl_tt
); );
d_in_i <= d_in when ctrl_invert = '0' else not d_in; d_in_i <= d_in when ctrl_invert = '0' else not d_in;
......
components/solid/firmware/hdl/sc_channels.vhd
View file @ 5f924703
...@@ -27,8 +27,8 @@ entity sc_channels is ...@@ -27,8 +27,8 @@ entity sc_channels is
rst40: in std_logic; rst40: in std_logic;
clk160: in std_logic; clk160: in std_logic;
clk280: in std_logic; clk280: in std_logic;
d_p: inout std_logic_vector(N_CHAN - 1 downto 0); d_p: in std_logic_vector(N_CHAN - 1 downto 0);
d_n: inout std_logic_vector(N_CHAN - 1 downto 0); d_n: in std_logic_vector(N_CHAN - 1 downto 0);
sync_ctrl: in std_logic_vector(3 downto 0); sync_ctrl: in std_logic_vector(3 downto 0);
zs_sel: in std_logic_vector(1 downto 0); zs_sel: in std_logic_vector(1 downto 0);
sctr: in std_logic_vector(47 downto 0); sctr: in std_logic_vector(47 downto 0);
......
components/solid/firmware/hdl/sc_daq.vhd
View file @ 5f924703
...@@ -29,8 +29,8 @@ entity sc_daq is ...@@ -29,8 +29,8 @@ entity sc_daq is
led_out: out std_logic; led_out: out std_logic;
chan: in std_logic_vector(7 downto 0); chan: in std_logic_vector(7 downto 0);
chan_err: out std_logic; chan_err: out std_logic;
d_p: inout std_logic_vector(N_CHAN - 1 downto 0); d_p: in std_logic_vector(N_CHAN - 1 downto 0);
d_n: inout std_logic_vector(N_CHAN - 1 downto 0); d_n: in std_logic_vector(N_CHAN - 1 downto 0);
clk125: in std_logic; clk125: in std_logic;
rst125: in std_logic; rst125: in std_logic;
pllclk: in std_logic; pllclk: in std_logic;
......
components/solid/firmware/hdl/sc_input_serdes.vhd
View file @ 5f924703
...@@ -16,8 +16,8 @@ entity sc_input_serdes is ...@@ -16,8 +16,8 @@ entity sc_input_serdes is
clk: in std_logic; clk: in std_logic;
rst: in std_logic; rst: in std_logic;
clk_s: in std_logic; clk_s: in std_logic;
d_p: inout std_logic; d_p: in std_logic;
d_n: inout std_logic; d_n: in std_logic;
slip: in std_logic; slip: in std_logic;
inc: in std_logic; inc: in std_logic;
cntout: out std_logic_vector(4 downto 0); cntout: out std_logic_vector(4 downto 0);
...@@ -33,8 +33,6 @@ architecture rtl of sc_input_serdes is ...@@ -33,8 +33,6 @@ architecture rtl of sc_input_serdes is
signal d: std_logic_vector(13 downto 0); signal d: std_logic_vector(13 downto 0);
signal s1, s2: std_logic; signal s1, s2: std_logic;
signal clk_sb: std_logic; signal clk_sb: std_logic;
signal k: std_logic_vector(13 downto 0);
signal tq: std_logic;
begin begin
...@@ -139,39 +137,5 @@ begin ...@@ -139,39 +137,5 @@ begin
dynclkdivsel => '0', dynclkdivsel => '0',
dynclksel => '0' dynclksel => '0'
); );
-- Test logic
process(clk_s)
begin
if rising_edge(clk_s) then
if rst = '1' then
k <= "00000000000001";
else
k <= k(12 downto 0) & '0';
end if;
end if;
end process;
oreg: ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE"
)
port map(
q => tq,
c => clk_s,
ce => '1',
d1 => k(0),
d2 => k(1),
s => '0'
);
obuf: OBUFTDS
port map(
i => tq,
t => tt,
o => d_p,
ob => d_n
);
end rtl; end rtl;
projects/64ch/firmware/hdl/payload.vhd
View file @ 5f924703
...@@ -46,8 +46,8 @@ entity payload is ...@@ -46,8 +46,8 @@ entity payload is
sync_in: in std_logic; sync_in: in std_logic;
trig_in: in std_logic; trig_in: in std_logic;
trig_out: out std_logic; trig_out: out std_logic;
adc_d_p: inout std_logic_vector(63 downto 0); adc_d_p: in std_logic_vector(63 downto 0);
adc_d_n: inout std_logic_vector(63 downto 0) adc_d_n: in std_logic_vector(63 downto 0)
); );
end payload; end payload;
...@@ -183,14 +183,6 @@ begin ...@@ -183,14 +183,6 @@ begin
ib => adc_d_n(i), ib => adc_d_n(i),
o => open o => open
); );
bufo: OBUFTDS
port map(
i => '0',
t => '1',
o => adc_d_p(i),
ob => adc_p_n(i)
);
end generate; end generate;
......
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