Commit 5416d9d1 authored by Dave Newbold's avatar Dave Newbold

Adding LEDs; updating sim constants

parent 1b36f4f1
......@@ -85,7 +85,7 @@ begin
clk200 => clk200,
nuke => nuke,
soft_rst => soft_rst,
leds => leds(1 downto 0),
leds => leds,
debug => open,
mac_addr(47 downto 4) => MAC_ADDR(47 downto 4),
mac_addr(3 downto 0) => dip_sw,
......
......@@ -81,9 +81,9 @@ begin
q => led_p
);
leds <= ('0', onehz);
leds <= (led_p(0), onehz);
debug <= sfp_los & '0' & led_p(0) & (locked and onehz);
debug <= (others => '0');
-- Ethernet MAC core and PHY interface
......
......@@ -26,7 +26,7 @@ entity sc_daq is
sync_in: in std_logic;
trig_in: in std_logic;
trig_out: out std_logic;
led_out: out std_logic;
led_out: out std_logic_vector(2 downto 0);
chan: in std_logic_vector(7 downto 0);
chan_err: out std_logic;
d_p: in std_logic_vector(N_CHAN - 1 downto 0);
......@@ -52,7 +52,7 @@ architecture rtl of sc_daq is
signal zs_sel: std_logic_vector(1 downto 0);
signal chan_trig: sc_trig_array;
signal link_d, link_q: std_logic_vector(15 downto 0);
signal link_d_valid, link_q_valid, link_ack: std_logic;
signal link_d_valid, link_q_valid, link_ack, link_ok: std_logic;
signal ro_chan: std_logic_vector(7 downto 0);
signal ro_d, trig_d: std_logic_vector(31 downto 0);
signal ro_blkend, ro_empty, ro_ren, trig_sync, trig_blkend, trig_we, trig_roc_veto: std_logic;
......@@ -93,7 +93,7 @@ begin
clk280 => clk280,
sync_in => sync_in,
trig_in => trig_in,
led_out => led_out,
led => led_out(0),
sctr => sctr,
chan_sync_ctrl => sync_ctrl,
trig_en => trig_en,
......@@ -212,6 +212,7 @@ begin
ipb_out => ipbr(N_SLV_TLINK),
clk125 => clk125,
rst125 => rst125,
link_ok => link_ok,
clk40 => clk40_i,
rst40 => rst40_i,
d => link_d,
......@@ -243,5 +244,18 @@ begin
empty => ro_empty,
ren => ro_ren
);
-- LED
stretch: entity work.led_stretcher
generic map(
WIDTH => 2
)
port map(
clk => clk125,
d(0) => link_d_valid,
d(1) => link_ok,
q => led_out(2 downto 1)
);
end rtl;
......@@ -30,7 +30,7 @@ entity sc_timing is
clk280: out std_logic; -- chip 280MHz clock
sync_in: in std_logic; -- external sync signal in
trig_in: in std_logic; -- external trigger in
led_out: out std_logic; -- LED flash out
led: out std_logic; -- LED flash out
sctr: out std_logic_vector(47 downto 0); -- sample counter
chan_sync_ctrl: out std_logic_vector(3 downto 0); -- Timing signals to channels
trig_en: out std_logic;
......@@ -177,7 +177,7 @@ begin
end process;
sctr <= std_logic_vector(sctr_i);
led_out <= sctr_i(LED_BLK_RADIX + BLK_RADIX - 1);
led <= sctr_i(LED_BLK_RADIX + BLK_RADIX - 1) and not (wait_sync or sync_err);
-- Random number gen
......
......@@ -163,7 +163,7 @@ begin
qmask(0) => (N_TRG - 1 downto 0 => '1', others => '0')
);
trig_mask <= ctrl_mask(0)(N_TRG - 1 downto 0);
trig_mask <= ctrl_mask(0)(N_TRG - 1 downto 0);
ltrig: entity work.sc_local_trig
port map(
......
......@@ -17,6 +17,7 @@ entity sc_trig_link is
ipb_out: out ipb_rbus;
clk125: in std_logic;
rst125: in std_logic;
link_ok: out std_logic;
clk40: in std_logic;
rst40: in std_logic;
d: in std_logic_vector(15 downto 0);
......@@ -35,5 +36,6 @@ begin
ipb_out <= IPB_RBUS_NULL;
q <= (others => '0');
q_valid <= '0';
link_ok <= '0';
end rtl;
......@@ -102,7 +102,6 @@ begin
ctrl_rst_idelayctrl <= ctrl(0)(3);
ctrl_chan <= ctrl(0)(15 downto 8);
sel <= ctrl(0)(28 downto 24);
userleds <= ctrl(0)(31 downto 29);
-- Required for timing alignment at inputs
......@@ -149,6 +148,7 @@ begin
sync_in => sync_in,
trig_in => trig_in,
trig_out => trig_out,
led_out => userleds,
chan => ctrl_chan,
chan_err => chan_err,
d_p => adc_d_p,
......
......@@ -119,7 +119,7 @@ begin
ctrl_chan <= ctrl(0)(15 downto 8);
ctrl_board_id <= ctrl(0)(23 downto 16);
userleds <= "000" & led;
userleds(3) <= '0';
-- Required for timing alignment at inputs
......@@ -206,7 +206,7 @@ begin
sync_in => sync_in,
trig_in => trig_in,
trig_out => trig_out,
led_out => led,
led_out => userleds(2 downto 0),
chan => ctrl_chan,
chan_err => chan_err,
d_p => adc_d_p,
......
......@@ -16,6 +16,7 @@ package top_decl is
constant N_CHAN: integer := 2;
constant BLK_RADIX: integer := 8; -- 256 sample blocks
constant SUPERBLK_RADIX: integer := 5; -- Superblock is 32 blocks
constant LED_BLK_RADIX: integer := 18; -- Divisor for blocks-per-led-flash
constant BUF_RADIX: integer := 11; -- One BRAM for NZS / ZS buffer
constant NZS_BLKS: integer := 2; -- Reserve two blocks of space for NZS buffer
constant ZS_BLKS: integer := 2; -- Time window for ZS buffer
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment